Initial commit

Experiments/Shared/PC.v

@@ -0,0 +1,19 @@
+module PC(
+    input         clk,
+    input         rst,
+    input         pc_inc,
+    input  [31:0] offset,
+    output reg [31:0] PCdata
+);
+    always @(posedge clk or posedge rst) begin
+        if (rst) begin
+            PCdata <= 32'd0;
+        end else begin
+            if (pc_inc) begin
+                PCdata <= PCdata + 4; 
+            end else begin
+                PCdata <= PCdata + offset;
+            end
+        end
+    end
+endmodule