Initial commit
This commit is contained in:
5
Exp1-2-2/Exp1-2-2.runs/.jobs/vrs_config_1.xml
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5
Exp1-2-2/Exp1-2-2.runs/.jobs/vrs_config_1.xml
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@@ -0,0 +1,5 @@
|
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<?xml version="1.0"?>
|
||||
<Runs Version="1" Minor="0">
|
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<Run Id="synth_1" LaunchDir="F:/Schoolwork/DigitalLogic/Exp1-2-2/Exp1-2-2.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
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</Runs>
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|
||||
8
Exp1-2-2/Exp1-2-2.runs/.jobs/vrs_config_2.xml
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8
Exp1-2-2/Exp1-2-2.runs/.jobs/vrs_config_2.xml
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@@ -0,0 +1,8 @@
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<?xml version="1.0"?>
|
||||
<Runs Version="1" Minor="0">
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<Run Id="synth_1" LaunchDir="F:/Schoolwork/DigitalLogic/Exp1-2-2/Exp1-2-2.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
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||||
<Run Id="impl_1" LaunchDir="F:/Schoolwork/DigitalLogic/Exp1-2-2/Exp1-2-2.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="init_design" ToStepId="route_design">
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||||
<Parent Id="synth_1"/>
|
||||
</Run>
|
||||
</Runs>
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||||
|
||||
5
Exp1-2-2/Exp1-2-2.runs/.jobs/vrs_config_3.xml
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5
Exp1-2-2/Exp1-2-2.runs/.jobs/vrs_config_3.xml
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@@ -0,0 +1,5 @@
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<?xml version="1.0"?>
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||||
<Runs Version="1" Minor="0">
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||||
<Run Id="impl_1" LaunchDir="F:/Schoolwork/DigitalLogic/Exp1-2-2/Exp1-2-2.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="write_bitstream" ToStepId="write_bitstream"/>
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</Runs>
|
||||
|
||||
97
Exp1-2-2/Exp1-2-2.runs/impl_1/gen_run.xml
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97
Exp1-2-2/Exp1-2-2.runs/impl_1/gen_run.xml
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@@ -0,0 +1,97 @@
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<?xml version="1.0" encoding="UTF-8"?>
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<GenRun Id="impl_1" LaunchPart="xc7a35tcsg324-1" LaunchTime="1727320500">
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<File Type="PWROPT-DCP" Name="mux41_pwropt.dcp"/>
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||||
<File Type="ROUTE-PWR" Name="mux41_power_routed.rpt"/>
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||||
<File Type="PA-TCL" Name="mux41.tcl"/>
|
||||
<File Type="ROUTE-PWR-SUM" Name="mux41_power_summary_routed.pb"/>
|
||||
<File Type="REPORTS-TCL" Name="mux41_reports.tcl"/>
|
||||
<File Type="BG-DRC" Name="mux41.drc"/>
|
||||
<File Type="OPT-DCP" Name="mux41_opt.dcp"/>
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||||
<File Type="OPT-HWDEF" Name="mux41.hwdef"/>
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||||
<File Type="OPT-DRC" Name="mux41_drc_opted.rpt"/>
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||||
<File Type="PLACE-DCP" Name="mux41_placed.dcp"/>
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||||
<File Type="PLACE-IO" Name="mux41_io_placed.rpt"/>
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||||
<File Type="PLACE-UTIL" Name="mux41_utilization_placed.rpt"/>
|
||||
<File Type="PLACE-UTIL-PB" Name="mux41_utilization_placed.pb"/>
|
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<File Type="PLACE-CTRL" Name="mux41_control_sets_placed.rpt"/>
|
||||
<File Type="PLACE-PRE-SIMILARITY" Name="mux41_incremental_reuse_pre_placed.rpt"/>
|
||||
<File Type="POSTPLACE-PWROPT-DCP" Name="mux41_postplace_pwropt.dcp"/>
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||||
<File Type="PHYSOPT-DCP" Name="mux41_physopt.dcp"/>
|
||||
<File Type="BG-BIT" Name="mux41.bit"/>
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||||
<File Type="ROUTE-ERROR-DCP" Name="mux41_routed_error.dcp"/>
|
||||
<File Type="ROUTE-DCP" Name="mux41_routed.dcp"/>
|
||||
<File Type="ROUTE-BLACKBOX-DCP" Name="mux41_routed_bb.dcp"/>
|
||||
<File Type="ROUTE-DRC" Name="mux41_drc_routed.rpt"/>
|
||||
<File Type="ROUTE-DRC-PB" Name="mux41_drc_routed.pb"/>
|
||||
<File Type="BITSTR-MSK" Name="mux41.msk"/>
|
||||
<File Type="ROUTE-DRC-RPX" Name="mux41_drc_routed.rpx"/>
|
||||
<File Type="BG-BGN" Name="mux41.bgn"/>
|
||||
<File Type="ROUTE-METHODOLOGY-DRC" Name="mux41_methodology_drc_routed.rpt"/>
|
||||
<File Type="BITSTR-RBT" Name="mux41.rbt"/>
|
||||
<File Type="ROUTE-METHODOLOGY-DRC-RPX" Name="mux41_methodology_drc_routed.rpx"/>
|
||||
<File Type="BG-BIN" Name="mux41.bin"/>
|
||||
<File Type="ROUTE-METHODOLOGY-DRC-PB" Name="mux41_methodology_drc_routed.pb"/>
|
||||
<File Type="ROUTE-PWR-RPX" Name="mux41_power_routed.rpx"/>
|
||||
<File Type="ROUTE-STATUS" Name="mux41_route_status.rpt"/>
|
||||
<File Type="ROUTE-STATUS-PB" Name="mux41_route_status.pb"/>
|
||||
<File Type="ROUTE-TIMINGSUMMARY" Name="mux41_timing_summary_routed.rpt"/>
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||||
<File Type="ROUTE-TIMING-PB" Name="mux41_timing_summary_routed.pb"/>
|
||||
<File Type="ROUTE-TIMING-RPX" Name="mux41_timing_summary_routed.rpx"/>
|
||||
<File Type="RDI-RDI" Name="mux41.vdi"/>
|
||||
<File Type="ROUTE-CLK" Name="mux41_clock_utilization_routed.rpt"/>
|
||||
<File Type="POSTROUTE-PHYSOPT-DCP" Name="mux41_postroute_physopt.dcp"/>
|
||||
<File Type="POSTROUTE-PHYSOPT-BLACKBOX-DCP" Name="mux41_postroute_physopt_bb.dcp"/>
|
||||
<File Type="BITSTR-NKY" Name="mux41.nky"/>
|
||||
<File Type="BITSTR-BMM" Name="mux41_bd.bmm"/>
|
||||
<File Type="BITSTR-MMI" Name="mux41.mmi"/>
|
||||
<File Type="BITSTR-LTX" Name="mux41.ltx"/>
|
||||
<File Type="BITSTR-SYSDEF" Name="mux41.sysdef"/>
|
||||
<File Type="WBT-USG" Name="usage_statistics_webtalk.html"/>
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<FileSet Name="sources" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1">
|
||||
<Filter Type="Srcs"/>
|
||||
<File Path="$PSRCDIR/sources_1/new/mux21.v">
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||||
<FileInfo>
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||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
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||||
<Attr Name="UsedIn" Val="simulation"/>
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||||
</FileInfo>
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||||
</File>
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||||
<File Path="$PSRCDIR/sources_1/new/mux41.v">
|
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<FileInfo>
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<Attr Name="UsedIn" Val="synthesis"/>
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||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
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<Config>
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||||
<Option Name="DesignMode" Val="RTL"/>
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<Option Name="TopModule" Val="mux41"/>
|
||||
<Option Name="TopAutoSet" Val="TRUE"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="constrs_in" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1">
|
||||
<Filter Type="Constrs"/>
|
||||
<File Path="$PSRCDIR/constrs_1/new/mux41.xdc">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<Config>
|
||||
<Option Name="TargetConstrsFile" Val="$PSRCDIR/constrs_1/new/mux41.xdc"/>
|
||||
<Option Name="ConstrsType" Val="XDC"/>
|
||||
</Config>
|
||||
</FileSet>
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||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2018"/>
|
||||
<Step Id="init_design"/>
|
||||
<Step Id="opt_design"/>
|
||||
<Step Id="power_opt_design"/>
|
||||
<Step Id="place_design"/>
|
||||
<Step Id="post_place_power_opt_design"/>
|
||||
<Step Id="phys_opt_design"/>
|
||||
<Step Id="route_design"/>
|
||||
<Step Id="post_route_phys_opt_design"/>
|
||||
<Step Id="write_bitstream"/>
|
||||
</Strategy>
|
||||
</GenRun>
|
||||
9
Exp1-2-2/Exp1-2-2.runs/impl_1/htr.txt
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9
Exp1-2-2/Exp1-2-2.runs/impl_1/htr.txt
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@@ -0,0 +1,9 @@
|
||||
REM
|
||||
REM Vivado(TM)
|
||||
REM htr.txt: a Vivado-generated description of how-to-repeat the
|
||||
REM the basic steps of a run. Note that runme.bat/sh needs
|
||||
REM to be invoked for Vivado to track run status.
|
||||
REM Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
|
||||
REM
|
||||
|
||||
vivado -log mux41.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source mux41.tcl -notrace
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||||
BIN
Exp1-2-2/Exp1-2-2.runs/impl_1/init_design.pb
Normal file
BIN
Exp1-2-2/Exp1-2-2.runs/impl_1/init_design.pb
Normal file
Binary file not shown.
84
Exp1-2-2/Exp1-2-2.runs/impl_1/mux41.tcl
Normal file
84
Exp1-2-2/Exp1-2-2.runs/impl_1/mux41.tcl
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||||
#
|
||||
# Report generation script generated by Vivado
|
||||
#
|
||||
|
||||
proc create_report { reportName command } {
|
||||
set status "."
|
||||
append status $reportName ".fail"
|
||||
if { [file exists $status] } {
|
||||
eval file delete [glob $status]
|
||||
}
|
||||
send_msg_id runtcl-4 info "Executing : $command"
|
||||
set retval [eval catch { $command } msg]
|
||||
if { $retval != 0 } {
|
||||
set fp [open $status w]
|
||||
close $fp
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||||
send_msg_id runtcl-5 warning "$msg"
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||||
}
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||||
}
|
||||
proc start_step { step } {
|
||||
set stopFile ".stop.rst"
|
||||
if {[file isfile .stop.rst]} {
|
||||
puts ""
|
||||
puts "*** Halting run - EA reset detected ***"
|
||||
puts ""
|
||||
puts ""
|
||||
return -code error
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||||
}
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||||
set beginFile ".$step.begin.rst"
|
||||
set platform "$::tcl_platform(platform)"
|
||||
set user "$::tcl_platform(user)"
|
||||
set pid [pid]
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||||
set host ""
|
||||
if { [string equal $platform unix] } {
|
||||
if { [info exist ::env(HOSTNAME)] } {
|
||||
set host $::env(HOSTNAME)
|
||||
}
|
||||
} else {
|
||||
if { [info exist ::env(COMPUTERNAME)] } {
|
||||
set host $::env(COMPUTERNAME)
|
||||
}
|
||||
}
|
||||
set ch [open $beginFile w]
|
||||
puts $ch "<?xml version=\"1.0\"?>"
|
||||
puts $ch "<ProcessHandle Version=\"1\" Minor=\"0\">"
|
||||
puts $ch " <Process Command=\".planAhead.\" Owner=\"$user\" Host=\"$host\" Pid=\"$pid\">"
|
||||
puts $ch " </Process>"
|
||||
puts $ch "</ProcessHandle>"
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||||
close $ch
|
||||
}
|
||||
|
||||
proc end_step { step } {
|
||||
set endFile ".$step.end.rst"
|
||||
set ch [open $endFile w]
|
||||
close $ch
|
||||
}
|
||||
|
||||
proc step_failed { step } {
|
||||
set endFile ".$step.error.rst"
|
||||
set ch [open $endFile w]
|
||||
close $ch
|
||||
}
|
||||
|
||||
|
||||
start_step write_bitstream
|
||||
set ACTIVE_STEP write_bitstream
|
||||
set rc [catch {
|
||||
create_msg_db write_bitstream.pb
|
||||
set_param xicom.use_bs_reader 1
|
||||
open_checkpoint mux41_routed.dcp
|
||||
set_property webtalk.parent_dir F:/Schoolwork/DigitalLogic/Exp1-2-2/Exp1-2-2.cache/wt [current_project]
|
||||
catch { write_mem_info -force mux41.mmi }
|
||||
write_bitstream -force mux41.bit
|
||||
catch {write_debug_probes -quiet -force mux41}
|
||||
catch {file copy -force mux41.ltx debug_nets.ltx}
|
||||
close_msg_db -file write_bitstream.pb
|
||||
} RESULT]
|
||||
if {$rc} {
|
||||
step_failed write_bitstream
|
||||
return -code error $RESULT
|
||||
} else {
|
||||
end_step write_bitstream
|
||||
unset ACTIVE_STEP
|
||||
}
|
||||
|
||||
486
Exp1-2-2/Exp1-2-2.runs/impl_1/mux41.vdi
Normal file
486
Exp1-2-2/Exp1-2-2.runs/impl_1/mux41.vdi
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@@ -0,0 +1,486 @@
|
||||
#-----------------------------------------------------------
|
||||
# Vivado v2018.1 (64-bit)
|
||||
# SW Build 2188600 on Wed Apr 4 18:40:38 MDT 2018
|
||||
# IP Build 2185939 on Wed Apr 4 20:55:05 MDT 2018
|
||||
# Start of session at: Thu Sep 26 11:15:35 2024
|
||||
# Process ID: 5212
|
||||
# Current directory: F:/Schoolwork/DigitalLogic/Exp1-2-2/Exp1-2-2.runs/impl_1
|
||||
# Command line: vivado.exe -log mux41.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source mux41.tcl -notrace
|
||||
# Log file: F:/Schoolwork/DigitalLogic/Exp1-2-2/Exp1-2-2.runs/impl_1/mux41.vdi
|
||||
# Journal file: F:/Schoolwork/DigitalLogic/Exp1-2-2/Exp1-2-2.runs/impl_1\vivado.jou
|
||||
#-----------------------------------------------------------
|
||||
source mux41.tcl -notrace
|
||||
Command: link_design -top mux41 -part xc7a35tcsg324-1
|
||||
Design is defaulting to srcset: sources_1
|
||||
Design is defaulting to constrset: constrs_1
|
||||
INFO: [Netlist 29-17] Analyzing 6 Unisim elements for replacement
|
||||
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
|
||||
INFO: [Project 1-479] Netlist was created with Vivado 2018.1
|
||||
INFO: [Device 21-403] Loading part xc7a35tcsg324-1
|
||||
INFO: [Project 1-570] Preparing netlist for logic optimization
|
||||
Parsing XDC File [F:/Schoolwork/DigitalLogic/Exp1-2-2/Exp1-2-2.srcs/constrs_1/new/mux41.xdc]
|
||||
Finished Parsing XDC File [F:/Schoolwork/DigitalLogic/Exp1-2-2/Exp1-2-2.srcs/constrs_1/new/mux41.xdc]
|
||||
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
|
||||
INFO: [Project 1-111] Unisim Transformation Summary:
|
||||
No Unisim elements were transformed.
|
||||
|
||||
7 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
||||
link_design completed successfully
|
||||
link_design: Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 607.348 ; gain = 303.273
|
||||
Command: opt_design
|
||||
Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t'
|
||||
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t'
|
||||
Running DRC as a precondition to command opt_design
|
||||
|
||||
Starting DRC Task
|
||||
INFO: [DRC 23-27] Running DRC with 2 threads
|
||||
INFO: [Project 1-461] DRC finished with 0 Errors
|
||||
INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information.
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.075 . Memory (MB): peak = 609.430 ; gain = 2.082
|
||||
INFO: [Timing 38-35] Done setting XDC timing constraints.
|
||||
|
||||
Starting Logic Optimization Task
|
||||
|
||||
Phase 1 Retarget
|
||||
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
|
||||
INFO: [Opt 31-49] Retargeted 0 cell(s).
|
||||
Phase 1 Retarget | Checksum: 1e3e1106b
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 1130.844 ; gain = 0.000
|
||||
INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 0 cells
|
||||
|
||||
Phase 2 Constant propagation
|
||||
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
|
||||
Phase 2 Constant propagation | Checksum: 1e3e1106b
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.004 . Memory (MB): peak = 1130.844 ; gain = 0.000
|
||||
INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells
|
||||
|
||||
Phase 3 Sweep
|
||||
Phase 3 Sweep | Checksum: 1e3e1106b
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.004 . Memory (MB): peak = 1130.844 ; gain = 0.000
|
||||
INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 0 cells
|
||||
|
||||
Phase 4 BUFG optimization
|
||||
Phase 4 BUFG optimization | Checksum: 1e3e1106b
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.005 . Memory (MB): peak = 1130.844 ; gain = 0.000
|
||||
INFO: [Opt 31-389] Phase BUFG optimization created 0 cells and removed 0 cells
|
||||
|
||||
Phase 5 Shift Register Optimization
|
||||
Phase 5 Shift Register Optimization | Checksum: 1e3e1106b
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.005 . Memory (MB): peak = 1130.844 ; gain = 0.000
|
||||
INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells
|
||||
|
||||
Phase 6 Post Processing Netlist
|
||||
Phase 6 Post Processing Netlist | Checksum: 1e3e1106b
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.006 . Memory (MB): peak = 1130.844 ; gain = 0.000
|
||||
INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells
|
||||
|
||||
Starting Connectivity Check Task
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1130.844 ; gain = 0.000
|
||||
Ending Logic Optimization Task | Checksum: 1e3e1106b
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.007 . Memory (MB): peak = 1130.844 ; gain = 0.000
|
||||
|
||||
Starting Power Optimization Task
|
||||
INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns.
|
||||
Ending Power Optimization Task | Checksum: 1e3e1106b
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.006 . Memory (MB): peak = 1130.844 ; gain = 0.000
|
||||
INFO: [Common 17-83] Releasing license: Implementation
|
||||
23 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
||||
opt_design completed successfully
|
||||
opt_design: Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 1130.844 ; gain = 523.496
|
||||
INFO: [Timing 38-480] Writing timing data to binary archive.
|
||||
Writing placer database...
|
||||
Writing XDEF routing.
|
||||
Writing XDEF routing logical nets.
|
||||
Writing XDEF routing special nets.
|
||||
Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.019 . Memory (MB): peak = 1130.844 ; gain = 0.000
|
||||
INFO: [Common 17-1381] The checkpoint 'F:/Schoolwork/DigitalLogic/Exp1-2-2/Exp1-2-2.runs/impl_1/mux41_opt.dcp' has been generated.
|
||||
INFO: [runtcl-4] Executing : report_drc -file mux41_drc_opted.rpt -pb mux41_drc_opted.pb -rpx mux41_drc_opted.rpx
|
||||
Command: report_drc -file mux41_drc_opted.rpt -pb mux41_drc_opted.pb -rpx mux41_drc_opted.rpx
|
||||
INFO: [IP_Flow 19-234] Refreshing IP repositories
|
||||
INFO: [IP_Flow 19-1704] No user IP repositories specified
|
||||
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'D:/Xilinx/Vivado/2018.1/data/ip'.
|
||||
INFO: [DRC 23-27] Running DRC with 2 threads
|
||||
INFO: [Coretcl 2-168] The results of DRC are in file F:/Schoolwork/DigitalLogic/Exp1-2-2/Exp1-2-2.runs/impl_1/mux41_drc_opted.rpt.
|
||||
report_drc completed successfully
|
||||
Command: place_design
|
||||
Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t'
|
||||
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t'
|
||||
INFO: [DRC 23-27] Running DRC with 2 threads
|
||||
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
|
||||
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
|
||||
Running DRC as a precondition to command place_design
|
||||
INFO: [DRC 23-27] Running DRC with 2 threads
|
||||
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
|
||||
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
|
||||
|
||||
Starting Placer Task
|
||||
INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 2 CPUs
|
||||
|
||||
Phase 1 Placer Initialization
|
||||
|
||||
Phase 1.1 Placer Initialization Netlist Sorting
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1133.133 ; gain = 0.000
|
||||
Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 12f477d06
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 1133.133 ; gain = 0.000
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1133.133 ; gain = 0.000
|
||||
|
||||
Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device
|
||||
INFO: [Timing 38-35] Done setting XDC timing constraints.
|
||||
Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 12f477d06
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.362 . Memory (MB): peak = 1157.184 ; gain = 24.051
|
||||
|
||||
Phase 1.3 Build Placer Netlist Model
|
||||
Phase 1.3 Build Placer Netlist Model | Checksum: 15695016a
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.370 . Memory (MB): peak = 1157.184 ; gain = 24.051
|
||||
|
||||
Phase 1.4 Constrain Clocks/Macros
|
||||
Phase 1.4 Constrain Clocks/Macros | Checksum: 15695016a
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.371 . Memory (MB): peak = 1157.184 ; gain = 24.051
|
||||
Phase 1 Placer Initialization | Checksum: 15695016a
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.372 . Memory (MB): peak = 1157.184 ; gain = 24.051
|
||||
|
||||
Phase 2 Global Placement
|
||||
Phase 2 Global Placement | Checksum: 224a517c0
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.529 . Memory (MB): peak = 1157.184 ; gain = 24.051
|
||||
|
||||
Phase 3 Detail Placement
|
||||
|
||||
Phase 3.1 Commit Multi Column Macros
|
||||
Phase 3.1 Commit Multi Column Macros | Checksum: 224a517c0
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.531 . Memory (MB): peak = 1157.184 ; gain = 24.051
|
||||
|
||||
Phase 3.2 Commit Most Macros & LUTRAMs
|
||||
Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 1c91896ab
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.539 . Memory (MB): peak = 1157.184 ; gain = 24.051
|
||||
|
||||
Phase 3.3 Area Swap Optimization
|
||||
Phase 3.3 Area Swap Optimization | Checksum: 15116b443
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.543 . Memory (MB): peak = 1157.184 ; gain = 24.051
|
||||
|
||||
Phase 3.4 Pipeline Register Optimization
|
||||
Phase 3.4 Pipeline Register Optimization | Checksum: 15116b443
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.543 . Memory (MB): peak = 1157.184 ; gain = 24.051
|
||||
|
||||
Phase 3.5 Small Shape Detail Placement
|
||||
Phase 3.5 Small Shape Detail Placement | Checksum: 1ac5be8b3
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.717 . Memory (MB): peak = 1157.637 ; gain = 24.504
|
||||
|
||||
Phase 3.6 Re-assign LUT pins
|
||||
Phase 3.6 Re-assign LUT pins | Checksum: 1ac5be8b3
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.717 . Memory (MB): peak = 1157.637 ; gain = 24.504
|
||||
|
||||
Phase 3.7 Pipeline Register Optimization
|
||||
Phase 3.7 Pipeline Register Optimization | Checksum: 1ac5be8b3
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.718 . Memory (MB): peak = 1157.637 ; gain = 24.504
|
||||
Phase 3 Detail Placement | Checksum: 1ac5be8b3
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.718 . Memory (MB): peak = 1157.637 ; gain = 24.504
|
||||
|
||||
Phase 4 Post Placement Optimization and Clean-Up
|
||||
|
||||
Phase 4.1 Post Commit Optimization
|
||||
Phase 4.1 Post Commit Optimization | Checksum: 1ac5be8b3
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.719 . Memory (MB): peak = 1157.637 ; gain = 24.504
|
||||
|
||||
Phase 4.2 Post Placement Cleanup
|
||||
Phase 4.2 Post Placement Cleanup | Checksum: 1ac5be8b3
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.722 . Memory (MB): peak = 1157.637 ; gain = 24.504
|
||||
|
||||
Phase 4.3 Placer Reporting
|
||||
Phase 4.3 Placer Reporting | Checksum: 1ac5be8b3
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.722 . Memory (MB): peak = 1157.637 ; gain = 24.504
|
||||
|
||||
Phase 4.4 Final Placement Cleanup
|
||||
Phase 4.4 Final Placement Cleanup | Checksum: 1ac5be8b3
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.722 . Memory (MB): peak = 1157.637 ; gain = 24.504
|
||||
Phase 4 Post Placement Optimization and Clean-Up | Checksum: 1ac5be8b3
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.723 . Memory (MB): peak = 1157.637 ; gain = 24.504
|
||||
Ending Placer Task | Checksum: c54a07d5
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.724 . Memory (MB): peak = 1157.637 ; gain = 24.504
|
||||
INFO: [Common 17-83] Releasing license: Implementation
|
||||
41 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
||||
place_design completed successfully
|
||||
INFO: [Timing 38-480] Writing timing data to binary archive.
|
||||
Writing placer database...
|
||||
Writing XDEF routing.
|
||||
Writing XDEF routing logical nets.
|
||||
Writing XDEF routing special nets.
|
||||
Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.023 . Memory (MB): peak = 1159.215 ; gain = 1.578
|
||||
INFO: [Common 17-1381] The checkpoint 'F:/Schoolwork/DigitalLogic/Exp1-2-2/Exp1-2-2.runs/impl_1/mux41_placed.dcp' has been generated.
|
||||
INFO: [runtcl-4] Executing : report_io -file mux41_io_placed.rpt
|
||||
report_io: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.027 . Memory (MB): peak = 1170.410 ; gain = 0.000
|
||||
INFO: [runtcl-4] Executing : report_utilization -file mux41_utilization_placed.rpt -pb mux41_utilization_placed.pb
|
||||
report_utilization: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.014 . Memory (MB): peak = 1170.410 ; gain = 0.000
|
||||
INFO: [runtcl-4] Executing : report_control_sets -verbose -file mux41_control_sets_placed.rpt
|
||||
report_control_sets: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1170.410 ; gain = 0.000
|
||||
Command: route_design
|
||||
Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t'
|
||||
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t'
|
||||
Running DRC as a precondition to command route_design
|
||||
INFO: [DRC 23-27] Running DRC with 2 threads
|
||||
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
|
||||
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
|
||||
|
||||
|
||||
Starting Routing Task
|
||||
INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 2 CPUs
|
||||
Checksum: PlaceDB: 153ecc1f ConstDB: 0 ShapeSum: b00b3bb6 RouteDB: 0
|
||||
|
||||
Phase 1 Build RT Design
|
||||
Phase 1 Build RT Design | Checksum: c648ffa8
|
||||
|
||||
Time (s): cpu = 00:00:14 ; elapsed = 00:00:12 . Memory (MB): peak = 1285.832 ; gain = 115.422
|
||||
Post Restoration Checksum: NetGraph: 2d5288c5 NumContArr: 98f676e3 Constraints: 0 Timing: 0
|
||||
|
||||
Phase 2 Router Initialization
|
||||
INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode.
|
||||
|
||||
Phase 2.1 Fix Topology Constraints
|
||||
Phase 2.1 Fix Topology Constraints | Checksum: c648ffa8
|
||||
|
||||
Time (s): cpu = 00:00:14 ; elapsed = 00:00:12 . Memory (MB): peak = 1291.891 ; gain = 121.480
|
||||
|
||||
Phase 2.2 Pre Route Cleanup
|
||||
Phase 2.2 Pre Route Cleanup | Checksum: c648ffa8
|
||||
|
||||
Time (s): cpu = 00:00:14 ; elapsed = 00:00:12 . Memory (MB): peak = 1291.891 ; gain = 121.480
|
||||
Phase 2 Router Initialization | Checksum: c648ffa8
|
||||
|
||||
Time (s): cpu = 00:00:14 ; elapsed = 00:00:12 . Memory (MB): peak = 1293.652 ; gain = 123.242
|
||||
|
||||
Phase 3 Initial Routing
|
||||
Phase 3 Initial Routing | Checksum: 973162bc
|
||||
|
||||
Time (s): cpu = 00:00:14 ; elapsed = 00:00:13 . Memory (MB): peak = 1293.652 ; gain = 123.242
|
||||
|
||||
Phase 4 Rip-up And Reroute
|
||||
|
||||
Phase 4.1 Global Iteration 0
|
||||
Number of Nodes with overlaps = 1
|
||||
Number of Nodes with overlaps = 0
|
||||
Phase 4.1 Global Iteration 0 | Checksum: d4df4150
|
||||
|
||||
Time (s): cpu = 00:00:14 ; elapsed = 00:00:13 . Memory (MB): peak = 1293.688 ; gain = 123.277
|
||||
Phase 4 Rip-up And Reroute | Checksum: d4df4150
|
||||
|
||||
Time (s): cpu = 00:00:14 ; elapsed = 00:00:13 . Memory (MB): peak = 1293.688 ; gain = 123.277
|
||||
|
||||
Phase 5 Delay and Skew Optimization
|
||||
Phase 5 Delay and Skew Optimization | Checksum: d4df4150
|
||||
|
||||
Time (s): cpu = 00:00:14 ; elapsed = 00:00:13 . Memory (MB): peak = 1293.688 ; gain = 123.277
|
||||
|
||||
Phase 6 Post Hold Fix
|
||||
|
||||
Phase 6.1 Hold Fix Iter
|
||||
Phase 6.1 Hold Fix Iter | Checksum: d4df4150
|
||||
|
||||
Time (s): cpu = 00:00:14 ; elapsed = 00:00:13 . Memory (MB): peak = 1293.688 ; gain = 123.277
|
||||
Phase 6 Post Hold Fix | Checksum: d4df4150
|
||||
|
||||
Time (s): cpu = 00:00:14 ; elapsed = 00:00:13 . Memory (MB): peak = 1293.688 ; gain = 123.277
|
||||
|
||||
Phase 7 Route finalize
|
||||
|
||||
Router Utilization Summary
|
||||
Global Vertical Routing Utilization = 0.00398629 %
|
||||
Global Horizontal Routing Utilization = 0.00221239 %
|
||||
Routable Net Status*
|
||||
*Does not include unroutable nets such as driverless and loadless.
|
||||
Run report_route_status for detailed report.
|
||||
Number of Failed Nets = 0
|
||||
Number of Unrouted Nets = 0
|
||||
Number of Partially Routed Nets = 0
|
||||
Number of Node Overlaps = 0
|
||||
|
||||
Congestion Report
|
||||
North Dir 1x1 Area, Max Cong = 1.8018%, No Congested Regions.
|
||||
South Dir 1x1 Area, Max Cong = 5.40541%, No Congested Regions.
|
||||
East Dir 1x1 Area, Max Cong = 2.94118%, No Congested Regions.
|
||||
West Dir 1x1 Area, Max Cong = 2.94118%, No Congested Regions.
|
||||
|
||||
------------------------------
|
||||
Reporting congestion hotspots
|
||||
------------------------------
|
||||
Direction: North
|
||||
----------------
|
||||
Congested clusters found at Level 0
|
||||
Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0
|
||||
Direction: South
|
||||
----------------
|
||||
Congested clusters found at Level 0
|
||||
Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0
|
||||
Direction: East
|
||||
----------------
|
||||
Congested clusters found at Level 0
|
||||
Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0
|
||||
Direction: West
|
||||
----------------
|
||||
Congested clusters found at Level 0
|
||||
Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0
|
||||
|
||||
Phase 7 Route finalize | Checksum: d4df4150
|
||||
|
||||
Time (s): cpu = 00:00:14 ; elapsed = 00:00:13 . Memory (MB): peak = 1293.688 ; gain = 123.277
|
||||
|
||||
Phase 8 Verifying routed nets
|
||||
|
||||
Verification completed successfully
|
||||
Phase 8 Verifying routed nets | Checksum: d4df4150
|
||||
|
||||
Time (s): cpu = 00:00:14 ; elapsed = 00:00:13 . Memory (MB): peak = 1295.703 ; gain = 125.293
|
||||
|
||||
Phase 9 Depositing Routes
|
||||
Phase 9 Depositing Routes | Checksum: d4df4150
|
||||
|
||||
Time (s): cpu = 00:00:14 ; elapsed = 00:00:13 . Memory (MB): peak = 1295.703 ; gain = 125.293
|
||||
INFO: [Route 35-16] Router Completed Successfully
|
||||
|
||||
Time (s): cpu = 00:00:14 ; elapsed = 00:00:13 . Memory (MB): peak = 1295.703 ; gain = 125.293
|
||||
|
||||
Routing Is Done.
|
||||
INFO: [Common 17-83] Releasing license: Implementation
|
||||
54 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
||||
route_design completed successfully
|
||||
route_design: Time (s): cpu = 00:00:14 ; elapsed = 00:00:13 . Memory (MB): peak = 1295.703 ; gain = 125.293
|
||||
INFO: [Timing 38-480] Writing timing data to binary archive.
|
||||
Writing placer database...
|
||||
Writing XDEF routing.
|
||||
Writing XDEF routing logical nets.
|
||||
Writing XDEF routing special nets.
|
||||
Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.024 . Memory (MB): peak = 1295.703 ; gain = 0.000
|
||||
INFO: [Common 17-1381] The checkpoint 'F:/Schoolwork/DigitalLogic/Exp1-2-2/Exp1-2-2.runs/impl_1/mux41_routed.dcp' has been generated.
|
||||
INFO: [runtcl-4] Executing : report_drc -file mux41_drc_routed.rpt -pb mux41_drc_routed.pb -rpx mux41_drc_routed.rpx
|
||||
Command: report_drc -file mux41_drc_routed.rpt -pb mux41_drc_routed.pb -rpx mux41_drc_routed.rpx
|
||||
INFO: [DRC 23-27] Running DRC with 2 threads
|
||||
INFO: [Coretcl 2-168] The results of DRC are in file F:/Schoolwork/DigitalLogic/Exp1-2-2/Exp1-2-2.runs/impl_1/mux41_drc_routed.rpt.
|
||||
report_drc completed successfully
|
||||
INFO: [runtcl-4] Executing : report_methodology -file mux41_methodology_drc_routed.rpt -pb mux41_methodology_drc_routed.pb -rpx mux41_methodology_drc_routed.rpx
|
||||
Command: report_methodology -file mux41_methodology_drc_routed.rpt -pb mux41_methodology_drc_routed.pb -rpx mux41_methodology_drc_routed.rpx
|
||||
INFO: [Timing 38-35] Done setting XDC timing constraints.
|
||||
INFO: [Timing 38-35] Done setting XDC timing constraints.
|
||||
INFO: [DRC 23-133] Running Methodology with 2 threads
|
||||
INFO: [Coretcl 2-1520] The results of Report Methodology are in file F:/Schoolwork/DigitalLogic/Exp1-2-2/Exp1-2-2.runs/impl_1/mux41_methodology_drc_routed.rpt.
|
||||
report_methodology completed successfully
|
||||
INFO: [runtcl-4] Executing : report_power -file mux41_power_routed.rpt -pb mux41_power_summary_routed.pb -rpx mux41_power_routed.rpx
|
||||
Command: report_power -file mux41_power_routed.rpt -pb mux41_power_summary_routed.pb -rpx mux41_power_routed.rpx
|
||||
WARNING: [Power 33-232] No user defined clocks were found in the design!
|
||||
Resolution: Please specify clocks using create_clock/create_generated_clock for sequential elements. For pure combinatorial circuits, please specify a virtual clock, otherwise the vectorless estimation might be inaccurate
|
||||
INFO: [Timing 38-35] Done setting XDC timing constraints.
|
||||
Running Vector-less Activity Propagation...
|
||||
|
||||
Finished Running Vector-less Activity Propagation
|
||||
66 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
||||
report_power completed successfully
|
||||
INFO: [runtcl-4] Executing : report_route_status -file mux41_route_status.rpt -pb mux41_route_status.pb
|
||||
INFO: [runtcl-4] Executing : report_timing_summary -max_paths 10 -file mux41_timing_summary_routed.rpt -pb mux41_timing_summary_routed.pb -rpx mux41_timing_summary_routed.rpx -warn_on_violation
|
||||
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max, Timing Stage: Requireds.
|
||||
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs
|
||||
WARNING: [Timing 38-313] There are no user specified timing constraints. Timing constraints are needed for proper timing analysis.
|
||||
INFO: [runtcl-4] Executing : report_incremental_reuse -file mux41_incremental_reuse_routed.rpt
|
||||
INFO: [Vivado_Tcl 4-545] No incremental reuse to report, no incremental placement and routing data was found.
|
||||
INFO: [runtcl-4] Executing : report_clock_utilization -file mux41_clock_utilization_routed.rpt
|
||||
INFO: [runtcl-4] Executing : report_bus_skew -warn_on_violation -file route_report_bus_skew_0.rpt -rpx route_report_bus_skew_0.rpx
|
||||
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max, Timing Stage: Requireds.
|
||||
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs
|
||||
INFO: [Common 17-206] Exiting Vivado at Thu Sep 26 11:16:12 2024...
|
||||
#-----------------------------------------------------------
|
||||
# Vivado v2018.1 (64-bit)
|
||||
# SW Build 2188600 on Wed Apr 4 18:40:38 MDT 2018
|
||||
# IP Build 2185939 on Wed Apr 4 20:55:05 MDT 2018
|
||||
# Start of session at: Thu Sep 26 11:16:29 2024
|
||||
# Process ID: 4044
|
||||
# Current directory: F:/Schoolwork/DigitalLogic/Exp1-2-2/Exp1-2-2.runs/impl_1
|
||||
# Command line: vivado.exe -log mux41.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source mux41.tcl -notrace
|
||||
# Log file: F:/Schoolwork/DigitalLogic/Exp1-2-2/Exp1-2-2.runs/impl_1/mux41.vdi
|
||||
# Journal file: F:/Schoolwork/DigitalLogic/Exp1-2-2/Exp1-2-2.runs/impl_1\vivado.jou
|
||||
#-----------------------------------------------------------
|
||||
source mux41.tcl -notrace
|
||||
Command: open_checkpoint mux41_routed.dcp
|
||||
|
||||
Starting open_checkpoint Task
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.023 . Memory (MB): peak = 241.633 ; gain = 0.000
|
||||
INFO: [Netlist 29-17] Analyzing 6 Unisim elements for replacement
|
||||
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
|
||||
INFO: [Project 1-479] Netlist was created with Vivado 2018.1
|
||||
INFO: [Device 21-403] Loading part xc7a35tcsg324-1
|
||||
INFO: [Project 1-570] Preparing netlist for logic optimization
|
||||
INFO: [Timing 38-478] Restoring timing data from binary archive.
|
||||
INFO: [Timing 38-479] Binary timing data restore complete.
|
||||
INFO: [Project 1-856] Restoring constraints from binary archive.
|
||||
INFO: [Project 1-853] Binary constraint restore complete.
|
||||
Reading XDEF placement.
|
||||
Reading placer database...
|
||||
Reading XDEF routing.
|
||||
Read XDEF File: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.059 . Memory (MB): peak = 1117.176 ; gain = 0.000
|
||||
Restored from archive | CPU: 0.000000 secs | Memory: 0.000000 MB |
|
||||
Finished XDEF File Restore: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.059 . Memory (MB): peak = 1117.176 ; gain = 0.000
|
||||
INFO: [Project 1-111] Unisim Transformation Summary:
|
||||
No Unisim elements were transformed.
|
||||
|
||||
INFO: [Project 1-604] Checkpoint was created with Vivado v2018.1 (64-bit) build 2188600
|
||||
open_checkpoint: Time (s): cpu = 00:00:13 ; elapsed = 00:00:17 . Memory (MB): peak = 1117.176 ; gain = 884.664
|
||||
Command: write_bitstream -force mux41.bit
|
||||
Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t'
|
||||
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t'
|
||||
Running DRC as a precondition to command write_bitstream
|
||||
INFO: [IP_Flow 19-234] Refreshing IP repositories
|
||||
INFO: [IP_Flow 19-1704] No user IP repositories specified
|
||||
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'D:/Xilinx/Vivado/2018.1/data/ip'.
|
||||
INFO: [DRC 23-27] Running DRC with 2 threads
|
||||
WARNING: [DRC CFGBVS-1] Missing CFGBVS and CONFIG_VOLTAGE Design Properties: Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design. Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0. It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax:
|
||||
|
||||
set_property CFGBVS value1 [current_design]
|
||||
#where value1 is either VCCO or GND
|
||||
|
||||
set_property CONFIG_VOLTAGE value2 [current_design]
|
||||
#where value2 is the voltage provided to configuration bank 0
|
||||
|
||||
Refer to the device configuration user guide for more information.
|
||||
INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings
|
||||
INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information.
|
||||
INFO: [Designutils 20-2272] Running write_bitstream with 2 threads.
|
||||
Loading data files...
|
||||
Loading site data...
|
||||
Loading route data...
|
||||
Processing options...
|
||||
Creating bitmap...
|
||||
Creating bitstream...
|
||||
Writing bitstream ./mux41.bit...
|
||||
INFO: [Vivado 12-1842] Bitgen Completed Successfully.
|
||||
INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory.
|
||||
INFO: [Common 17-83] Releasing license: Implementation
|
||||
22 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
||||
write_bitstream completed successfully
|
||||
write_bitstream: Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 1581.559 ; gain = 464.383
|
||||
INFO: [Common 17-206] Exiting Vivado at Thu Sep 26 11:16:58 2024...
|
||||
415
Exp1-2-2/Exp1-2-2.runs/impl_1/mux41_5212.backup.vdi
Normal file
415
Exp1-2-2/Exp1-2-2.runs/impl_1/mux41_5212.backup.vdi
Normal file
@@ -0,0 +1,415 @@
|
||||
#-----------------------------------------------------------
|
||||
# Vivado v2018.1 (64-bit)
|
||||
# SW Build 2188600 on Wed Apr 4 18:40:38 MDT 2018
|
||||
# IP Build 2185939 on Wed Apr 4 20:55:05 MDT 2018
|
||||
# Start of session at: Thu Sep 26 11:15:35 2024
|
||||
# Process ID: 5212
|
||||
# Current directory: F:/Schoolwork/DigitalLogic/Exp1-2-2/Exp1-2-2.runs/impl_1
|
||||
# Command line: vivado.exe -log mux41.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source mux41.tcl -notrace
|
||||
# Log file: F:/Schoolwork/DigitalLogic/Exp1-2-2/Exp1-2-2.runs/impl_1/mux41.vdi
|
||||
# Journal file: F:/Schoolwork/DigitalLogic/Exp1-2-2/Exp1-2-2.runs/impl_1\vivado.jou
|
||||
#-----------------------------------------------------------
|
||||
source mux41.tcl -notrace
|
||||
Command: link_design -top mux41 -part xc7a35tcsg324-1
|
||||
Design is defaulting to srcset: sources_1
|
||||
Design is defaulting to constrset: constrs_1
|
||||
INFO: [Netlist 29-17] Analyzing 6 Unisim elements for replacement
|
||||
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
|
||||
INFO: [Project 1-479] Netlist was created with Vivado 2018.1
|
||||
INFO: [Device 21-403] Loading part xc7a35tcsg324-1
|
||||
INFO: [Project 1-570] Preparing netlist for logic optimization
|
||||
Parsing XDC File [F:/Schoolwork/DigitalLogic/Exp1-2-2/Exp1-2-2.srcs/constrs_1/new/mux41.xdc]
|
||||
Finished Parsing XDC File [F:/Schoolwork/DigitalLogic/Exp1-2-2/Exp1-2-2.srcs/constrs_1/new/mux41.xdc]
|
||||
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
|
||||
INFO: [Project 1-111] Unisim Transformation Summary:
|
||||
No Unisim elements were transformed.
|
||||
|
||||
7 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
||||
link_design completed successfully
|
||||
link_design: Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 607.348 ; gain = 303.273
|
||||
Command: opt_design
|
||||
Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t'
|
||||
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t'
|
||||
Running DRC as a precondition to command opt_design
|
||||
|
||||
Starting DRC Task
|
||||
INFO: [DRC 23-27] Running DRC with 2 threads
|
||||
INFO: [Project 1-461] DRC finished with 0 Errors
|
||||
INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information.
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.075 . Memory (MB): peak = 609.430 ; gain = 2.082
|
||||
INFO: [Timing 38-35] Done setting XDC timing constraints.
|
||||
|
||||
Starting Logic Optimization Task
|
||||
|
||||
Phase 1 Retarget
|
||||
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
|
||||
INFO: [Opt 31-49] Retargeted 0 cell(s).
|
||||
Phase 1 Retarget | Checksum: 1e3e1106b
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 1130.844 ; gain = 0.000
|
||||
INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 0 cells
|
||||
|
||||
Phase 2 Constant propagation
|
||||
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
|
||||
Phase 2 Constant propagation | Checksum: 1e3e1106b
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.004 . Memory (MB): peak = 1130.844 ; gain = 0.000
|
||||
INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells
|
||||
|
||||
Phase 3 Sweep
|
||||
Phase 3 Sweep | Checksum: 1e3e1106b
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.004 . Memory (MB): peak = 1130.844 ; gain = 0.000
|
||||
INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 0 cells
|
||||
|
||||
Phase 4 BUFG optimization
|
||||
Phase 4 BUFG optimization | Checksum: 1e3e1106b
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.005 . Memory (MB): peak = 1130.844 ; gain = 0.000
|
||||
INFO: [Opt 31-389] Phase BUFG optimization created 0 cells and removed 0 cells
|
||||
|
||||
Phase 5 Shift Register Optimization
|
||||
Phase 5 Shift Register Optimization | Checksum: 1e3e1106b
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.005 . Memory (MB): peak = 1130.844 ; gain = 0.000
|
||||
INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells
|
||||
|
||||
Phase 6 Post Processing Netlist
|
||||
Phase 6 Post Processing Netlist | Checksum: 1e3e1106b
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.006 . Memory (MB): peak = 1130.844 ; gain = 0.000
|
||||
INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells
|
||||
|
||||
Starting Connectivity Check Task
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1130.844 ; gain = 0.000
|
||||
Ending Logic Optimization Task | Checksum: 1e3e1106b
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.007 . Memory (MB): peak = 1130.844 ; gain = 0.000
|
||||
|
||||
Starting Power Optimization Task
|
||||
INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns.
|
||||
Ending Power Optimization Task | Checksum: 1e3e1106b
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.006 . Memory (MB): peak = 1130.844 ; gain = 0.000
|
||||
INFO: [Common 17-83] Releasing license: Implementation
|
||||
23 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
||||
opt_design completed successfully
|
||||
opt_design: Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 1130.844 ; gain = 523.496
|
||||
INFO: [Timing 38-480] Writing timing data to binary archive.
|
||||
Writing placer database...
|
||||
Writing XDEF routing.
|
||||
Writing XDEF routing logical nets.
|
||||
Writing XDEF routing special nets.
|
||||
Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.019 . Memory (MB): peak = 1130.844 ; gain = 0.000
|
||||
INFO: [Common 17-1381] The checkpoint 'F:/Schoolwork/DigitalLogic/Exp1-2-2/Exp1-2-2.runs/impl_1/mux41_opt.dcp' has been generated.
|
||||
INFO: [runtcl-4] Executing : report_drc -file mux41_drc_opted.rpt -pb mux41_drc_opted.pb -rpx mux41_drc_opted.rpx
|
||||
Command: report_drc -file mux41_drc_opted.rpt -pb mux41_drc_opted.pb -rpx mux41_drc_opted.rpx
|
||||
INFO: [IP_Flow 19-234] Refreshing IP repositories
|
||||
INFO: [IP_Flow 19-1704] No user IP repositories specified
|
||||
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'D:/Xilinx/Vivado/2018.1/data/ip'.
|
||||
INFO: [DRC 23-27] Running DRC with 2 threads
|
||||
INFO: [Coretcl 2-168] The results of DRC are in file F:/Schoolwork/DigitalLogic/Exp1-2-2/Exp1-2-2.runs/impl_1/mux41_drc_opted.rpt.
|
||||
report_drc completed successfully
|
||||
Command: place_design
|
||||
Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t'
|
||||
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t'
|
||||
INFO: [DRC 23-27] Running DRC with 2 threads
|
||||
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
|
||||
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
|
||||
Running DRC as a precondition to command place_design
|
||||
INFO: [DRC 23-27] Running DRC with 2 threads
|
||||
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
|
||||
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
|
||||
|
||||
Starting Placer Task
|
||||
INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 2 CPUs
|
||||
|
||||
Phase 1 Placer Initialization
|
||||
|
||||
Phase 1.1 Placer Initialization Netlist Sorting
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1133.133 ; gain = 0.000
|
||||
Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 12f477d06
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 1133.133 ; gain = 0.000
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1133.133 ; gain = 0.000
|
||||
|
||||
Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device
|
||||
INFO: [Timing 38-35] Done setting XDC timing constraints.
|
||||
Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 12f477d06
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.362 . Memory (MB): peak = 1157.184 ; gain = 24.051
|
||||
|
||||
Phase 1.3 Build Placer Netlist Model
|
||||
Phase 1.3 Build Placer Netlist Model | Checksum: 15695016a
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.370 . Memory (MB): peak = 1157.184 ; gain = 24.051
|
||||
|
||||
Phase 1.4 Constrain Clocks/Macros
|
||||
Phase 1.4 Constrain Clocks/Macros | Checksum: 15695016a
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.371 . Memory (MB): peak = 1157.184 ; gain = 24.051
|
||||
Phase 1 Placer Initialization | Checksum: 15695016a
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.372 . Memory (MB): peak = 1157.184 ; gain = 24.051
|
||||
|
||||
Phase 2 Global Placement
|
||||
Phase 2 Global Placement | Checksum: 224a517c0
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.529 . Memory (MB): peak = 1157.184 ; gain = 24.051
|
||||
|
||||
Phase 3 Detail Placement
|
||||
|
||||
Phase 3.1 Commit Multi Column Macros
|
||||
Phase 3.1 Commit Multi Column Macros | Checksum: 224a517c0
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.531 . Memory (MB): peak = 1157.184 ; gain = 24.051
|
||||
|
||||
Phase 3.2 Commit Most Macros & LUTRAMs
|
||||
Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 1c91896ab
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.539 . Memory (MB): peak = 1157.184 ; gain = 24.051
|
||||
|
||||
Phase 3.3 Area Swap Optimization
|
||||
Phase 3.3 Area Swap Optimization | Checksum: 15116b443
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.543 . Memory (MB): peak = 1157.184 ; gain = 24.051
|
||||
|
||||
Phase 3.4 Pipeline Register Optimization
|
||||
Phase 3.4 Pipeline Register Optimization | Checksum: 15116b443
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.543 . Memory (MB): peak = 1157.184 ; gain = 24.051
|
||||
|
||||
Phase 3.5 Small Shape Detail Placement
|
||||
Phase 3.5 Small Shape Detail Placement | Checksum: 1ac5be8b3
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.717 . Memory (MB): peak = 1157.637 ; gain = 24.504
|
||||
|
||||
Phase 3.6 Re-assign LUT pins
|
||||
Phase 3.6 Re-assign LUT pins | Checksum: 1ac5be8b3
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.717 . Memory (MB): peak = 1157.637 ; gain = 24.504
|
||||
|
||||
Phase 3.7 Pipeline Register Optimization
|
||||
Phase 3.7 Pipeline Register Optimization | Checksum: 1ac5be8b3
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.718 . Memory (MB): peak = 1157.637 ; gain = 24.504
|
||||
Phase 3 Detail Placement | Checksum: 1ac5be8b3
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.718 . Memory (MB): peak = 1157.637 ; gain = 24.504
|
||||
|
||||
Phase 4 Post Placement Optimization and Clean-Up
|
||||
|
||||
Phase 4.1 Post Commit Optimization
|
||||
Phase 4.1 Post Commit Optimization | Checksum: 1ac5be8b3
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.719 . Memory (MB): peak = 1157.637 ; gain = 24.504
|
||||
|
||||
Phase 4.2 Post Placement Cleanup
|
||||
Phase 4.2 Post Placement Cleanup | Checksum: 1ac5be8b3
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.722 . Memory (MB): peak = 1157.637 ; gain = 24.504
|
||||
|
||||
Phase 4.3 Placer Reporting
|
||||
Phase 4.3 Placer Reporting | Checksum: 1ac5be8b3
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.722 . Memory (MB): peak = 1157.637 ; gain = 24.504
|
||||
|
||||
Phase 4.4 Final Placement Cleanup
|
||||
Phase 4.4 Final Placement Cleanup | Checksum: 1ac5be8b3
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.722 . Memory (MB): peak = 1157.637 ; gain = 24.504
|
||||
Phase 4 Post Placement Optimization and Clean-Up | Checksum: 1ac5be8b3
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.723 . Memory (MB): peak = 1157.637 ; gain = 24.504
|
||||
Ending Placer Task | Checksum: c54a07d5
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.724 . Memory (MB): peak = 1157.637 ; gain = 24.504
|
||||
INFO: [Common 17-83] Releasing license: Implementation
|
||||
41 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
||||
place_design completed successfully
|
||||
INFO: [Timing 38-480] Writing timing data to binary archive.
|
||||
Writing placer database...
|
||||
Writing XDEF routing.
|
||||
Writing XDEF routing logical nets.
|
||||
Writing XDEF routing special nets.
|
||||
Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.023 . Memory (MB): peak = 1159.215 ; gain = 1.578
|
||||
INFO: [Common 17-1381] The checkpoint 'F:/Schoolwork/DigitalLogic/Exp1-2-2/Exp1-2-2.runs/impl_1/mux41_placed.dcp' has been generated.
|
||||
INFO: [runtcl-4] Executing : report_io -file mux41_io_placed.rpt
|
||||
report_io: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.027 . Memory (MB): peak = 1170.410 ; gain = 0.000
|
||||
INFO: [runtcl-4] Executing : report_utilization -file mux41_utilization_placed.rpt -pb mux41_utilization_placed.pb
|
||||
report_utilization: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.014 . Memory (MB): peak = 1170.410 ; gain = 0.000
|
||||
INFO: [runtcl-4] Executing : report_control_sets -verbose -file mux41_control_sets_placed.rpt
|
||||
report_control_sets: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1170.410 ; gain = 0.000
|
||||
Command: route_design
|
||||
Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t'
|
||||
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t'
|
||||
Running DRC as a precondition to command route_design
|
||||
INFO: [DRC 23-27] Running DRC with 2 threads
|
||||
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
|
||||
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
|
||||
|
||||
|
||||
Starting Routing Task
|
||||
INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 2 CPUs
|
||||
Checksum: PlaceDB: 153ecc1f ConstDB: 0 ShapeSum: b00b3bb6 RouteDB: 0
|
||||
|
||||
Phase 1 Build RT Design
|
||||
Phase 1 Build RT Design | Checksum: c648ffa8
|
||||
|
||||
Time (s): cpu = 00:00:14 ; elapsed = 00:00:12 . Memory (MB): peak = 1285.832 ; gain = 115.422
|
||||
Post Restoration Checksum: NetGraph: 2d5288c5 NumContArr: 98f676e3 Constraints: 0 Timing: 0
|
||||
|
||||
Phase 2 Router Initialization
|
||||
INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode.
|
||||
|
||||
Phase 2.1 Fix Topology Constraints
|
||||
Phase 2.1 Fix Topology Constraints | Checksum: c648ffa8
|
||||
|
||||
Time (s): cpu = 00:00:14 ; elapsed = 00:00:12 . Memory (MB): peak = 1291.891 ; gain = 121.480
|
||||
|
||||
Phase 2.2 Pre Route Cleanup
|
||||
Phase 2.2 Pre Route Cleanup | Checksum: c648ffa8
|
||||
|
||||
Time (s): cpu = 00:00:14 ; elapsed = 00:00:12 . Memory (MB): peak = 1291.891 ; gain = 121.480
|
||||
Phase 2 Router Initialization | Checksum: c648ffa8
|
||||
|
||||
Time (s): cpu = 00:00:14 ; elapsed = 00:00:12 . Memory (MB): peak = 1293.652 ; gain = 123.242
|
||||
|
||||
Phase 3 Initial Routing
|
||||
Phase 3 Initial Routing | Checksum: 973162bc
|
||||
|
||||
Time (s): cpu = 00:00:14 ; elapsed = 00:00:13 . Memory (MB): peak = 1293.652 ; gain = 123.242
|
||||
|
||||
Phase 4 Rip-up And Reroute
|
||||
|
||||
Phase 4.1 Global Iteration 0
|
||||
Number of Nodes with overlaps = 1
|
||||
Number of Nodes with overlaps = 0
|
||||
Phase 4.1 Global Iteration 0 | Checksum: d4df4150
|
||||
|
||||
Time (s): cpu = 00:00:14 ; elapsed = 00:00:13 . Memory (MB): peak = 1293.688 ; gain = 123.277
|
||||
Phase 4 Rip-up And Reroute | Checksum: d4df4150
|
||||
|
||||
Time (s): cpu = 00:00:14 ; elapsed = 00:00:13 . Memory (MB): peak = 1293.688 ; gain = 123.277
|
||||
|
||||
Phase 5 Delay and Skew Optimization
|
||||
Phase 5 Delay and Skew Optimization | Checksum: d4df4150
|
||||
|
||||
Time (s): cpu = 00:00:14 ; elapsed = 00:00:13 . Memory (MB): peak = 1293.688 ; gain = 123.277
|
||||
|
||||
Phase 6 Post Hold Fix
|
||||
|
||||
Phase 6.1 Hold Fix Iter
|
||||
Phase 6.1 Hold Fix Iter | Checksum: d4df4150
|
||||
|
||||
Time (s): cpu = 00:00:14 ; elapsed = 00:00:13 . Memory (MB): peak = 1293.688 ; gain = 123.277
|
||||
Phase 6 Post Hold Fix | Checksum: d4df4150
|
||||
|
||||
Time (s): cpu = 00:00:14 ; elapsed = 00:00:13 . Memory (MB): peak = 1293.688 ; gain = 123.277
|
||||
|
||||
Phase 7 Route finalize
|
||||
|
||||
Router Utilization Summary
|
||||
Global Vertical Routing Utilization = 0.00398629 %
|
||||
Global Horizontal Routing Utilization = 0.00221239 %
|
||||
Routable Net Status*
|
||||
*Does not include unroutable nets such as driverless and loadless.
|
||||
Run report_route_status for detailed report.
|
||||
Number of Failed Nets = 0
|
||||
Number of Unrouted Nets = 0
|
||||
Number of Partially Routed Nets = 0
|
||||
Number of Node Overlaps = 0
|
||||
|
||||
Congestion Report
|
||||
North Dir 1x1 Area, Max Cong = 1.8018%, No Congested Regions.
|
||||
South Dir 1x1 Area, Max Cong = 5.40541%, No Congested Regions.
|
||||
East Dir 1x1 Area, Max Cong = 2.94118%, No Congested Regions.
|
||||
West Dir 1x1 Area, Max Cong = 2.94118%, No Congested Regions.
|
||||
|
||||
------------------------------
|
||||
Reporting congestion hotspots
|
||||
------------------------------
|
||||
Direction: North
|
||||
----------------
|
||||
Congested clusters found at Level 0
|
||||
Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0
|
||||
Direction: South
|
||||
----------------
|
||||
Congested clusters found at Level 0
|
||||
Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0
|
||||
Direction: East
|
||||
----------------
|
||||
Congested clusters found at Level 0
|
||||
Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0
|
||||
Direction: West
|
||||
----------------
|
||||
Congested clusters found at Level 0
|
||||
Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0
|
||||
|
||||
Phase 7 Route finalize | Checksum: d4df4150
|
||||
|
||||
Time (s): cpu = 00:00:14 ; elapsed = 00:00:13 . Memory (MB): peak = 1293.688 ; gain = 123.277
|
||||
|
||||
Phase 8 Verifying routed nets
|
||||
|
||||
Verification completed successfully
|
||||
Phase 8 Verifying routed nets | Checksum: d4df4150
|
||||
|
||||
Time (s): cpu = 00:00:14 ; elapsed = 00:00:13 . Memory (MB): peak = 1295.703 ; gain = 125.293
|
||||
|
||||
Phase 9 Depositing Routes
|
||||
Phase 9 Depositing Routes | Checksum: d4df4150
|
||||
|
||||
Time (s): cpu = 00:00:14 ; elapsed = 00:00:13 . Memory (MB): peak = 1295.703 ; gain = 125.293
|
||||
INFO: [Route 35-16] Router Completed Successfully
|
||||
|
||||
Time (s): cpu = 00:00:14 ; elapsed = 00:00:13 . Memory (MB): peak = 1295.703 ; gain = 125.293
|
||||
|
||||
Routing Is Done.
|
||||
INFO: [Common 17-83] Releasing license: Implementation
|
||||
54 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
||||
route_design completed successfully
|
||||
route_design: Time (s): cpu = 00:00:14 ; elapsed = 00:00:13 . Memory (MB): peak = 1295.703 ; gain = 125.293
|
||||
INFO: [Timing 38-480] Writing timing data to binary archive.
|
||||
Writing placer database...
|
||||
Writing XDEF routing.
|
||||
Writing XDEF routing logical nets.
|
||||
Writing XDEF routing special nets.
|
||||
Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.024 . Memory (MB): peak = 1295.703 ; gain = 0.000
|
||||
INFO: [Common 17-1381] The checkpoint 'F:/Schoolwork/DigitalLogic/Exp1-2-2/Exp1-2-2.runs/impl_1/mux41_routed.dcp' has been generated.
|
||||
INFO: [runtcl-4] Executing : report_drc -file mux41_drc_routed.rpt -pb mux41_drc_routed.pb -rpx mux41_drc_routed.rpx
|
||||
Command: report_drc -file mux41_drc_routed.rpt -pb mux41_drc_routed.pb -rpx mux41_drc_routed.rpx
|
||||
INFO: [DRC 23-27] Running DRC with 2 threads
|
||||
INFO: [Coretcl 2-168] The results of DRC are in file F:/Schoolwork/DigitalLogic/Exp1-2-2/Exp1-2-2.runs/impl_1/mux41_drc_routed.rpt.
|
||||
report_drc completed successfully
|
||||
INFO: [runtcl-4] Executing : report_methodology -file mux41_methodology_drc_routed.rpt -pb mux41_methodology_drc_routed.pb -rpx mux41_methodology_drc_routed.rpx
|
||||
Command: report_methodology -file mux41_methodology_drc_routed.rpt -pb mux41_methodology_drc_routed.pb -rpx mux41_methodology_drc_routed.rpx
|
||||
INFO: [Timing 38-35] Done setting XDC timing constraints.
|
||||
INFO: [Timing 38-35] Done setting XDC timing constraints.
|
||||
INFO: [DRC 23-133] Running Methodology with 2 threads
|
||||
INFO: [Coretcl 2-1520] The results of Report Methodology are in file F:/Schoolwork/DigitalLogic/Exp1-2-2/Exp1-2-2.runs/impl_1/mux41_methodology_drc_routed.rpt.
|
||||
report_methodology completed successfully
|
||||
INFO: [runtcl-4] Executing : report_power -file mux41_power_routed.rpt -pb mux41_power_summary_routed.pb -rpx mux41_power_routed.rpx
|
||||
Command: report_power -file mux41_power_routed.rpt -pb mux41_power_summary_routed.pb -rpx mux41_power_routed.rpx
|
||||
WARNING: [Power 33-232] No user defined clocks were found in the design!
|
||||
Resolution: Please specify clocks using create_clock/create_generated_clock for sequential elements. For pure combinatorial circuits, please specify a virtual clock, otherwise the vectorless estimation might be inaccurate
|
||||
INFO: [Timing 38-35] Done setting XDC timing constraints.
|
||||
Running Vector-less Activity Propagation...
|
||||
|
||||
Finished Running Vector-less Activity Propagation
|
||||
66 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
||||
report_power completed successfully
|
||||
INFO: [runtcl-4] Executing : report_route_status -file mux41_route_status.rpt -pb mux41_route_status.pb
|
||||
INFO: [runtcl-4] Executing : report_timing_summary -max_paths 10 -file mux41_timing_summary_routed.rpt -pb mux41_timing_summary_routed.pb -rpx mux41_timing_summary_routed.rpx -warn_on_violation
|
||||
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max, Timing Stage: Requireds.
|
||||
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs
|
||||
WARNING: [Timing 38-313] There are no user specified timing constraints. Timing constraints are needed for proper timing analysis.
|
||||
INFO: [runtcl-4] Executing : report_incremental_reuse -file mux41_incremental_reuse_routed.rpt
|
||||
INFO: [Vivado_Tcl 4-545] No incremental reuse to report, no incremental placement and routing data was found.
|
||||
INFO: [runtcl-4] Executing : report_clock_utilization -file mux41_clock_utilization_routed.rpt
|
||||
INFO: [runtcl-4] Executing : report_bus_skew -warn_on_violation -file route_report_bus_skew_0.rpt -rpx route_report_bus_skew_0.rpx
|
||||
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max, Timing Stage: Requireds.
|
||||
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs
|
||||
INFO: [Common 17-206] Exiting Vivado at Thu Sep 26 11:16:12 2024...
|
||||
@@ -0,0 +1,92 @@
|
||||
Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
|
||||
------------------------------------------------------------------------------------
|
||||
| Tool Version : Vivado v.2018.1 (win64) Build 2188600 Wed Apr 4 18:40:38 MDT 2018
|
||||
| Date : Thu Sep 26 11:16:12 2024
|
||||
| Host : W10-20240912132 running 64-bit major release (build 9200)
|
||||
| Command : report_clock_utilization -file mux41_clock_utilization_routed.rpt
|
||||
| Design : mux41
|
||||
| Device : 7a35t-csg324
|
||||
| Speed File : -1 PRODUCTION 1.21 2018-02-08
|
||||
------------------------------------------------------------------------------------
|
||||
|
||||
Clock Utilization Report
|
||||
|
||||
Table of Contents
|
||||
-----------------
|
||||
1. Clock Primitive Utilization
|
||||
2. Global Clock Resources
|
||||
3. Global Clock Source Details
|
||||
4. Clock Regions: Key Resource Utilization
|
||||
5. Clock Regions : Global Clock Summary
|
||||
|
||||
1. Clock Primitive Utilization
|
||||
------------------------------
|
||||
|
||||
+----------+------+-----------+-----+--------------+--------+
|
||||
| Type | Used | Available | LOC | Clock Region | Pblock |
|
||||
+----------+------+-----------+-----+--------------+--------+
|
||||
| BUFGCTRL | 0 | 32 | 0 | 0 | 0 |
|
||||
| BUFH | 0 | 72 | 0 | 0 | 0 |
|
||||
| BUFIO | 0 | 20 | 0 | 0 | 0 |
|
||||
| BUFMR | 0 | 10 | 0 | 0 | 0 |
|
||||
| BUFR | 0 | 20 | 0 | 0 | 0 |
|
||||
| MMCM | 0 | 5 | 0 | 0 | 0 |
|
||||
| PLL | 0 | 5 | 0 | 0 | 0 |
|
||||
+----------+------+-----------+-----+--------------+--------+
|
||||
|
||||
|
||||
2. Global Clock Resources
|
||||
-------------------------
|
||||
|
||||
+-----------+-----------+-----------------+------------+------+--------------+-------------------+-------------+-----------------+--------------+-------+------------+-----+
|
||||
| Global Id | Source Id | Driver Type/Pin | Constraint | Site | Clock Region | Load Clock Region | Clock Loads | Non-Clock Loads | Clock Period | Clock | Driver Pin | Net |
|
||||
+-----------+-----------+-----------------+------------+------+--------------+-------------------+-------------+-----------------+--------------+-------+------------+-----+
|
||||
* Clock Loads column represents the clock pin loads (pin count)
|
||||
** Non-Clock Loads column represents the non-clock pin loads (pin count)
|
||||
|
||||
|
||||
3. Global Clock Source Details
|
||||
------------------------------
|
||||
|
||||
+-----------+-----------+-----------------+------------+------+--------------+-------------+-----------------+---------------------+--------------+------------+-----+
|
||||
| Source Id | Global Id | Driver Type/Pin | Constraint | Site | Clock Region | Clock Loads | Non-Clock Loads | Source Clock Period | Source Clock | Driver Pin | Net |
|
||||
+-----------+-----------+-----------------+------------+------+--------------+-------------+-----------------+---------------------+--------------+------------+-----+
|
||||
* Clock Loads column represents the clock pin loads (pin count)
|
||||
** Non-Clock Loads column represents the non-clock pin loads (pin count)
|
||||
|
||||
|
||||
4. Clock Regions: Key Resource Utilization
|
||||
------------------------------------------
|
||||
|
||||
+-------------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+
|
||||
| | Global Clock | BUFRs | BUFMRs | BUFIOs | MMCM | PLL | GT | PCI | ILOGIC | OLOGIC | FF | LUTM | RAMB18 | RAMB36 | DSP48E2 |
|
||||
+-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+
|
||||
| Clock Region Name | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail |
|
||||
+-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+
|
||||
| X0Y0 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 1200 | 0 | 400 | 0 | 20 | 0 | 10 | 0 | 20 |
|
||||
| X1Y0 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 1500 | 0 | 450 | 0 | 40 | 0 | 20 | 0 | 20 |
|
||||
| X0Y1 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 1200 | 0 | 400 | 0 | 20 | 0 | 10 | 0 | 20 |
|
||||
| X1Y1 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 1500 | 0 | 450 | 0 | 40 | 0 | 20 | 0 | 20 |
|
||||
| X0Y2 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 1800 | 0 | 400 | 0 | 20 | 0 | 10 | 0 | 20 |
|
||||
| X1Y2 | 0 | 12 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 950 | 0 | 300 | 0 | 10 | 0 | 5 | 0 | 20 |
|
||||
+-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+
|
||||
* Global Clock column represents track count; while other columns represents cell counts
|
||||
|
||||
|
||||
5. Clock Regions : Global Clock Summary
|
||||
---------------------------------------
|
||||
|
||||
All Modules
|
||||
+----+----+----+
|
||||
| | X0 | X1 |
|
||||
+----+----+----+
|
||||
| Y2 | 0 | 0 |
|
||||
| Y1 | 0 | 0 |
|
||||
| Y0 | 0 | 0 |
|
||||
+----+----+----+
|
||||
|
||||
|
||||
|
||||
# Location of IO Primitives which is load of clock spine
|
||||
|
||||
# Location of clock ports
|
||||
61
Exp1-2-2/Exp1-2-2.runs/impl_1/mux41_control_sets_placed.rpt
Normal file
61
Exp1-2-2/Exp1-2-2.runs/impl_1/mux41_control_sets_placed.rpt
Normal file
@@ -0,0 +1,61 @@
|
||||
Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
|
||||
------------------------------------------------------------------------------------
|
||||
| Tool Version : Vivado v.2018.1 (win64) Build 2188600 Wed Apr 4 18:40:38 MDT 2018
|
||||
| Date : Thu Sep 26 11:15:58 2024
|
||||
| Host : W10-20240912132 running 64-bit major release (build 9200)
|
||||
| Command : report_control_sets -verbose -file mux41_control_sets_placed.rpt
|
||||
| Design : mux41
|
||||
| Device : xc7a35t
|
||||
------------------------------------------------------------------------------------
|
||||
|
||||
Control Set Information
|
||||
|
||||
Table of Contents
|
||||
-----------------
|
||||
1. Summary
|
||||
2. Histogram
|
||||
3. Flip-Flop Distribution
|
||||
4. Detailed Control Set Information
|
||||
|
||||
1. Summary
|
||||
----------
|
||||
|
||||
+----------------------------------------------------------+-------+
|
||||
| Status | Count |
|
||||
+----------------------------------------------------------+-------+
|
||||
| Number of unique control sets | 0 |
|
||||
| Unused register locations in slices containing registers | 0 |
|
||||
+----------------------------------------------------------+-------+
|
||||
|
||||
|
||||
2. Histogram
|
||||
------------
|
||||
|
||||
+--------+--------------+
|
||||
| Fanout | Control Sets |
|
||||
+--------+--------------+
|
||||
|
||||
|
||||
3. Flip-Flop Distribution
|
||||
-------------------------
|
||||
|
||||
+--------------+-----------------------+------------------------+-----------------+--------------+
|
||||
| Clock Enable | Synchronous Set/Reset | Asynchronous Set/Reset | Total Registers | Total Slices |
|
||||
+--------------+-----------------------+------------------------+-----------------+--------------+
|
||||
| No | No | No | 0 | 0 |
|
||||
| No | No | Yes | 0 | 0 |
|
||||
| No | Yes | No | 0 | 0 |
|
||||
| Yes | No | No | 0 | 0 |
|
||||
| Yes | No | Yes | 0 | 0 |
|
||||
| Yes | Yes | No | 0 | 0 |
|
||||
+--------------+-----------------------+------------------------+-----------------+--------------+
|
||||
|
||||
|
||||
4. Detailed Control Set Information
|
||||
-----------------------------------
|
||||
|
||||
+--------------+---------------+------------------+------------------+----------------+
|
||||
| Clock Signal | Enable Signal | Set/Reset Signal | Slice Load Count | Bel Load Count |
|
||||
+--------------+---------------+------------------+------------------+----------------+
|
||||
|
||||
|
||||
BIN
Exp1-2-2/Exp1-2-2.runs/impl_1/mux41_drc_opted.pb
Normal file
BIN
Exp1-2-2/Exp1-2-2.runs/impl_1/mux41_drc_opted.pb
Normal file
Binary file not shown.
49
Exp1-2-2/Exp1-2-2.runs/impl_1/mux41_drc_opted.rpt
Normal file
49
Exp1-2-2/Exp1-2-2.runs/impl_1/mux41_drc_opted.rpt
Normal file
@@ -0,0 +1,49 @@
|
||||
Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
|
||||
------------------------------------------------------------------------------------------------------
|
||||
| Tool Version : Vivado v.2018.1 (win64) Build 2188600 Wed Apr 4 18:40:38 MDT 2018
|
||||
| Date : Thu Sep 26 11:15:57 2024
|
||||
| Host : W10-20240912132 running 64-bit major release (build 9200)
|
||||
| Command : report_drc -file mux41_drc_opted.rpt -pb mux41_drc_opted.pb -rpx mux41_drc_opted.rpx
|
||||
| Design : mux41
|
||||
| Device : xc7a35tcsg324-1
|
||||
| Speed File : -1
|
||||
| Design State : Synthesized
|
||||
------------------------------------------------------------------------------------------------------
|
||||
|
||||
Report DRC
|
||||
|
||||
Table of Contents
|
||||
-----------------
|
||||
1. REPORT SUMMARY
|
||||
2. REPORT DETAILS
|
||||
|
||||
1. REPORT SUMMARY
|
||||
-----------------
|
||||
Netlist: netlist
|
||||
Floorplan: design_1
|
||||
Design limits: <entire design considered>
|
||||
Ruledeck: default
|
||||
Max violations: <unlimited>
|
||||
Violations found: 1
|
||||
+----------+----------+-----------------------------------------------------+------------+
|
||||
| Rule | Severity | Description | Violations |
|
||||
+----------+----------+-----------------------------------------------------+------------+
|
||||
| CFGBVS-1 | Warning | Missing CFGBVS and CONFIG_VOLTAGE Design Properties | 1 |
|
||||
+----------+----------+-----------------------------------------------------+------------+
|
||||
|
||||
2. REPORT DETAILS
|
||||
-----------------
|
||||
CFGBVS-1#1 Warning
|
||||
Missing CFGBVS and CONFIG_VOLTAGE Design Properties
|
||||
Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design. Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0. It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax:
|
||||
|
||||
set_property CFGBVS value1 [current_design]
|
||||
#where value1 is either VCCO or GND
|
||||
|
||||
set_property CONFIG_VOLTAGE value2 [current_design]
|
||||
#where value2 is the voltage provided to configuration bank 0
|
||||
|
||||
Refer to the device configuration user guide for more information.
|
||||
Related violations: <none>
|
||||
|
||||
|
||||
BIN
Exp1-2-2/Exp1-2-2.runs/impl_1/mux41_drc_routed.pb
Normal file
BIN
Exp1-2-2/Exp1-2-2.runs/impl_1/mux41_drc_routed.pb
Normal file
Binary file not shown.
49
Exp1-2-2/Exp1-2-2.runs/impl_1/mux41_drc_routed.rpt
Normal file
49
Exp1-2-2/Exp1-2-2.runs/impl_1/mux41_drc_routed.rpt
Normal file
@@ -0,0 +1,49 @@
|
||||
Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
|
||||
---------------------------------------------------------------------------------------------------------
|
||||
| Tool Version : Vivado v.2018.1 (win64) Build 2188600 Wed Apr 4 18:40:38 MDT 2018
|
||||
| Date : Thu Sep 26 11:16:11 2024
|
||||
| Host : W10-20240912132 running 64-bit major release (build 9200)
|
||||
| Command : report_drc -file mux41_drc_routed.rpt -pb mux41_drc_routed.pb -rpx mux41_drc_routed.rpx
|
||||
| Design : mux41
|
||||
| Device : xc7a35tcsg324-1
|
||||
| Speed File : -1
|
||||
| Design State : Routed
|
||||
---------------------------------------------------------------------------------------------------------
|
||||
|
||||
Report DRC
|
||||
|
||||
Table of Contents
|
||||
-----------------
|
||||
1. REPORT SUMMARY
|
||||
2. REPORT DETAILS
|
||||
|
||||
1. REPORT SUMMARY
|
||||
-----------------
|
||||
Netlist: netlist
|
||||
Floorplan: design_1
|
||||
Design limits: <entire design considered>
|
||||
Ruledeck: default
|
||||
Max violations: <unlimited>
|
||||
Violations found: 1
|
||||
+----------+----------+-----------------------------------------------------+------------+
|
||||
| Rule | Severity | Description | Violations |
|
||||
+----------+----------+-----------------------------------------------------+------------+
|
||||
| CFGBVS-1 | Warning | Missing CFGBVS and CONFIG_VOLTAGE Design Properties | 1 |
|
||||
+----------+----------+-----------------------------------------------------+------------+
|
||||
|
||||
2. REPORT DETAILS
|
||||
-----------------
|
||||
CFGBVS-1#1 Warning
|
||||
Missing CFGBVS and CONFIG_VOLTAGE Design Properties
|
||||
Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design. Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0. It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax:
|
||||
|
||||
set_property CFGBVS value1 [current_design]
|
||||
#where value1 is either VCCO or GND
|
||||
|
||||
set_property CONFIG_VOLTAGE value2 [current_design]
|
||||
#where value2 is the voltage provided to configuration bank 0
|
||||
|
||||
Refer to the device configuration user guide for more information.
|
||||
Related violations: <none>
|
||||
|
||||
|
||||
366
Exp1-2-2/Exp1-2-2.runs/impl_1/mux41_io_placed.rpt
Normal file
366
Exp1-2-2/Exp1-2-2.runs/impl_1/mux41_io_placed.rpt
Normal file
@@ -0,0 +1,366 @@
|
||||
Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
|
||||
-------------------------------------------------------------------------------------------------
|
||||
| Tool Version : Vivado v.2018.1 (win64) Build 2188600 Wed Apr 4 18:40:38 MDT 2018
|
||||
| Date : Thu Sep 26 11:15:58 2024
|
||||
| Host : W10-20240912132 running 64-bit major release (build 9200)
|
||||
| Command : report_io -file mux41_io_placed.rpt
|
||||
| Design : mux41
|
||||
| Device : xc7a35t
|
||||
| Speed File : -1
|
||||
| Package : csg324
|
||||
| Package Version : FINAL 2013-12-19
|
||||
| Package Pin Delay Version : VERS. 2.0 2013-12-19
|
||||
-------------------------------------------------------------------------------------------------
|
||||
|
||||
IO Information
|
||||
|
||||
Table of Contents
|
||||
-----------------
|
||||
1. Summary
|
||||
2. IO Assignments by Package Pin
|
||||
|
||||
1. Summary
|
||||
----------
|
||||
|
||||
+---------------+
|
||||
| Total User IO |
|
||||
+---------------+
|
||||
| 7 |
|
||||
+---------------+
|
||||
|
||||
|
||||
2. IO Assignments by Package Pin
|
||||
--------------------------------
|
||||
|
||||
+------------+-------------+------------+------------------------------+-------------+-------------+---------+------------+------+---------------------+----------------------+---------+------------+-----------+----------+------+------------------+--------------+-------------------+--------------+
|
||||
| Pin Number | Signal Name | Bank Type | Pin Name | Use | IO Standard | IO Bank | Drive (mA) | Slew | On-Chip Termination | Off-Chip Termination | Voltage | Constraint | Pull Type | DQS Bias | Vref | Signal Integrity | Pre Emphasis | Lvds Pre Emphasis | Equalization |
|
||||
+------------+-------------+------------+------------------------------+-------------+-------------+---------+------------+------+---------------------+----------------------+---------+------------+-----------+----------+------+------------------+--------------+-------------------+--------------+
|
||||
| A1 | | High Range | IO_L9N_T1_DQS_AD7N_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| A2 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| A3 | | High Range | IO_L8N_T1_AD14N_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| A4 | | High Range | IO_L8P_T1_AD14P_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| A5 | | High Range | IO_L3N_T0_DQS_AD5N_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| A6 | | High Range | IO_L3P_T0_DQS_AD5P_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| A7 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 3.30 | | | | | | | | |
|
||||
| A8 | | High Range | IO_L12N_T1_MRCC_16 | User IO | | 16 | | | | | | | | | | | | | |
|
||||
| A9 | | High Range | IO_L14N_T2_SRCC_16 | User IO | | 16 | | | | | | | | | | | | | |
|
||||
| A10 | | High Range | IO_L14P_T2_SRCC_16 | User IO | | 16 | | | | | | | | | | | | | |
|
||||
| A11 | | High Range | IO_L4N_T0_15 | User IO | | 15 | | | | | | | | | | | | | |
|
||||
| A12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| A13 | | High Range | IO_L9P_T1_DQS_AD3P_15 | User IO | | 15 | | | | | | | | | | | | | |
|
||||
| A14 | | High Range | IO_L9N_T1_DQS_AD3N_15 | User IO | | 15 | | | | | | | | | | | | | |
|
||||
| A15 | | High Range | IO_L8P_T1_AD10P_15 | User IO | | 15 | | | | | | | | | | | | | |
|
||||
| A16 | | High Range | IO_L8N_T1_AD10N_15 | User IO | | 15 | | | | | | | | | | | | | |
|
||||
| A17 | | High Range | VCCO_15 | VCCO | | 15 | | | | | any** | | | | | | | | |
|
||||
| A18 | | High Range | IO_L10N_T1_AD11N_15 | User IO | | 15 | | | | | | | | | | | | | |
|
||||
| B1 | | High Range | IO_L9P_T1_DQS_AD7P_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| B2 | | High Range | IO_L10N_T1_AD15N_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| B3 | | High Range | IO_L10P_T1_AD15P_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| B4 | | High Range | IO_L7N_T1_AD6N_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| B5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| B6 | | High Range | IO_L2N_T0_AD12N_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| B7 | | High Range | IO_L2P_T0_AD12P_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| B8 | | High Range | IO_L12P_T1_MRCC_16 | User IO | | 16 | | | | | | | | | | | | | |
|
||||
| B9 | | High Range | IO_L11N_T1_SRCC_16 | User IO | | 16 | | | | | | | | | | | | | |
|
||||
| B10 | | High Range | VCCO_16 | VCCO | | 16 | | | | | any** | | | | | | | | |
|
||||
| B11 | | High Range | IO_L4P_T0_15 | User IO | | 15 | | | | | | | | | | | | | |
|
||||
| B12 | | High Range | IO_L3N_T0_DQS_AD1N_15 | User IO | | 15 | | | | | | | | | | | | | |
|
||||
| B13 | | High Range | IO_L2P_T0_AD8P_15 | User IO | | 15 | | | | | | | | | | | | | |
|
||||
| B14 | | High Range | IO_L2N_T0_AD8N_15 | User IO | | 15 | | | | | | | | | | | | | |
|
||||
| B15 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| B16 | | High Range | IO_L7P_T1_AD2P_15 | User IO | | 15 | | | | | | | | | | | | | |
|
||||
| B17 | | High Range | IO_L7N_T1_AD2N_15 | User IO | | 15 | | | | | | | | | | | | | |
|
||||
| B18 | | High Range | IO_L10P_T1_AD11P_15 | User IO | | 15 | | | | | | | | | | | | | |
|
||||
| C1 | | High Range | IO_L16N_T2_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| C2 | | High Range | IO_L16P_T2_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| C3 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 3.30 | | | | | | | | |
|
||||
| C4 | | High Range | IO_L7P_T1_AD6P_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| C5 | | High Range | IO_L1N_T0_AD4N_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| C6 | | High Range | IO_L1P_T0_AD4P_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| C7 | | High Range | IO_L4N_T0_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| C8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| C9 | | High Range | IO_L11P_T1_SRCC_16 | User IO | | 16 | | | | | | | | | | | | | |
|
||||
| C10 | | High Range | IO_L13N_T2_MRCC_16 | User IO | | 16 | | | | | | | | | | | | | |
|
||||
| C11 | | High Range | IO_L13P_T2_MRCC_16 | User IO | | 16 | | | | | | | | | | | | | |
|
||||
| C12 | | High Range | IO_L3P_T0_DQS_AD1P_15 | User IO | | 15 | | | | | | | | | | | | | |
|
||||
| C13 | | High Range | VCCO_15 | VCCO | | 15 | | | | | any** | | | | | | | | |
|
||||
| C14 | | High Range | IO_L1N_T0_AD0N_15 | User IO | | 15 | | | | | | | | | | | | | |
|
||||
| C15 | | High Range | IO_L12N_T1_MRCC_15 | User IO | | 15 | | | | | | | | | | | | | |
|
||||
| C16 | | High Range | IO_L20P_T3_A20_15 | User IO | | 15 | | | | | | | | | | | | | |
|
||||
| C17 | | High Range | IO_L20N_T3_A19_15 | User IO | | 15 | | | | | | | | | | | | | |
|
||||
| C18 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| D1 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| D2 | | High Range | IO_L14N_T2_SRCC_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| D3 | | High Range | IO_L12N_T1_MRCC_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| D4 | | High Range | IO_L11N_T1_SRCC_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| D5 | | High Range | IO_L11P_T1_SRCC_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| D6 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 3.30 | | | | | | | | |
|
||||
| D7 | | High Range | IO_L6N_T0_VREF_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| D8 | | High Range | IO_L4P_T0_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| D9 | | High Range | IO_L6N_T0_VREF_16 | User IO | | 16 | | | | | | | | | | | | | |
|
||||
| D10 | | High Range | IO_L19N_T3_VREF_16 | User IO | | 16 | | | | | | | | | | | | | |
|
||||
| D11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| D12 | | High Range | IO_L6P_T0_15 | User IO | | 15 | | | | | | | | | | | | | |
|
||||
| D13 | | High Range | IO_L6N_T0_VREF_15 | User IO | | 15 | | | | | | | | | | | | | |
|
||||
| D14 | | High Range | IO_L1P_T0_AD0P_15 | User IO | | 15 | | | | | | | | | | | | | |
|
||||
| D15 | | High Range | IO_L12P_T1_MRCC_15 | User IO | | 15 | | | | | | | | | | | | | |
|
||||
| D16 | | High Range | VCCO_15 | VCCO | | 15 | | | | | any** | | | | | | | | |
|
||||
| D17 | | High Range | IO_L16N_T2_A27_15 | User IO | | 15 | | | | | | | | | | | | | |
|
||||
| D18 | | High Range | IO_L21N_T3_DQS_A18_15 | User IO | | 15 | | | | | | | | | | | | | |
|
||||
| E1 | | High Range | IO_L18N_T2_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| E2 | | High Range | IO_L14P_T2_SRCC_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| E3 | | High Range | IO_L12P_T1_MRCC_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| E4 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| E5 | | High Range | IO_L5N_T0_AD13N_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| E6 | | High Range | IO_L5P_T0_AD13P_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| E7 | | High Range | IO_L6P_T0_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| E8 | | Dedicated | VCCBATT_0 | Config | | 0 | | | | | | | | | | | | | |
|
||||
| E9 | | Dedicated | CCLK_0 | Config | | 0 | | | | | | | | | | | | | |
|
||||
| E10 | | Dedicated | TCK_0 | Config | | 0 | | | | | | | | | | | | | |
|
||||
| E11 | | Dedicated | TDI_0 | Config | | 0 | | | | | | | | | | | | | |
|
||||
| E12 | | Dedicated | TMS_0 | Config | | 0 | | | | | | | | | | | | | |
|
||||
| E13 | | Dedicated | TDO_0 | Config | | 0 | | | | | | | | | | | | | |
|
||||
| E14 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| E15 | | High Range | IO_L11P_T1_SRCC_15 | User IO | | 15 | | | | | | | | | | | | | |
|
||||
| E16 | | High Range | IO_L11N_T1_SRCC_15 | User IO | | 15 | | | | | | | | | | | | | |
|
||||
| E17 | | High Range | IO_L16P_T2_A28_15 | User IO | | 15 | | | | | | | | | | | | | |
|
||||
| E18 | | High Range | IO_L21P_T3_DQS_15 | User IO | | 15 | | | | | | | | | | | | | |
|
||||
| F1 | | High Range | IO_L18P_T2_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| F2 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 3.30 | | | | | | | | |
|
||||
| F3 | | High Range | IO_L13N_T2_MRCC_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| F4 | | High Range | IO_L13P_T2_MRCC_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| F5 | | High Range | IO_0_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| F6 | Y | High Range | IO_L19N_T3_VREF_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| F7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| F8 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
|
||||
| F9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| F10 | | | VCCBRAM | VCCBRAM | | | | | | | | | | | | | | | |
|
||||
| F11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| F12 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | |
|
||||
| F13 | | High Range | IO_L5P_T0_AD9P_15 | User IO | | 15 | | | | | | | | | | | | | |
|
||||
| F14 | | High Range | IO_L5N_T0_AD9N_15 | User IO | | 15 | | | | | | | | | | | | | |
|
||||
| F15 | | High Range | IO_L14P_T2_SRCC_15 | User IO | | 15 | | | | | | | | | | | | | |
|
||||
| F16 | | High Range | IO_L14N_T2_SRCC_15 | User IO | | 15 | | | | | | | | | | | | | |
|
||||
| F17 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| F18 | | High Range | IO_L22N_T3_A16_15 | User IO | | 15 | | | | | | | | | | | | | |
|
||||
| G1 | | High Range | IO_L17N_T2_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| G2 | | High Range | IO_L15N_T2_DQS_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| G3 | | High Range | IO_L20N_T3_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| G4 | | High Range | IO_L20P_T3_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| G5 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 3.30 | | | | | | | | |
|
||||
| G6 | | High Range | IO_L19P_T3_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| G7 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
|
||||
| G8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| G9 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
|
||||
| G10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| G11 | | | VCCBRAM | VCCBRAM | | | | | | | | | | | | | | | |
|
||||
| G12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| G13 | | High Range | IO_0_15 | User IO | | 15 | | | | | | | | | | | | | |
|
||||
| G14 | | High Range | IO_L15N_T2_DQS_ADV_B_15 | User IO | | 15 | | | | | | | | | | | | | |
|
||||
| G15 | | High Range | VCCO_15 | VCCO | | 15 | | | | | any** | | | | | | | | |
|
||||
| G16 | | High Range | IO_L13N_T2_MRCC_15 | User IO | | 15 | | | | | | | | | | | | | |
|
||||
| G17 | | High Range | IO_L18N_T2_A23_15 | User IO | | 15 | | | | | | | | | | | | | |
|
||||
| G18 | | High Range | IO_L22P_T3_A17_15 | User IO | | 15 | | | | | | | | | | | | | |
|
||||
| H1 | | High Range | IO_L17P_T2_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| H2 | | High Range | IO_L15P_T2_DQS_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| H3 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| H4 | | High Range | IO_L21N_T3_DQS_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| H5 | | High Range | IO_L24N_T3_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| H6 | | High Range | IO_L24P_T3_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| H7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| H8 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
|
||||
| H9 | | Dedicated | GNDADC_0 | XADC | | 0 | | | | | | | | | | | | | |
|
||||
| H10 | | Dedicated | VCCADC_0 | XADC | | 0 | | | | | | | | | | | | | |
|
||||
| H11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| H12 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | |
|
||||
| H13 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| H14 | | High Range | IO_L15P_T2_DQS_15 | User IO | | 15 | | | | | | | | | | | | | |
|
||||
| H15 | | High Range | IO_L19N_T3_A21_VREF_15 | User IO | | 15 | | | | | | | | | | | | | |
|
||||
| H16 | | High Range | IO_L13P_T2_MRCC_15 | User IO | | 15 | | | | | | | | | | | | | |
|
||||
| H17 | | High Range | IO_L18P_T2_A24_15 | User IO | | 15 | | | | | | | | | | | | | |
|
||||
| H18 | | High Range | VCCO_15 | VCCO | | 15 | | | | | any** | | | | | | | | |
|
||||
| J1 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 3.30 | | | | | | | | |
|
||||
| J2 | | High Range | IO_L22N_T3_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| J3 | | High Range | IO_L22P_T3_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| J4 | | High Range | IO_L21P_T3_DQS_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| J5 | | High Range | IO_25_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| J6 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| J7 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
|
||||
| J8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| J9 | | Dedicated | VREFN_0 | XADC | | 0 | | | | | | | | | | | | | |
|
||||
| J10 | | Dedicated | VP_0 | XADC | | 0 | | | | | | | | | | | | | |
|
||||
| J11 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
|
||||
| J12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| J13 | | High Range | IO_L17N_T2_A25_15 | User IO | | 15 | | | | | | | | | | | | | |
|
||||
| J14 | | High Range | IO_L19P_T3_A22_15 | User IO | | 15 | | | | | | | | | | | | | |
|
||||
| J15 | | High Range | IO_L24N_T3_RS0_15 | User IO | | 15 | | | | | | | | | | | | | |
|
||||
| J16 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| J17 | | High Range | IO_L23P_T3_FOE_B_15 | User IO | | 15 | | | | | | | | | | | | | |
|
||||
| J18 | | High Range | IO_L23N_T3_FWE_B_15 | User IO | | 15 | | | | | | | | | | | | | |
|
||||
| K1 | | High Range | IO_L23N_T3_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| K2 | | High Range | IO_L23P_T3_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| K3 | | High Range | IO_L2P_T0_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| K4 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 3.30 | | | | | | | | |
|
||||
| K5 | | High Range | IO_L5P_T0_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| K6 | | High Range | IO_0_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| K7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| K8 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
|
||||
| K9 | | Dedicated | VN_0 | XADC | | 0 | | | | | | | | | | | | | |
|
||||
| K10 | | Dedicated | VREFP_0 | XADC | | 0 | | | | | | | | | | | | | |
|
||||
| K11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| K12 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | |
|
||||
| K13 | | High Range | IO_L17P_T2_A26_15 | User IO | | 15 | | | | | | | | | | | | | |
|
||||
| K14 | | High Range | VCCO_15 | VCCO | | 15 | | | | | any** | | | | | | | | |
|
||||
| K15 | | High Range | IO_L24P_T3_RS1_15 | User IO | | 15 | | | | | | | | | | | | | |
|
||||
| K16 | | High Range | IO_25_15 | User IO | | 15 | | | | | | | | | | | | | |
|
||||
| K17 | | High Range | IO_L1P_T0_D00_MOSI_14 | User IO | | 14 | | | | | | | | | | | | | |
|
||||
| K18 | | High Range | IO_L1N_T0_D01_DIN_14 | User IO | | 14 | | | | | | | | | | | | | |
|
||||
| L1 | | High Range | IO_L1P_T0_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| L2 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| L3 | | High Range | IO_L2N_T0_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| L4 | | High Range | IO_L5N_T0_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| L5 | | High Range | IO_L6N_T0_VREF_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| L6 | | High Range | IO_L6P_T0_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| L7 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
|
||||
| L8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| L9 | | Dedicated | DXN_0 | Temp Sensor | | 0 | | | | | | | | | | | | | |
|
||||
| L10 | | Dedicated | DXP_0 | Temp Sensor | | 0 | | | | | | | | | | | | | |
|
||||
| L11 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
|
||||
| L12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| L13 | | High Range | IO_L6P_T0_FCS_B_14 | User IO | | 14 | | | | | | | | | | | | | |
|
||||
| L14 | | High Range | IO_L2P_T0_D02_14 | User IO | | 14 | | | | | | | | | | | | | |
|
||||
| L15 | | High Range | IO_L3P_T0_DQS_PUDC_B_14 | User IO | | 14 | | | | | | | | | | | | | |
|
||||
| L16 | | High Range | IO_L3N_T0_DQS_EMCCLK_14 | User IO | | 14 | | | | | | | | | | | | | |
|
||||
| L17 | | High Range | VCCO_14 | VCCO | | 14 | | | | | any** | | | | | | | | |
|
||||
| L18 | | High Range | IO_L4P_T0_D04_14 | User IO | | 14 | | | | | | | | | | | | | |
|
||||
| M1 | | High Range | IO_L1N_T0_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| M2 | | High Range | IO_L4N_T0_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| M3 | | High Range | IO_L4P_T0_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| M4 | S[0] | High Range | IO_L16P_T2_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | |
|
||||
| M5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| M6 | | High Range | IO_L18P_T2_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| M7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| M8 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
|
||||
| M9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| M10 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
|
||||
| M11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| M12 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | |
|
||||
| M13 | | High Range | IO_L6N_T0_D08_VREF_14 | User IO | | 14 | | | | | | | | | | | | | |
|
||||
| M14 | | High Range | IO_L2N_T0_D03_14 | User IO | | 14 | | | | | | | | | | | | | |
|
||||
| M15 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| M16 | | High Range | IO_L10P_T1_D14_14 | User IO | | 14 | | | | | | | | | | | | | |
|
||||
| M17 | | High Range | IO_L10N_T1_D15_14 | User IO | | 14 | | | | | | | | | | | | | |
|
||||
| M18 | | High Range | IO_L4N_T0_D05_14 | User IO | | 14 | | | | | | | | | | | | | |
|
||||
| N1 | | High Range | IO_L3N_T0_DQS_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| N2 | | High Range | IO_L3P_T0_DQS_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| N3 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 3.30 | | | | | | | | |
|
||||
| N4 | | High Range | IO_L16N_T2_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| N5 | | High Range | IO_L13P_T2_MRCC_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| N6 | | High Range | IO_L18N_T2_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| N7 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
|
||||
| N8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| N9 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
|
||||
| N10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| N11 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
|
||||
| N12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| N13 | | High Range | VCCO_14 | VCCO | | 14 | | | | | any** | | | | | | | | |
|
||||
| N14 | | High Range | IO_L8P_T1_D11_14 | User IO | | 14 | | | | | | | | | | | | | |
|
||||
| N15 | | High Range | IO_L11P_T1_SRCC_14 | User IO | | 14 | | | | | | | | | | | | | |
|
||||
| N16 | | High Range | IO_L11N_T1_SRCC_14 | User IO | | 14 | | | | | | | | | | | | | |
|
||||
| N17 | | High Range | IO_L9P_T1_DQS_14 | User IO | | 14 | | | | | | | | | | | | | |
|
||||
| N18 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| P1 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| P2 | I[3] | High Range | IO_L15P_T2_DQS_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | |
|
||||
| P3 | I[2] | High Range | IO_L14N_T2_SRCC_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | |
|
||||
| P4 | I[1] | High Range | IO_L14P_T2_SRCC_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | |
|
||||
| P5 | I[0] | High Range | IO_L13N_T2_MRCC_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | |
|
||||
| P6 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 3.30 | | | | | | | | |
|
||||
| P7 | | Dedicated | INIT_B_0 | Config | | 0 | | | | | | | | | | | | | |
|
||||
| P8 | | Dedicated | CFGBVS_0 | Config | | 0 | | | | | | | | | | | | | |
|
||||
| P9 | | Dedicated | PROGRAM_B_0 | Config | | 0 | | | | | | | | | | | | | |
|
||||
| P10 | | Dedicated | DONE_0 | Config | | 0 | | | | | | | | | | | | | |
|
||||
| P11 | | Dedicated | M2_0 | Config | | 0 | | | | | | | | | | | | | |
|
||||
| P12 | | Dedicated | M0_0 | Config | | 0 | | | | | | | | | | | | | |
|
||||
| P13 | | Dedicated | M1_0 | Config | | 0 | | | | | | | | | | | | | |
|
||||
| P14 | | High Range | IO_L8N_T1_D12_14 | User IO | | 14 | | | | | | | | | | | | | |
|
||||
| P15 | | High Range | IO_L13P_T2_MRCC_14 | User IO | | 14 | | | | | | | | | | | | | |
|
||||
| P16 | | High Range | VCCO_14 | VCCO | | 14 | | | | | any** | | | | | | | | |
|
||||
| P17 | | High Range | IO_L12P_T1_MRCC_14 | User IO | | 14 | | | | | | | | | | | | | |
|
||||
| P18 | | High Range | IO_L9N_T1_DQS_D13_14 | User IO | | 14 | | | | | | | | | | | | | |
|
||||
| R1 | | High Range | IO_L17P_T2_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| R2 | S[1] | High Range | IO_L15N_T2_DQS_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | |
|
||||
| R3 | | High Range | IO_L11P_T1_SRCC_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| R4 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| R5 | | High Range | IO_L19N_T3_VREF_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| R6 | | High Range | IO_L19P_T3_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| R7 | | High Range | IO_L23P_T3_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| R8 | | High Range | IO_L24P_T3_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| R9 | | Dedicated | VCCO_0 | VCCO | | 0 | | | | | any** | | | | | | | | |
|
||||
| R10 | | High Range | IO_25_14 | User IO | | 14 | | | | | | | | | | | | | |
|
||||
| R11 | | High Range | IO_0_14 | User IO | | 14 | | | | | | | | | | | | | |
|
||||
| R12 | | High Range | IO_L5P_T0_D06_14 | User IO | | 14 | | | | | | | | | | | | | |
|
||||
| R13 | | High Range | IO_L5N_T0_D07_14 | User IO | | 14 | | | | | | | | | | | | | |
|
||||
| R14 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| R15 | | High Range | IO_L13N_T2_MRCC_14 | User IO | | 14 | | | | | | | | | | | | | |
|
||||
| R16 | | High Range | IO_L15P_T2_DQS_RDWR_B_14 | User IO | | 14 | | | | | | | | | | | | | |
|
||||
| R17 | | High Range | IO_L12N_T1_MRCC_14 | User IO | | 14 | | | | | | | | | | | | | |
|
||||
| R18 | | High Range | IO_L7P_T1_D09_14 | User IO | | 14 | | | | | | | | | | | | | |
|
||||
| T1 | | High Range | IO_L17N_T2_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| T2 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 3.30 | | | | | | | | |
|
||||
| T3 | | High Range | IO_L11N_T1_SRCC_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| T4 | | High Range | IO_L12N_T1_MRCC_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| T5 | | High Range | IO_L12P_T1_MRCC_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| T6 | | High Range | IO_L23N_T3_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| T7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| T8 | | High Range | IO_L24N_T3_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| T9 | | High Range | IO_L24P_T3_A01_D17_14 | User IO | | 14 | | | | | | | | | | | | | |
|
||||
| T10 | | High Range | IO_L24N_T3_A00_D16_14 | User IO | | 14 | | | | | | | | | | | | | |
|
||||
| T11 | | High Range | IO_L19P_T3_A10_D26_14 | User IO | | 14 | | | | | | | | | | | | | |
|
||||
| T12 | | High Range | VCCO_14 | VCCO | | 14 | | | | | any** | | | | | | | | |
|
||||
| T13 | | High Range | IO_L23P_T3_A03_D19_14 | User IO | | 14 | | | | | | | | | | | | | |
|
||||
| T14 | | High Range | IO_L14P_T2_SRCC_14 | User IO | | 14 | | | | | | | | | | | | | |
|
||||
| T15 | | High Range | IO_L14N_T2_SRCC_14 | User IO | | 14 | | | | | | | | | | | | | |
|
||||
| T16 | | High Range | IO_L15N_T2_DQS_DOUT_CSO_B_14 | User IO | | 14 | | | | | | | | | | | | | |
|
||||
| T17 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| T18 | | High Range | IO_L7N_T1_D10_14 | User IO | | 14 | | | | | | | | | | | | | |
|
||||
| U1 | | High Range | IO_L7P_T1_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| U2 | | High Range | IO_L9P_T1_DQS_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| U3 | | High Range | IO_L8N_T1_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| U4 | | High Range | IO_L8P_T1_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| U5 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 3.30 | | | | | | | | |
|
||||
| U6 | | High Range | IO_L22N_T3_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| U7 | | High Range | IO_L22P_T3_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| U8 | | High Range | IO_25_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| U9 | | High Range | IO_L21P_T3_DQS_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| U10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| U11 | | High Range | IO_L19N_T3_A09_D25_VREF_14 | User IO | | 14 | | | | | | | | | | | | | |
|
||||
| U12 | | High Range | IO_L20P_T3_A08_D24_14 | User IO | | 14 | | | | | | | | | | | | | |
|
||||
| U13 | | High Range | IO_L23N_T3_A02_D18_14 | User IO | | 14 | | | | | | | | | | | | | |
|
||||
| U14 | | High Range | IO_L22P_T3_A05_D21_14 | User IO | | 14 | | | | | | | | | | | | | |
|
||||
| U15 | | High Range | VCCO_14 | VCCO | | 14 | | | | | any** | | | | | | | | |
|
||||
| U16 | | High Range | IO_L18P_T2_A12_D28_14 | User IO | | 14 | | | | | | | | | | | | | |
|
||||
| U17 | | High Range | IO_L17P_T2_A14_D30_14 | User IO | | 14 | | | | | | | | | | | | | |
|
||||
| U18 | | High Range | IO_L17N_T2_A13_D29_14 | User IO | | 14 | | | | | | | | | | | | | |
|
||||
| V1 | | High Range | IO_L7N_T1_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| V2 | | High Range | IO_L9N_T1_DQS_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| V3 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| V4 | | High Range | IO_L10N_T1_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| V5 | | High Range | IO_L10P_T1_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| V6 | | High Range | IO_L20N_T3_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| V7 | | High Range | IO_L20P_T3_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| V8 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 3.30 | | | | | | | | |
|
||||
| V9 | | High Range | IO_L21N_T3_DQS_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| V10 | | High Range | IO_L21P_T3_DQS_14 | User IO | | 14 | | | | | | | | | | | | | |
|
||||
| V11 | | High Range | IO_L21N_T3_DQS_A06_D22_14 | User IO | | 14 | | | | | | | | | | | | | |
|
||||
| V12 | | High Range | IO_L20N_T3_A07_D23_14 | User IO | | 14 | | | | | | | | | | | | | |
|
||||
| V13 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| V14 | | High Range | IO_L22N_T3_A04_D20_14 | User IO | | 14 | | | | | | | | | | | | | |
|
||||
| V15 | | High Range | IO_L16P_T2_CSI_B_14 | User IO | | 14 | | | | | | | | | | | | | |
|
||||
| V16 | | High Range | IO_L16N_T2_A15_D31_14 | User IO | | 14 | | | | | | | | | | | | | |
|
||||
| V17 | | High Range | IO_L18N_T2_A11_D27_14 | User IO | | 14 | | | | | | | | | | | | | |
|
||||
| V18 | | High Range | VCCO_14 | VCCO | | 14 | | | | | any** | | | | | | | | |
|
||||
+------------+-------------+------------+------------------------------+-------------+-------------+---------+------------+------+---------------------+----------------------+---------+------------+-----------+----------+------+------------------+--------------+-------------------+--------------+
|
||||
* Default value
|
||||
** Special VCCO requirements may apply. Please consult the device family datasheet for specific guideline on VCCO requirements.
|
||||
|
||||
|
||||
BIN
Exp1-2-2/Exp1-2-2.runs/impl_1/mux41_methodology_drc_routed.pb
Normal file
BIN
Exp1-2-2/Exp1-2-2.runs/impl_1/mux41_methodology_drc_routed.pb
Normal file
Binary file not shown.
@@ -0,0 +1,34 @@
|
||||
Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
|
||||
-----------------------------------------------------------------------------------------------------------------------------------------------------
|
||||
| Tool Version : Vivado v.2018.1 (win64) Build 2188600 Wed Apr 4 18:40:38 MDT 2018
|
||||
| Date : Thu Sep 26 11:16:12 2024
|
||||
| Host : W10-20240912132 running 64-bit major release (build 9200)
|
||||
| Command : report_methodology -file mux41_methodology_drc_routed.rpt -pb mux41_methodology_drc_routed.pb -rpx mux41_methodology_drc_routed.rpx
|
||||
| Design : mux41
|
||||
| Device : xc7a35tcsg324-1
|
||||
| Speed File : -1
|
||||
| Design State : Routed
|
||||
-----------------------------------------------------------------------------------------------------------------------------------------------------
|
||||
|
||||
Report Methodology
|
||||
|
||||
Table of Contents
|
||||
-----------------
|
||||
1. REPORT SUMMARY
|
||||
2. REPORT DETAILS
|
||||
|
||||
1. REPORT SUMMARY
|
||||
-----------------
|
||||
Netlist: netlist
|
||||
Floorplan: design_1
|
||||
Design limits: <entire design considered>
|
||||
Max violations: <unlimited>
|
||||
Violations found: 0
|
||||
+------+----------+-------------+------------+
|
||||
| Rule | Severity | Description | Violations |
|
||||
+------+----------+-------------+------------+
|
||||
+------+----------+-------------+------------+
|
||||
|
||||
2. REPORT DETAILS
|
||||
-----------------
|
||||
|
||||
BIN
Exp1-2-2/Exp1-2-2.runs/impl_1/mux41_opt.dcp
Normal file
BIN
Exp1-2-2/Exp1-2-2.runs/impl_1/mux41_opt.dcp
Normal file
Binary file not shown.
BIN
Exp1-2-2/Exp1-2-2.runs/impl_1/mux41_placed.dcp
Normal file
BIN
Exp1-2-2/Exp1-2-2.runs/impl_1/mux41_placed.dcp
Normal file
Binary file not shown.
140
Exp1-2-2/Exp1-2-2.runs/impl_1/mux41_power_routed.rpt
Normal file
140
Exp1-2-2/Exp1-2-2.runs/impl_1/mux41_power_routed.rpt
Normal file
@@ -0,0 +1,140 @@
|
||||
Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
|
||||
-------------------------------------------------------------------------------------------------------------------------------------
|
||||
| Tool Version : Vivado v.2018.1 (win64) Build 2188600 Wed Apr 4 18:40:38 MDT 2018
|
||||
| Date : Thu Sep 26 11:16:12 2024
|
||||
| Host : W10-20240912132 running 64-bit major release (build 9200)
|
||||
| Command : report_power -file mux41_power_routed.rpt -pb mux41_power_summary_routed.pb -rpx mux41_power_routed.rpx
|
||||
| Design : mux41
|
||||
| Device : xc7a35tcsg324-1
|
||||
| Design State : routed
|
||||
| Grade : commercial
|
||||
| Process : typical
|
||||
| Characterization : Production
|
||||
-------------------------------------------------------------------------------------------------------------------------------------
|
||||
|
||||
Power Report
|
||||
|
||||
Table of Contents
|
||||
-----------------
|
||||
1. Summary
|
||||
1.1 On-Chip Components
|
||||
1.2 Power Supply Summary
|
||||
1.3 Confidence Level
|
||||
2. Settings
|
||||
2.1 Environment
|
||||
2.2 Clock Constraints
|
||||
3. Detailed Reports
|
||||
3.1 By Hierarchy
|
||||
|
||||
1. Summary
|
||||
----------
|
||||
|
||||
+--------------------------+--------------+
|
||||
| Total On-Chip Power (W) | 1.373 |
|
||||
| Design Power Budget (W) | Unspecified* |
|
||||
| Power Budget Margin (W) | NA |
|
||||
| Dynamic (W) | 1.299 |
|
||||
| Device Static (W) | 0.075 |
|
||||
| Effective TJA (C/W) | 4.8 |
|
||||
| Max Ambient (C) | 78.4 |
|
||||
| Junction Temperature (C) | 31.6 |
|
||||
| Confidence Level | Low |
|
||||
| Setting File | --- |
|
||||
| Simulation Activity File | --- |
|
||||
| Design Nets Matched | NA |
|
||||
+--------------------------+--------------+
|
||||
* Specify Design Power Budget using, set_operating_conditions -design_power_budget <value in Watts>
|
||||
|
||||
|
||||
1.1 On-Chip Components
|
||||
----------------------
|
||||
|
||||
+----------------+-----------+----------+-----------+-----------------+
|
||||
| On-Chip | Power (W) | Used | Available | Utilization (%) |
|
||||
+----------------+-----------+----------+-----------+-----------------+
|
||||
| Slice Logic | 0.004 | 1 | --- | --- |
|
||||
| LUT as Logic | 0.004 | 1 | 20800 | <0.01 |
|
||||
| Signals | 0.030 | 7 | --- | --- |
|
||||
| I/O | 1.265 | 7 | 210 | 3.33 |
|
||||
| Static Power | 0.075 | | | |
|
||||
| Total | 1.373 | | | |
|
||||
+----------------+-----------+----------+-----------+-----------------+
|
||||
|
||||
|
||||
1.2 Power Supply Summary
|
||||
------------------------
|
||||
|
||||
+-----------+-------------+-----------+-------------+------------+
|
||||
| Source | Voltage (V) | Total (A) | Dynamic (A) | Static (A) |
|
||||
+-----------+-------------+-----------+-------------+------------+
|
||||
| Vccint | 1.000 | 0.070 | 0.058 | 0.012 |
|
||||
| Vccaux | 1.800 | 0.058 | 0.045 | 0.013 |
|
||||
| Vcco33 | 3.300 | 0.352 | 0.351 | 0.001 |
|
||||
| Vcco25 | 2.500 | 0.000 | 0.000 | 0.000 |
|
||||
| Vcco18 | 1.800 | 0.000 | 0.000 | 0.000 |
|
||||
| Vcco15 | 1.500 | 0.000 | 0.000 | 0.000 |
|
||||
| Vcco135 | 1.350 | 0.000 | 0.000 | 0.000 |
|
||||
| Vcco12 | 1.200 | 0.000 | 0.000 | 0.000 |
|
||||
| Vccaux_io | 1.800 | 0.000 | 0.000 | 0.000 |
|
||||
| Vccbram | 1.000 | 0.000 | 0.000 | 0.000 |
|
||||
| MGTAVcc | 1.000 | 0.000 | 0.000 | 0.000 |
|
||||
| MGTAVtt | 1.200 | 0.000 | 0.000 | 0.000 |
|
||||
| Vccadc | 1.800 | 0.020 | 0.000 | 0.020 |
|
||||
+-----------+-------------+-----------+-------------+------------+
|
||||
|
||||
|
||||
1.3 Confidence Level
|
||||
--------------------
|
||||
|
||||
+-----------------------------+------------+--------------------------------------------------------+------------------------------------------------------------------------------------------------------------+
|
||||
| User Input Data | Confidence | Details | Action |
|
||||
+-----------------------------+------------+--------------------------------------------------------+------------------------------------------------------------------------------------------------------------+
|
||||
| Design implementation state | High | Design is routed | |
|
||||
| Clock nodes activity | High | User specified more than 95% of clocks | |
|
||||
| I/O nodes activity | Low | More than 75% of inputs are missing user specification | Provide missing input activity with simulation results or by editing the "By Resource Type -> I/Os" view |
|
||||
| Internal nodes activity | Medium | User specified less than 25% of internal nodes | Provide missing internal nodes activity with simulation results or by editing the "By Resource Type" views |
|
||||
| Device models | High | Device models are Production | |
|
||||
| | | | |
|
||||
| Overall confidence level | Low | | |
|
||||
+-----------------------------+------------+--------------------------------------------------------+------------------------------------------------------------------------------------------------------------+
|
||||
|
||||
|
||||
2. Settings
|
||||
-----------
|
||||
|
||||
2.1 Environment
|
||||
---------------
|
||||
|
||||
+-----------------------+--------------------------+
|
||||
| Ambient Temp (C) | 25.0 |
|
||||
| ThetaJA (C/W) | 4.8 |
|
||||
| Airflow (LFM) | 250 |
|
||||
| Heat Sink | medium (Medium Profile) |
|
||||
| ThetaSA (C/W) | 4.6 |
|
||||
| Board Selection | medium (10"x10") |
|
||||
| # of Board Layers | 12to15 (12 to 15 Layers) |
|
||||
| Board Temperature (C) | 25.0 |
|
||||
+-----------------------+--------------------------+
|
||||
|
||||
|
||||
2.2 Clock Constraints
|
||||
---------------------
|
||||
|
||||
+-------+--------+-----------------+
|
||||
| Clock | Domain | Constraint (ns) |
|
||||
+-------+--------+-----------------+
|
||||
|
||||
|
||||
3. Detailed Reports
|
||||
-------------------
|
||||
|
||||
3.1 By Hierarchy
|
||||
----------------
|
||||
|
||||
+-------+-----------+
|
||||
| Name | Power (W) |
|
||||
+-------+-----------+
|
||||
| mux41 | 1.299 |
|
||||
+-------+-----------+
|
||||
|
||||
|
||||
BIN
Exp1-2-2/Exp1-2-2.runs/impl_1/mux41_power_summary_routed.pb
Normal file
BIN
Exp1-2-2/Exp1-2-2.runs/impl_1/mux41_power_summary_routed.pb
Normal file
Binary file not shown.
BIN
Exp1-2-2/Exp1-2-2.runs/impl_1/mux41_route_status.pb
Normal file
BIN
Exp1-2-2/Exp1-2-2.runs/impl_1/mux41_route_status.pb
Normal file
Binary file not shown.
11
Exp1-2-2/Exp1-2-2.runs/impl_1/mux41_route_status.rpt
Normal file
11
Exp1-2-2/Exp1-2-2.runs/impl_1/mux41_route_status.rpt
Normal file
@@ -0,0 +1,11 @@
|
||||
Design Route Status
|
||||
: # nets :
|
||||
------------------------------------------- : ----------- :
|
||||
# of logical nets.......................... : 14 :
|
||||
# of nets not needing routing.......... : 7 :
|
||||
# of internally routed nets........ : 7 :
|
||||
# of routable nets..................... : 7 :
|
||||
# of fully routed nets............. : 7 :
|
||||
# of nets with routing errors.......... : 0 :
|
||||
------------------------------------------- : ----------- :
|
||||
|
||||
BIN
Exp1-2-2/Exp1-2-2.runs/impl_1/mux41_routed.dcp
Normal file
BIN
Exp1-2-2/Exp1-2-2.runs/impl_1/mux41_routed.dcp
Normal file
Binary file not shown.
@@ -0,0 +1,2 @@
|
||||
|
||||
2012.4’)Timing analysis from Implemented netlist.
|
||||
173
Exp1-2-2/Exp1-2-2.runs/impl_1/mux41_timing_summary_routed.rpt
Normal file
173
Exp1-2-2/Exp1-2-2.runs/impl_1/mux41_timing_summary_routed.rpt
Normal file
@@ -0,0 +1,173 @@
|
||||
Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
|
||||
--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
|
||||
| Tool Version : Vivado v.2018.1 (win64) Build 2188600 Wed Apr 4 18:40:38 MDT 2018
|
||||
| Date : Thu Sep 26 11:16:12 2024
|
||||
| Host : W10-20240912132 running 64-bit major release (build 9200)
|
||||
| Command : report_timing_summary -max_paths 10 -file mux41_timing_summary_routed.rpt -pb mux41_timing_summary_routed.pb -rpx mux41_timing_summary_routed.rpx -warn_on_violation
|
||||
| Design : mux41
|
||||
| Device : 7a35t-csg324
|
||||
| Speed File : -1 PRODUCTION 1.21 2018-02-08
|
||||
--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
|
||||
|
||||
Timing Summary Report
|
||||
|
||||
------------------------------------------------------------------------------------------------
|
||||
| Timer Settings
|
||||
| --------------
|
||||
------------------------------------------------------------------------------------------------
|
||||
|
||||
Enable Multi Corner Analysis : Yes
|
||||
Enable Pessimism Removal : Yes
|
||||
Pessimism Removal Resolution : Nearest Common Node
|
||||
Enable Input Delay Default Clock : No
|
||||
Enable Preset / Clear Arcs : No
|
||||
Disable Flight Delays : No
|
||||
Ignore I/O Paths : No
|
||||
Timing Early Launch at Borrowing Latches : false
|
||||
|
||||
Corner Analyze Analyze
|
||||
Name Max Paths Min Paths
|
||||
------ --------- ---------
|
||||
Slow Yes Yes
|
||||
Fast Yes Yes
|
||||
|
||||
|
||||
|
||||
check_timing report
|
||||
|
||||
Table of Contents
|
||||
-----------------
|
||||
1. checking no_clock
|
||||
2. checking constant_clock
|
||||
3. checking pulse_width_clock
|
||||
4. checking unconstrained_internal_endpoints
|
||||
5. checking no_input_delay
|
||||
6. checking no_output_delay
|
||||
7. checking multiple_clock
|
||||
8. checking generated_clocks
|
||||
9. checking loops
|
||||
10. checking partial_input_delay
|
||||
11. checking partial_output_delay
|
||||
12. checking latch_loops
|
||||
|
||||
1. checking no_clock
|
||||
--------------------
|
||||
There are 0 register/latch pins with no clock.
|
||||
|
||||
|
||||
2. checking constant_clock
|
||||
--------------------------
|
||||
There are 0 register/latch pins with constant_clock.
|
||||
|
||||
|
||||
3. checking pulse_width_clock
|
||||
-----------------------------
|
||||
There are 0 register/latch pins which need pulse_width check
|
||||
|
||||
|
||||
4. checking unconstrained_internal_endpoints
|
||||
--------------------------------------------
|
||||
There are 0 pins that are not constrained for maximum delay.
|
||||
|
||||
There are 0 pins that are not constrained for maximum delay due to constant clock.
|
||||
|
||||
|
||||
5. checking no_input_delay
|
||||
--------------------------
|
||||
There are 0 input ports with no input delay specified.
|
||||
|
||||
There are 0 input ports with no input delay but user has a false path constraint.
|
||||
|
||||
|
||||
6. checking no_output_delay
|
||||
---------------------------
|
||||
There are 0 ports with no output delay specified.
|
||||
|
||||
There are 0 ports with no output delay but user has a false path constraint
|
||||
|
||||
There are 0 ports with no output delay but with a timing clock defined on it or propagating through it
|
||||
|
||||
|
||||
7. checking multiple_clock
|
||||
--------------------------
|
||||
There are 0 register/latch pins with multiple clocks.
|
||||
|
||||
|
||||
8. checking generated_clocks
|
||||
----------------------------
|
||||
There are 0 generated clocks that are not connected to a clock source.
|
||||
|
||||
|
||||
9. checking loops
|
||||
-----------------
|
||||
There are 0 combinational loops in the design.
|
||||
|
||||
|
||||
10. checking partial_input_delay
|
||||
--------------------------------
|
||||
There are 0 input ports with partial input delay specified.
|
||||
|
||||
|
||||
11. checking partial_output_delay
|
||||
---------------------------------
|
||||
There are 0 ports with partial output delay specified.
|
||||
|
||||
|
||||
12. checking latch_loops
|
||||
------------------------
|
||||
There are 0 combinational latch loops in the design through latch input
|
||||
|
||||
|
||||
|
||||
------------------------------------------------------------------------------------------------
|
||||
| Design Timing Summary
|
||||
| ---------------------
|
||||
------------------------------------------------------------------------------------------------
|
||||
|
||||
WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints
|
||||
------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- --------------------
|
||||
NA NA NA NA NA NA NA NA NA NA NA NA
|
||||
|
||||
|
||||
There are no user specified timing constraints.
|
||||
|
||||
|
||||
------------------------------------------------------------------------------------------------
|
||||
| Clock Summary
|
||||
| -------------
|
||||
------------------------------------------------------------------------------------------------
|
||||
|
||||
|
||||
------------------------------------------------------------------------------------------------
|
||||
| Intra Clock Table
|
||||
| -----------------
|
||||
------------------------------------------------------------------------------------------------
|
||||
|
||||
Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints
|
||||
----- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- --------------------
|
||||
|
||||
|
||||
------------------------------------------------------------------------------------------------
|
||||
| Inter Clock Table
|
||||
| -----------------
|
||||
------------------------------------------------------------------------------------------------
|
||||
|
||||
From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints
|
||||
---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- -------------------
|
||||
|
||||
|
||||
------------------------------------------------------------------------------------------------
|
||||
| Other Path Groups Table
|
||||
| -----------------------
|
||||
------------------------------------------------------------------------------------------------
|
||||
|
||||
Path Group From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints
|
||||
---------- ---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- -------------------
|
||||
|
||||
|
||||
------------------------------------------------------------------------------------------------
|
||||
| Timing Details
|
||||
| --------------
|
||||
------------------------------------------------------------------------------------------------
|
||||
|
||||
|
||||
BIN
Exp1-2-2/Exp1-2-2.runs/impl_1/mux41_utilization_placed.pb
Normal file
BIN
Exp1-2-2/Exp1-2-2.runs/impl_1/mux41_utilization_placed.pb
Normal file
Binary file not shown.
194
Exp1-2-2/Exp1-2-2.runs/impl_1/mux41_utilization_placed.rpt
Normal file
194
Exp1-2-2/Exp1-2-2.runs/impl_1/mux41_utilization_placed.rpt
Normal file
@@ -0,0 +1,194 @@
|
||||
Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
|
||||
-------------------------------------------------------------------------------------------------------
|
||||
| Tool Version : Vivado v.2018.1 (win64) Build 2188600 Wed Apr 4 18:40:38 MDT 2018
|
||||
| Date : Thu Sep 26 11:15:58 2024
|
||||
| Host : W10-20240912132 running 64-bit major release (build 9200)
|
||||
| Command : report_utilization -file mux41_utilization_placed.rpt -pb mux41_utilization_placed.pb
|
||||
| Design : mux41
|
||||
| Device : 7a35tcsg324-1
|
||||
| Design State : Fully Placed
|
||||
-------------------------------------------------------------------------------------------------------
|
||||
|
||||
Utilization Design Information
|
||||
|
||||
Table of Contents
|
||||
-----------------
|
||||
1. Slice Logic
|
||||
1.1 Summary of Registers by Type
|
||||
2. Slice Logic Distribution
|
||||
3. Memory
|
||||
4. DSP
|
||||
5. IO and GT Specific
|
||||
6. Clocking
|
||||
7. Specific Feature
|
||||
8. Primitives
|
||||
9. Black Boxes
|
||||
10. Instantiated Netlists
|
||||
|
||||
1. Slice Logic
|
||||
--------------
|
||||
|
||||
+-------------------------+------+-------+-----------+-------+
|
||||
| Site Type | Used | Fixed | Available | Util% |
|
||||
+-------------------------+------+-------+-----------+-------+
|
||||
| Slice LUTs | 1 | 0 | 20800 | <0.01 |
|
||||
| LUT as Logic | 1 | 0 | 20800 | <0.01 |
|
||||
| LUT as Memory | 0 | 0 | 9600 | 0.00 |
|
||||
| Slice Registers | 0 | 0 | 41600 | 0.00 |
|
||||
| Register as Flip Flop | 0 | 0 | 41600 | 0.00 |
|
||||
| Register as Latch | 0 | 0 | 41600 | 0.00 |
|
||||
| F7 Muxes | 0 | 0 | 16300 | 0.00 |
|
||||
| F8 Muxes | 0 | 0 | 8150 | 0.00 |
|
||||
+-------------------------+------+-------+-----------+-------+
|
||||
|
||||
|
||||
1.1 Summary of Registers by Type
|
||||
--------------------------------
|
||||
|
||||
+-------+--------------+-------------+--------------+
|
||||
| Total | Clock Enable | Synchronous | Asynchronous |
|
||||
+-------+--------------+-------------+--------------+
|
||||
| 0 | _ | - | - |
|
||||
| 0 | _ | - | Set |
|
||||
| 0 | _ | - | Reset |
|
||||
| 0 | _ | Set | - |
|
||||
| 0 | _ | Reset | - |
|
||||
| 0 | Yes | - | - |
|
||||
| 0 | Yes | - | Set |
|
||||
| 0 | Yes | - | Reset |
|
||||
| 0 | Yes | Set | - |
|
||||
| 0 | Yes | Reset | - |
|
||||
+-------+--------------+-------------+--------------+
|
||||
|
||||
|
||||
2. Slice Logic Distribution
|
||||
---------------------------
|
||||
|
||||
+--------------------------+------+-------+-----------+-------+
|
||||
| Site Type | Used | Fixed | Available | Util% |
|
||||
+--------------------------+------+-------+-----------+-------+
|
||||
| Slice | 1 | 0 | 8150 | 0.01 |
|
||||
| SLICEL | 1 | 0 | | |
|
||||
| SLICEM | 0 | 0 | | |
|
||||
| LUT as Logic | 1 | 0 | 20800 | <0.01 |
|
||||
| using O5 output only | 0 | | | |
|
||||
| using O6 output only | 1 | | | |
|
||||
| using O5 and O6 | 0 | | | |
|
||||
| LUT as Memory | 0 | 0 | 9600 | 0.00 |
|
||||
| LUT as Distributed RAM | 0 | 0 | | |
|
||||
| LUT as Shift Register | 0 | 0 | | |
|
||||
| LUT Flip Flop Pairs | 0 | 0 | 20800 | 0.00 |
|
||||
| Unique Control Sets | 0 | | | |
|
||||
+--------------------------+------+-------+-----------+-------+
|
||||
* Note: Review the Control Sets Report for more information regarding control sets.
|
||||
|
||||
|
||||
3. Memory
|
||||
---------
|
||||
|
||||
+----------------+------+-------+-----------+-------+
|
||||
| Site Type | Used | Fixed | Available | Util% |
|
||||
+----------------+------+-------+-----------+-------+
|
||||
| Block RAM Tile | 0 | 0 | 50 | 0.00 |
|
||||
| RAMB36/FIFO* | 0 | 0 | 50 | 0.00 |
|
||||
| RAMB18 | 0 | 0 | 100 | 0.00 |
|
||||
+----------------+------+-------+-----------+-------+
|
||||
* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1
|
||||
|
||||
|
||||
4. DSP
|
||||
------
|
||||
|
||||
+-----------+------+-------+-----------+-------+
|
||||
| Site Type | Used | Fixed | Available | Util% |
|
||||
+-----------+------+-------+-----------+-------+
|
||||
| DSPs | 0 | 0 | 90 | 0.00 |
|
||||
+-----------+------+-------+-----------+-------+
|
||||
|
||||
|
||||
5. IO and GT Specific
|
||||
---------------------
|
||||
|
||||
+-----------------------------+------+-------+-----------+-------+
|
||||
| Site Type | Used | Fixed | Available | Util% |
|
||||
+-----------------------------+------+-------+-----------+-------+
|
||||
| Bonded IOB | 7 | 7 | 210 | 3.33 |
|
||||
| IOB Master Pads | 3 | | | |
|
||||
| IOB Slave Pads | 4 | | | |
|
||||
| Bonded IPADs | 0 | 0 | 2 | 0.00 |
|
||||
| PHY_CONTROL | 0 | 0 | 5 | 0.00 |
|
||||
| PHASER_REF | 0 | 0 | 5 | 0.00 |
|
||||
| OUT_FIFO | 0 | 0 | 20 | 0.00 |
|
||||
| IN_FIFO | 0 | 0 | 20 | 0.00 |
|
||||
| IDELAYCTRL | 0 | 0 | 5 | 0.00 |
|
||||
| IBUFDS | 0 | 0 | 202 | 0.00 |
|
||||
| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 20 | 0.00 |
|
||||
| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 20 | 0.00 |
|
||||
| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 250 | 0.00 |
|
||||
| ILOGIC | 0 | 0 | 210 | 0.00 |
|
||||
| OLOGIC | 0 | 0 | 210 | 0.00 |
|
||||
+-----------------------------+------+-------+-----------+-------+
|
||||
|
||||
|
||||
6. Clocking
|
||||
-----------
|
||||
|
||||
+------------+------+-------+-----------+-------+
|
||||
| Site Type | Used | Fixed | Available | Util% |
|
||||
+------------+------+-------+-----------+-------+
|
||||
| BUFGCTRL | 0 | 0 | 32 | 0.00 |
|
||||
| BUFIO | 0 | 0 | 20 | 0.00 |
|
||||
| MMCME2_ADV | 0 | 0 | 5 | 0.00 |
|
||||
| PLLE2_ADV | 0 | 0 | 5 | 0.00 |
|
||||
| BUFMRCE | 0 | 0 | 10 | 0.00 |
|
||||
| BUFHCE | 0 | 0 | 72 | 0.00 |
|
||||
| BUFR | 0 | 0 | 20 | 0.00 |
|
||||
+------------+------+-------+-----------+-------+
|
||||
|
||||
|
||||
7. Specific Feature
|
||||
-------------------
|
||||
|
||||
+-------------+------+-------+-----------+-------+
|
||||
| Site Type | Used | Fixed | Available | Util% |
|
||||
+-------------+------+-------+-----------+-------+
|
||||
| BSCANE2 | 0 | 0 | 4 | 0.00 |
|
||||
| CAPTUREE2 | 0 | 0 | 1 | 0.00 |
|
||||
| DNA_PORT | 0 | 0 | 1 | 0.00 |
|
||||
| EFUSE_USR | 0 | 0 | 1 | 0.00 |
|
||||
| FRAME_ECCE2 | 0 | 0 | 1 | 0.00 |
|
||||
| ICAPE2 | 0 | 0 | 2 | 0.00 |
|
||||
| PCIE_2_1 | 0 | 0 | 1 | 0.00 |
|
||||
| STARTUPE2 | 0 | 0 | 1 | 0.00 |
|
||||
| XADC | 0 | 0 | 1 | 0.00 |
|
||||
+-------------+------+-------+-----------+-------+
|
||||
|
||||
|
||||
8. Primitives
|
||||
-------------
|
||||
|
||||
+----------+------+---------------------+
|
||||
| Ref Name | Used | Functional Category |
|
||||
+----------+------+---------------------+
|
||||
| IBUF | 6 | IO |
|
||||
| OBUF | 1 | IO |
|
||||
| LUT6 | 1 | LUT |
|
||||
+----------+------+---------------------+
|
||||
|
||||
|
||||
9. Black Boxes
|
||||
--------------
|
||||
|
||||
+----------+------+
|
||||
| Ref Name | Used |
|
||||
+----------+------+
|
||||
|
||||
|
||||
10. Instantiated Netlists
|
||||
-------------------------
|
||||
|
||||
+----------+------+
|
||||
| Ref Name | Used |
|
||||
+----------+------+
|
||||
|
||||
|
||||
BIN
Exp1-2-2/Exp1-2-2.runs/impl_1/opt_design.pb
Normal file
BIN
Exp1-2-2/Exp1-2-2.runs/impl_1/opt_design.pb
Normal file
Binary file not shown.
BIN
Exp1-2-2/Exp1-2-2.runs/impl_1/place_design.pb
Normal file
BIN
Exp1-2-2/Exp1-2-2.runs/impl_1/place_design.pb
Normal file
Binary file not shown.
BIN
Exp1-2-2/Exp1-2-2.runs/impl_1/route_design.pb
Normal file
BIN
Exp1-2-2/Exp1-2-2.runs/impl_1/route_design.pb
Normal file
Binary file not shown.
15
Exp1-2-2/Exp1-2-2.runs/impl_1/route_report_bus_skew_0.rpt
Normal file
15
Exp1-2-2/Exp1-2-2.runs/impl_1/route_report_bus_skew_0.rpt
Normal file
@@ -0,0 +1,15 @@
|
||||
Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
|
||||
-----------------------------------------------------------------------------------------------------------------------
|
||||
| Tool Version : Vivado v.2018.1 (win64) Build 2188600 Wed Apr 4 18:40:38 MDT 2018
|
||||
| Date : Thu Sep 26 11:16:12 2024
|
||||
| Host : W10-20240912132 running 64-bit major release (build 9200)
|
||||
| Command : report_bus_skew -warn_on_violation -file route_report_bus_skew_0.rpt -rpx route_report_bus_skew_0.rpx
|
||||
| Design : mux41
|
||||
| Device : 7a35t-csg324
|
||||
| Speed File : -1 PRODUCTION 1.21 2018-02-08
|
||||
-----------------------------------------------------------------------------------------------------------------------
|
||||
|
||||
Bus Skew Report
|
||||
|
||||
No bus skew constraints
|
||||
|
||||
459
Exp1-2-2/Exp1-2-2.runs/impl_1/usage_statistics_webtalk.xml
Normal file
459
Exp1-2-2/Exp1-2-2.runs/impl_1/usage_statistics_webtalk.xml
Normal file
@@ -0,0 +1,459 @@
|
||||
<?xml version="1.0" encoding="UTF-8" ?>
|
||||
<webTalkData fileName='usage_statistics_webtalk.xml' majorVersion='1' minorVersion='0' timeStamp='Thu Sep 26 11:16:57 2024'>
|
||||
<section name="__ROOT__" level="0" order="1" description="">
|
||||
<section name="software_version_and_target_device" level="1" order="1" description="">
|
||||
<keyValuePair key="beta" value="FALSE" description="" />
|
||||
<keyValuePair key="build_version" value="2188600" description="" />
|
||||
<keyValuePair key="date_generated" value="Thu Sep 26 11:16:57 2024" description="" />
|
||||
<keyValuePair key="os_platform" value="WIN64" description="" />
|
||||
<keyValuePair key="product_version" value="Vivado v2018.1 (64-bit)" description="" />
|
||||
<keyValuePair key="project_id" value="fbe5a834d1f2498f94e9d82c49c1070a" description="" />
|
||||
<keyValuePair key="project_iteration" value="1" description="" />
|
||||
<keyValuePair key="random_id" value="78ec1a93-fd1a-4b14-8c4b-87f04256706b" description="" />
|
||||
<keyValuePair key="registration_id" value="78ec1a93-fd1a-4b14-8c4b-87f04256706b" description="" />
|
||||
<keyValuePair key="route_design" value="TRUE" description="" />
|
||||
<keyValuePair key="target_device" value="xc7a35t" description="" />
|
||||
<keyValuePair key="target_family" value="artix7" description="" />
|
||||
<keyValuePair key="target_package" value="csg324" description="" />
|
||||
<keyValuePair key="target_speed" value="-1" description="" />
|
||||
<keyValuePair key="tool_flow" value="Vivado" description="" />
|
||||
</section>
|
||||
<section name="user_environment" level="1" order="2" description="">
|
||||
<keyValuePair key="cpu_name" value="13th Gen Intel(R) Core(TM) i7-13700H" description="" />
|
||||
<keyValuePair key="cpu_speed" value="2918 MHz" description="" />
|
||||
<keyValuePair key="os_name" value="Microsoft Windows 8 or later , 64-bit" description="" />
|
||||
<keyValuePair key="os_release" value="major release (build 9200)" description="" />
|
||||
<keyValuePair key="system_ram" value="16.000 GB" description="" />
|
||||
<keyValuePair key="total_processors" value="1" description="" />
|
||||
</section>
|
||||
<section name="report_drc" level="1" order="3" description="">
|
||||
<section name="command_line_options" level="2" order="1" description="">
|
||||
<keyValuePair key="-append" value="default::[not_specified]" description="" />
|
||||
<keyValuePair key="-checks" value="default::[not_specified]" description="" />
|
||||
<keyValuePair key="-fail_on" value="default::[not_specified]" description="" />
|
||||
<keyValuePair key="-force" value="default::[not_specified]" description="" />
|
||||
<keyValuePair key="-format" value="default::[not_specified]" description="" />
|
||||
<keyValuePair key="-internal" value="default::[not_specified]" description="" />
|
||||
<keyValuePair key="-internal_only" value="default::[not_specified]" description="" />
|
||||
<keyValuePair key="-messages" value="default::[not_specified]" description="" />
|
||||
<keyValuePair key="-name" value="default::[not_specified]" description="" />
|
||||
<keyValuePair key="-no_waivers" value="default::[not_specified]" description="" />
|
||||
<keyValuePair key="-return_string" value="default::[not_specified]" description="" />
|
||||
<keyValuePair key="-ruledecks" value="default::[not_specified]" description="" />
|
||||
<keyValuePair key="-upgrade_cw" value="default::[not_specified]" description="" />
|
||||
<keyValuePair key="-waived" value="default::[not_specified]" description="" />
|
||||
</section>
|
||||
<section name="results" level="2" order="2" description="">
|
||||
<keyValuePair key="cfgbvs-1" value="1" description="" />
|
||||
</section>
|
||||
</section>
|
||||
<section name="report_utilization" level="1" order="4" description="">
|
||||
<section name="clocking" level="2" order="1" description="">
|
||||
<keyValuePair key="bufgctrl_available" value="32" description="" />
|
||||
<keyValuePair key="bufgctrl_fixed" value="0" description="" />
|
||||
<keyValuePair key="bufgctrl_used" value="0" description="" />
|
||||
<keyValuePair key="bufgctrl_util_percentage" value="0.00" description="" />
|
||||
<keyValuePair key="bufhce_available" value="72" description="" />
|
||||
<keyValuePair key="bufhce_fixed" value="0" description="" />
|
||||
<keyValuePair key="bufhce_used" value="0" description="" />
|
||||
<keyValuePair key="bufhce_util_percentage" value="0.00" description="" />
|
||||
<keyValuePair key="bufio_available" value="20" description="" />
|
||||
<keyValuePair key="bufio_fixed" value="0" description="" />
|
||||
<keyValuePair key="bufio_used" value="0" description="" />
|
||||
<keyValuePair key="bufio_util_percentage" value="0.00" description="" />
|
||||
<keyValuePair key="bufmrce_available" value="10" description="" />
|
||||
<keyValuePair key="bufmrce_fixed" value="0" description="" />
|
||||
<keyValuePair key="bufmrce_used" value="0" description="" />
|
||||
<keyValuePair key="bufmrce_util_percentage" value="0.00" description="" />
|
||||
<keyValuePair key="bufr_available" value="20" description="" />
|
||||
<keyValuePair key="bufr_fixed" value="0" description="" />
|
||||
<keyValuePair key="bufr_used" value="0" description="" />
|
||||
<keyValuePair key="bufr_util_percentage" value="0.00" description="" />
|
||||
<keyValuePair key="mmcme2_adv_available" value="5" description="" />
|
||||
<keyValuePair key="mmcme2_adv_fixed" value="0" description="" />
|
||||
<keyValuePair key="mmcme2_adv_used" value="0" description="" />
|
||||
<keyValuePair key="mmcme2_adv_util_percentage" value="0.00" description="" />
|
||||
<keyValuePair key="plle2_adv_available" value="5" description="" />
|
||||
<keyValuePair key="plle2_adv_fixed" value="0" description="" />
|
||||
<keyValuePair key="plle2_adv_used" value="0" description="" />
|
||||
<keyValuePair key="plle2_adv_util_percentage" value="0.00" description="" />
|
||||
</section>
|
||||
<section name="dsp" level="2" order="2" description="">
|
||||
<keyValuePair key="dsps_available" value="90" description="" />
|
||||
<keyValuePair key="dsps_fixed" value="0" description="" />
|
||||
<keyValuePair key="dsps_used" value="0" description="" />
|
||||
<keyValuePair key="dsps_util_percentage" value="0.00" description="" />
|
||||
</section>
|
||||
<section name="io_standard" level="2" order="3" description="">
|
||||
<keyValuePair key="blvds_25" value="0" description="" />
|
||||
<keyValuePair key="diff_hstl_i" value="0" description="" />
|
||||
<keyValuePair key="diff_hstl_i_18" value="0" description="" />
|
||||
<keyValuePair key="diff_hstl_ii" value="0" description="" />
|
||||
<keyValuePair key="diff_hstl_ii_18" value="0" description="" />
|
||||
<keyValuePair key="diff_hsul_12" value="0" description="" />
|
||||
<keyValuePair key="diff_mobile_ddr" value="0" description="" />
|
||||
<keyValuePair key="diff_sstl135" value="0" description="" />
|
||||
<keyValuePair key="diff_sstl135_r" value="0" description="" />
|
||||
<keyValuePair key="diff_sstl15" value="0" description="" />
|
||||
<keyValuePair key="diff_sstl15_r" value="0" description="" />
|
||||
<keyValuePair key="diff_sstl18_i" value="0" description="" />
|
||||
<keyValuePair key="diff_sstl18_ii" value="0" description="" />
|
||||
<keyValuePair key="hstl_i" value="0" description="" />
|
||||
<keyValuePair key="hstl_i_18" value="0" description="" />
|
||||
<keyValuePair key="hstl_ii" value="0" description="" />
|
||||
<keyValuePair key="hstl_ii_18" value="0" description="" />
|
||||
<keyValuePair key="hsul_12" value="0" description="" />
|
||||
<keyValuePair key="lvcmos12" value="0" description="" />
|
||||
<keyValuePair key="lvcmos15" value="0" description="" />
|
||||
<keyValuePair key="lvcmos18" value="0" description="" />
|
||||
<keyValuePair key="lvcmos25" value="0" description="" />
|
||||
<keyValuePair key="lvcmos33" value="1" description="" />
|
||||
<keyValuePair key="lvds_25" value="0" description="" />
|
||||
<keyValuePair key="lvttl" value="0" description="" />
|
||||
<keyValuePair key="mini_lvds_25" value="0" description="" />
|
||||
<keyValuePair key="mobile_ddr" value="0" description="" />
|
||||
<keyValuePair key="pci33_3" value="0" description="" />
|
||||
<keyValuePair key="ppds_25" value="0" description="" />
|
||||
<keyValuePair key="rsds_25" value="0" description="" />
|
||||
<keyValuePair key="sstl135" value="0" description="" />
|
||||
<keyValuePair key="sstl135_r" value="0" description="" />
|
||||
<keyValuePair key="sstl15" value="0" description="" />
|
||||
<keyValuePair key="sstl15_r" value="0" description="" />
|
||||
<keyValuePair key="sstl18_i" value="0" description="" />
|
||||
<keyValuePair key="sstl18_ii" value="0" description="" />
|
||||
<keyValuePair key="tmds_33" value="0" description="" />
|
||||
</section>
|
||||
<section name="memory" level="2" order="4" description="">
|
||||
<keyValuePair key="block_ram_tile_available" value="50" description="" />
|
||||
<keyValuePair key="block_ram_tile_fixed" value="0" description="" />
|
||||
<keyValuePair key="block_ram_tile_used" value="0" description="" />
|
||||
<keyValuePair key="block_ram_tile_util_percentage" value="0.00" description="" />
|
||||
<keyValuePair key="ramb18_available" value="100" description="" />
|
||||
<keyValuePair key="ramb18_fixed" value="0" description="" />
|
||||
<keyValuePair key="ramb18_used" value="0" description="" />
|
||||
<keyValuePair key="ramb18_util_percentage" value="0.00" description="" />
|
||||
<keyValuePair key="ramb36_fifo_available" value="50" description="" />
|
||||
<keyValuePair key="ramb36_fifo_fixed" value="0" description="" />
|
||||
<keyValuePair key="ramb36_fifo_used" value="0" description="" />
|
||||
<keyValuePair key="ramb36_fifo_util_percentage" value="0.00" description="" />
|
||||
</section>
|
||||
<section name="primitives" level="2" order="5" description="">
|
||||
<keyValuePair key="ibuf_functional_category" value="IO" description="" />
|
||||
<keyValuePair key="ibuf_used" value="6" description="" />
|
||||
<keyValuePair key="lut6_functional_category" value="LUT" description="" />
|
||||
<keyValuePair key="lut6_used" value="1" description="" />
|
||||
<keyValuePair key="obuf_functional_category" value="IO" description="" />
|
||||
<keyValuePair key="obuf_used" value="1" description="" />
|
||||
</section>
|
||||
<section name="slice_logic" level="2" order="6" description="">
|
||||
<keyValuePair key="f7_muxes_available" value="16300" description="" />
|
||||
<keyValuePair key="f7_muxes_fixed" value="0" description="" />
|
||||
<keyValuePair key="f7_muxes_used" value="0" description="" />
|
||||
<keyValuePair key="f7_muxes_util_percentage" value="0.00" description="" />
|
||||
<keyValuePair key="f8_muxes_available" value="8150" description="" />
|
||||
<keyValuePair key="f8_muxes_fixed" value="0" description="" />
|
||||
<keyValuePair key="f8_muxes_used" value="0" description="" />
|
||||
<keyValuePair key="f8_muxes_util_percentage" value="0.00" description="" />
|
||||
<keyValuePair key="lut_as_distributed_ram_fixed" value="0" description="" />
|
||||
<keyValuePair key="lut_as_distributed_ram_used" value="0" description="" />
|
||||
<keyValuePair key="lut_as_logic_available" value="20800" description="" />
|
||||
<keyValuePair key="lut_as_logic_available" value="20800" description="" />
|
||||
<keyValuePair key="lut_as_logic_fixed" value="0" description="" />
|
||||
<keyValuePair key="lut_as_logic_fixed" value="0" description="" />
|
||||
<keyValuePair key="lut_as_logic_used" value="1" description="" />
|
||||
<keyValuePair key="lut_as_logic_used" value="1" description="" />
|
||||
<keyValuePair key="lut_as_logic_util_percentage" value="<0.01" description="" />
|
||||
<keyValuePair key="lut_as_logic_util_percentage" value="<0.01" description="" />
|
||||
<keyValuePair key="lut_as_memory_available" value="9600" description="" />
|
||||
<keyValuePair key="lut_as_memory_available" value="9600" description="" />
|
||||
<keyValuePair key="lut_as_memory_fixed" value="0" description="" />
|
||||
<keyValuePair key="lut_as_memory_fixed" value="0" description="" />
|
||||
<keyValuePair key="lut_as_memory_used" value="0" description="" />
|
||||
<keyValuePair key="lut_as_memory_used" value="0" description="" />
|
||||
<keyValuePair key="lut_as_memory_util_percentage" value="0.00" description="" />
|
||||
<keyValuePair key="lut_as_memory_util_percentage" value="0.00" description="" />
|
||||
<keyValuePair key="lut_as_shift_register_fixed" value="0" description="" />
|
||||
<keyValuePair key="lut_as_shift_register_used" value="0" description="" />
|
||||
<keyValuePair key="lut_flip_flop_pairs_available" value="20800" description="" />
|
||||
<keyValuePair key="lut_flip_flop_pairs_fixed" value="0" description="" />
|
||||
<keyValuePair key="lut_flip_flop_pairs_used" value="0" description="" />
|
||||
<keyValuePair key="lut_flip_flop_pairs_util_percentage" value="0.00" description="" />
|
||||
<keyValuePair key="register_as_flip_flop_available" value="41600" description="" />
|
||||
<keyValuePair key="register_as_flip_flop_fixed" value="0" description="" />
|
||||
<keyValuePair key="register_as_flip_flop_used" value="0" description="" />
|
||||
<keyValuePair key="register_as_flip_flop_util_percentage" value="0.00" description="" />
|
||||
<keyValuePair key="register_as_latch_available" value="41600" description="" />
|
||||
<keyValuePair key="register_as_latch_fixed" value="0" description="" />
|
||||
<keyValuePair key="register_as_latch_used" value="0" description="" />
|
||||
<keyValuePair key="register_as_latch_util_percentage" value="0.00" description="" />
|
||||
<keyValuePair key="slice_available" value="8150" description="" />
|
||||
<keyValuePair key="slice_fixed" value="0" description="" />
|
||||
<keyValuePair key="slice_luts_available" value="20800" description="" />
|
||||
<keyValuePair key="slice_luts_fixed" value="0" description="" />
|
||||
<keyValuePair key="slice_luts_used" value="1" description="" />
|
||||
<keyValuePair key="slice_luts_util_percentage" value="<0.01" description="" />
|
||||
<keyValuePair key="slice_registers_available" value="41600" description="" />
|
||||
<keyValuePair key="slice_registers_fixed" value="0" description="" />
|
||||
<keyValuePair key="slice_registers_used" value="0" description="" />
|
||||
<keyValuePair key="slice_registers_util_percentage" value="0.00" description="" />
|
||||
<keyValuePair key="slice_used" value="1" description="" />
|
||||
<keyValuePair key="slice_util_percentage" value="0.01" description="" />
|
||||
<keyValuePair key="slicel_fixed" value="0" description="" />
|
||||
<keyValuePair key="slicel_used" value="1" description="" />
|
||||
<keyValuePair key="slicem_fixed" value="0" description="" />
|
||||
<keyValuePair key="slicem_used" value="0" description="" />
|
||||
<keyValuePair key="unique_control_sets_used" value="0" description="" />
|
||||
<keyValuePair key="using_o5_and_o6_fixed" value="0" description="" />
|
||||
<keyValuePair key="using_o5_and_o6_used" value="0" description="" />
|
||||
<keyValuePair key="using_o5_output_only_fixed" value="0" description="" />
|
||||
<keyValuePair key="using_o5_output_only_used" value="0" description="" />
|
||||
<keyValuePair key="using_o6_output_only_fixed" value="0" description="" />
|
||||
<keyValuePair key="using_o6_output_only_used" value="1" description="" />
|
||||
</section>
|
||||
<section name="specific_feature" level="2" order="7" description="">
|
||||
<keyValuePair key="bscane2_available" value="4" description="" />
|
||||
<keyValuePair key="bscane2_fixed" value="0" description="" />
|
||||
<keyValuePair key="bscane2_used" value="0" description="" />
|
||||
<keyValuePair key="bscane2_util_percentage" value="0.00" description="" />
|
||||
<keyValuePair key="capturee2_available" value="1" description="" />
|
||||
<keyValuePair key="capturee2_fixed" value="0" description="" />
|
||||
<keyValuePair key="capturee2_used" value="0" description="" />
|
||||
<keyValuePair key="capturee2_util_percentage" value="0.00" description="" />
|
||||
<keyValuePair key="dna_port_available" value="1" description="" />
|
||||
<keyValuePair key="dna_port_fixed" value="0" description="" />
|
||||
<keyValuePair key="dna_port_used" value="0" description="" />
|
||||
<keyValuePair key="dna_port_util_percentage" value="0.00" description="" />
|
||||
<keyValuePair key="efuse_usr_available" value="1" description="" />
|
||||
<keyValuePair key="efuse_usr_fixed" value="0" description="" />
|
||||
<keyValuePair key="efuse_usr_used" value="0" description="" />
|
||||
<keyValuePair key="efuse_usr_util_percentage" value="0.00" description="" />
|
||||
<keyValuePair key="frame_ecce2_available" value="1" description="" />
|
||||
<keyValuePair key="frame_ecce2_fixed" value="0" description="" />
|
||||
<keyValuePair key="frame_ecce2_used" value="0" description="" />
|
||||
<keyValuePair key="frame_ecce2_util_percentage" value="0.00" description="" />
|
||||
<keyValuePair key="icape2_available" value="2" description="" />
|
||||
<keyValuePair key="icape2_fixed" value="0" description="" />
|
||||
<keyValuePair key="icape2_used" value="0" description="" />
|
||||
<keyValuePair key="icape2_util_percentage" value="0.00" description="" />
|
||||
<keyValuePair key="pcie_2_1_available" value="1" description="" />
|
||||
<keyValuePair key="pcie_2_1_fixed" value="0" description="" />
|
||||
<keyValuePair key="pcie_2_1_used" value="0" description="" />
|
||||
<keyValuePair key="pcie_2_1_util_percentage" value="0.00" description="" />
|
||||
<keyValuePair key="startupe2_available" value="1" description="" />
|
||||
<keyValuePair key="startupe2_fixed" value="0" description="" />
|
||||
<keyValuePair key="startupe2_used" value="0" description="" />
|
||||
<keyValuePair key="startupe2_util_percentage" value="0.00" description="" />
|
||||
<keyValuePair key="xadc_available" value="1" description="" />
|
||||
<keyValuePair key="xadc_fixed" value="0" description="" />
|
||||
<keyValuePair key="xadc_used" value="0" description="" />
|
||||
<keyValuePair key="xadc_util_percentage" value="0.00" description="" />
|
||||
</section>
|
||||
</section>
|
||||
<section name="router" level="1" order="5" description="">
|
||||
<section name="usage" level="2" order="1" description="">
|
||||
<keyValuePair key="actual_expansions" value="1207" description="" />
|
||||
<keyValuePair key="bogomips" value="0" description="" />
|
||||
<keyValuePair key="bram18" value="0" description="" />
|
||||
<keyValuePair key="bram36" value="0" description="" />
|
||||
<keyValuePair key="bufg" value="0" description="" />
|
||||
<keyValuePair key="bufr" value="0" description="" />
|
||||
<keyValuePair key="ctrls" value="0" description="" />
|
||||
<keyValuePair key="dsp" value="0" description="" />
|
||||
<keyValuePair key="effort" value="2" description="" />
|
||||
<keyValuePair key="estimated_expansions" value="7956" description="" />
|
||||
<keyValuePair key="ff" value="0" description="" />
|
||||
<keyValuePair key="global_clocks" value="0" description="" />
|
||||
<keyValuePair key="high_fanout_nets" value="0" description="" />
|
||||
<keyValuePair key="iob" value="7" description="" />
|
||||
<keyValuePair key="lut" value="1" description="" />
|
||||
<keyValuePair key="movable_instances" value="8" description="" />
|
||||
<keyValuePair key="nets" value="14" description="" />
|
||||
<keyValuePair key="pins" value="21" description="" />
|
||||
<keyValuePair key="pll" value="0" description="" />
|
||||
<keyValuePair key="router_runtime" value="0.000000" description="" />
|
||||
<keyValuePair key="router_timing_driven" value="1" description="" />
|
||||
<keyValuePair key="threads" value="2" description="" />
|
||||
<keyValuePair key="timing_constraints_exist" value="1" description="" />
|
||||
</section>
|
||||
</section>
|
||||
<section name="synthesis" level="1" order="6" description="">
|
||||
<section name="command_line_options" level="2" order="1" description="">
|
||||
<keyValuePair key="-assert" value="default::[not_specified]" description="" />
|
||||
<keyValuePair key="-bufg" value="default::12" description="" />
|
||||
<keyValuePair key="-cascade_dsp" value="default::auto" description="" />
|
||||
<keyValuePair key="-constrset" value="default::[not_specified]" description="" />
|
||||
<keyValuePair key="-control_set_opt_threshold" value="default::auto" description="" />
|
||||
<keyValuePair key="-directive" value="default::default" description="" />
|
||||
<keyValuePair key="-fanout_limit" value="default::10000" description="" />
|
||||
<keyValuePair key="-flatten_hierarchy" value="default::rebuilt" description="" />
|
||||
<keyValuePair key="-fsm_extraction" value="default::auto" description="" />
|
||||
<keyValuePair key="-gated_clock_conversion" value="default::off" description="" />
|
||||
<keyValuePair key="-generic" value="default::[not_specified]" description="" />
|
||||
<keyValuePair key="-include_dirs" value="default::[not_specified]" description="" />
|
||||
<keyValuePair key="-keep_equivalent_registers" value="default::[not_specified]" description="" />
|
||||
<keyValuePair key="-max_bram" value="default::-1" description="" />
|
||||
<keyValuePair key="-max_bram_cascade_height" value="default::-1" description="" />
|
||||
<keyValuePair key="-max_dsp" value="default::-1" description="" />
|
||||
<keyValuePair key="-max_uram" value="default::-1" description="" />
|
||||
<keyValuePair key="-max_uram_cascade_height" value="default::-1" description="" />
|
||||
<keyValuePair key="-mode" value="default::default" description="" />
|
||||
<keyValuePair key="-name" value="default::[not_specified]" description="" />
|
||||
<keyValuePair key="-no_lc" value="default::[not_specified]" description="" />
|
||||
<keyValuePair key="-no_srlextract" value="default::[not_specified]" description="" />
|
||||
<keyValuePair key="-no_timing_driven" value="default::[not_specified]" description="" />
|
||||
<keyValuePair key="-part" value="xc7a35tcsg324-1" description="" />
|
||||
<keyValuePair key="-resource_sharing" value="default::auto" description="" />
|
||||
<keyValuePair key="-retiming" value="default::[not_specified]" description="" />
|
||||
<keyValuePair key="-rtl" value="default::[not_specified]" description="" />
|
||||
<keyValuePair key="-rtl_skip_constraints" value="default::[not_specified]" description="" />
|
||||
<keyValuePair key="-rtl_skip_ip" value="default::[not_specified]" description="" />
|
||||
<keyValuePair key="-seu_protect" value="default::none" description="" />
|
||||
<keyValuePair key="-sfcu" value="default::[not_specified]" description="" />
|
||||
<keyValuePair key="-shreg_min_size" value="default::3" description="" />
|
||||
<keyValuePair key="-top" value="mux41" description="" />
|
||||
<keyValuePair key="-verilog_define" value="default::[not_specified]" description="" />
|
||||
</section>
|
||||
<section name="usage" level="2" order="2" description="">
|
||||
<keyValuePair key="elapsed" value="00:00:23s" description="" />
|
||||
<keyValuePair key="hls_ip" value="0" description="" />
|
||||
<keyValuePair key="memory_gain" value="484.586MB" description="" />
|
||||
<keyValuePair key="memory_peak" value="786.168MB" description="" />
|
||||
</section>
|
||||
</section>
|
||||
<section name="unisim_transformation" level="1" order="7" description="">
|
||||
<section name="post_unisim_transformation" level="2" order="1" description="">
|
||||
<keyValuePair key="ibuf" value="6" description="" />
|
||||
<keyValuePair key="lut6" value="1" description="" />
|
||||
<keyValuePair key="obuf" value="1" description="" />
|
||||
</section>
|
||||
<section name="pre_unisim_transformation" level="2" order="2" description="">
|
||||
<keyValuePair key="ibuf" value="6" description="" />
|
||||
<keyValuePair key="lut6" value="1" description="" />
|
||||
<keyValuePair key="obuf" value="1" description="" />
|
||||
</section>
|
||||
</section>
|
||||
<section name="vivado_usage" level="1" order="8" description="">
|
||||
<section name="gui_handlers" level="2" order="1" description="">
|
||||
<keyValuePair key="addsrcwizard_specify_hdl_netlist_block_design" value="1" description="" />
|
||||
<keyValuePair key="addsrcwizard_specify_simulation_specific_hdl_files" value="1" description="" />
|
||||
<keyValuePair key="basedialog_cancel" value="3" description="" />
|
||||
<keyValuePair key="basedialog_ok" value="22" description="" />
|
||||
<keyValuePair key="basedialog_yes" value="1" description="" />
|
||||
<keyValuePair key="createconstraintsfilepanel_file_name" value="1" description="" />
|
||||
<keyValuePair key="createsrcfiledialog_file_name" value="6" description="" />
|
||||
<keyValuePair key="filesetpanel_file_set_panel_tree" value="67" description="" />
|
||||
<keyValuePair key="flownavigatortreepanel_flow_navigator_tree" value="13" description="" />
|
||||
<keyValuePair key="fpgachooser_fpga_table" value="2" description="" />
|
||||
<keyValuePair key="graphicalview_zoom_fit" value="1" description="" />
|
||||
<keyValuePair key="mainmenumgr_checkpoint" value="1" description="" />
|
||||
<keyValuePair key="mainmenumgr_design_hubs" value="1" description="" />
|
||||
<keyValuePair key="mainmenumgr_edit" value="10" description="" />
|
||||
<keyValuePair key="mainmenumgr_file" value="16" description="" />
|
||||
<keyValuePair key="mainmenumgr_floorplanning" value="1" description="" />
|
||||
<keyValuePair key="mainmenumgr_flow" value="2" description="" />
|
||||
<keyValuePair key="mainmenumgr_help" value="6" description="" />
|
||||
<keyValuePair key="mainmenumgr_io_planning" value="1" description="" />
|
||||
<keyValuePair key="mainmenumgr_open_recent_project" value="3" description="" />
|
||||
<keyValuePair key="mainmenumgr_project" value="10" description="" />
|
||||
<keyValuePair key="mainmenumgr_reports" value="6" description="" />
|
||||
<keyValuePair key="mainmenumgr_settings" value="2" description="" />
|
||||
<keyValuePair key="mainmenumgr_tools" value="6" description="" />
|
||||
<keyValuePair key="mainmenumgr_view" value="4" description="" />
|
||||
<keyValuePair key="mainmenumgr_window" value="2" description="" />
|
||||
<keyValuePair key="mainwinmenumgr_layout" value="2" description="" />
|
||||
<keyValuePair key="messagewithoptiondialog_dont_show_this_dialog_again" value="1" description="" />
|
||||
<keyValuePair key="pacommandnames_auto_update_hier" value="4" description="" />
|
||||
<keyValuePair key="pacommandnames_close_project" value="2" description="" />
|
||||
<keyValuePair key="pacommandnames_goto_netlist_design" value="1" description="" />
|
||||
<keyValuePair key="pacommandnames_license_manage" value="1" description="" />
|
||||
<keyValuePair key="pacommandnames_new_project" value="1" description="" />
|
||||
<keyValuePair key="pacommandnames_run_bitgen" value="1" description="" />
|
||||
<keyValuePair key="pacommandnames_simulation_run" value="1" description="" />
|
||||
<keyValuePair key="pacommandnames_simulation_run_behavioral" value="4" description="" />
|
||||
<keyValuePair key="pacommandnames_src_replace_file" value="1" description="" />
|
||||
<keyValuePair key="progressdialog_cancel" value="1" description="" />
|
||||
<keyValuePair key="projectnamechooser_project_name" value="1" description="" />
|
||||
<keyValuePair key="rdicommands_copy" value="1" description="" />
|
||||
<keyValuePair key="rdicommands_custom_commands" value="6" description="" />
|
||||
<keyValuePair key="rdicommands_delete" value="1" description="" />
|
||||
<keyValuePair key="rdicommands_properties" value="1" description="" />
|
||||
<keyValuePair key="rdicommands_redo" value="2" description="" />
|
||||
<keyValuePair key="rdicommands_settings" value="1" description="" />
|
||||
<keyValuePair key="rdicommands_undo" value="1" description="" />
|
||||
<keyValuePair key="removesourcesdialog_also_delete" value="1" description="" />
|
||||
<keyValuePair key="saveprojectutils_cancel" value="1" description="" />
|
||||
<keyValuePair key="saveprojectutils_save" value="1" description="" />
|
||||
<keyValuePair key="settingsdialog_options_tree" value="1" description="" />
|
||||
<keyValuePair key="settingsdialog_project_tree" value="6" description="" />
|
||||
<keyValuePair key="signaltreepanel_signal_tree_table" value="20" description="" />
|
||||
<keyValuePair key="srcchooserpanel_add_hdl_and_netlist_files_to_your_project" value="1" description="" />
|
||||
<keyValuePair key="srcchooserpanel_add_or_create_source_file" value="1" description="" />
|
||||
<keyValuePair key="srcchooserpanel_create_file" value="4" description="" />
|
||||
<keyValuePair key="srcmenu_ip_hierarchy" value="2" description="" />
|
||||
<keyValuePair key="syntheticagettingstartedview_recent_projects" value="5" description="" />
|
||||
<keyValuePair key="taskbanner_close" value="1" description="" />
|
||||
<keyValuePair key="verilogoptionschooserpanel_specify_compilation_options_for_verilog" value="1" description="" />
|
||||
</section>
|
||||
<section name="java_command_handlers" level="2" order="2" description="">
|
||||
<keyValuePair key="addsources" value="4" description="" />
|
||||
<keyValuePair key="closeproject" value="2" description="" />
|
||||
<keyValuePair key="customizemenusandtoolbars" value="1" description="" />
|
||||
<keyValuePair key="editdelete" value="1" description="" />
|
||||
<keyValuePair key="editproperties" value="1" description="" />
|
||||
<keyValuePair key="fileprintcmdhandler" value="1" description="" />
|
||||
<keyValuePair key="markselection" value="1" description="" />
|
||||
<keyValuePair key="newproject" value="1" description="" />
|
||||
<keyValuePair key="runbitgen" value="1" description="" />
|
||||
<keyValuePair key="runimplementation" value="1" description="" />
|
||||
<keyValuePair key="runsynthesis" value="1" description="" />
|
||||
<keyValuePair key="savedesign" value="1" description="" />
|
||||
<keyValuePair key="savefileproxyhandler" value="1" description="" />
|
||||
<keyValuePair key="simulationrun" value="3" description="" />
|
||||
<keyValuePair key="toolssettings" value="1" description="" />
|
||||
<keyValuePair key="updateregid" value="1" description="" />
|
||||
<keyValuePair key="updatesourcefiles" value="1" description="" />
|
||||
<keyValuePair key="viewtaskrtlanalysis" value="2" description="" />
|
||||
<keyValuePair key="viewtasksynthesis" value="1" description="" />
|
||||
</section>
|
||||
<section name="other_data" level="2" order="3" description="">
|
||||
<keyValuePair key="guimode" value="6" description="" />
|
||||
</section>
|
||||
<section name="project_data" level="2" order="4" description="">
|
||||
<keyValuePair key="constraintsetcount" value="1" description="" />
|
||||
<keyValuePair key="core_container" value="false" description="" />
|
||||
<keyValuePair key="currentimplrun" value="impl_1" description="" />
|
||||
<keyValuePair key="currentsynthesisrun" value="synth_1" description="" />
|
||||
<keyValuePair key="default_library" value="xil_defaultlib" description="" />
|
||||
<keyValuePair key="designmode" value="RTL" description="" />
|
||||
<keyValuePair key="export_simulation_activehdl" value="0" description="" />
|
||||
<keyValuePair key="export_simulation_ies" value="0" description="" />
|
||||
<keyValuePair key="export_simulation_modelsim" value="0" description="" />
|
||||
<keyValuePair key="export_simulation_questa" value="0" description="" />
|
||||
<keyValuePair key="export_simulation_riviera" value="0" description="" />
|
||||
<keyValuePair key="export_simulation_vcs" value="0" description="" />
|
||||
<keyValuePair key="export_simulation_xsim" value="0" description="" />
|
||||
<keyValuePair key="implstrategy" value="Vivado Implementation Defaults" description="" />
|
||||
<keyValuePair key="launch_simulation_activehdl" value="0" description="" />
|
||||
<keyValuePair key="launch_simulation_ies" value="0" description="" />
|
||||
<keyValuePair key="launch_simulation_modelsim" value="0" description="" />
|
||||
<keyValuePair key="launch_simulation_questa" value="0" description="" />
|
||||
<keyValuePair key="launch_simulation_riviera" value="0" description="" />
|
||||
<keyValuePair key="launch_simulation_vcs" value="0" description="" />
|
||||
<keyValuePair key="launch_simulation_xsim" value="3" description="" />
|
||||
<keyValuePair key="simulator_language" value="Mixed" description="" />
|
||||
<keyValuePair key="srcsetcount" value="2" description="" />
|
||||
<keyValuePair key="synthesisstrategy" value="Vivado Synthesis Defaults" description="" />
|
||||
<keyValuePair key="target_language" value="Verilog" description="" />
|
||||
<keyValuePair key="target_simulator" value="XSim" description="" />
|
||||
<keyValuePair key="totalimplruns" value="1" description="" />
|
||||
<keyValuePair key="totalsynthesisruns" value="1" description="" />
|
||||
</section>
|
||||
</section>
|
||||
<section name="xsim" level="1" order="9" description="">
|
||||
<section name="command_line_options" level="2" order="1" description="">
|
||||
<keyValuePair key="-sim_mode" value="default::behavioral" description="" />
|
||||
<keyValuePair key="-sim_type" value="default::" description="" />
|
||||
</section>
|
||||
</section>
|
||||
</section>
|
||||
</webTalkData>
|
||||
12
Exp1-2-2/Exp1-2-2.runs/impl_1/vivado.jou
Normal file
12
Exp1-2-2/Exp1-2-2.runs/impl_1/vivado.jou
Normal file
@@ -0,0 +1,12 @@
|
||||
#-----------------------------------------------------------
|
||||
# Vivado v2018.1 (64-bit)
|
||||
# SW Build 2188600 on Wed Apr 4 18:40:38 MDT 2018
|
||||
# IP Build 2185939 on Wed Apr 4 20:55:05 MDT 2018
|
||||
# Start of session at: Thu Sep 26 11:16:29 2024
|
||||
# Process ID: 4044
|
||||
# Current directory: F:/Schoolwork/DigitalLogic/Exp1-2-2/Exp1-2-2.runs/impl_1
|
||||
# Command line: vivado.exe -log mux41.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source mux41.tcl -notrace
|
||||
# Log file: F:/Schoolwork/DigitalLogic/Exp1-2-2/Exp1-2-2.runs/impl_1/mux41.vdi
|
||||
# Journal file: F:/Schoolwork/DigitalLogic/Exp1-2-2/Exp1-2-2.runs/impl_1\vivado.jou
|
||||
#-----------------------------------------------------------
|
||||
source mux41.tcl -notrace
|
||||
BIN
Exp1-2-2/Exp1-2-2.runs/impl_1/vivado.pb
Normal file
BIN
Exp1-2-2/Exp1-2-2.runs/impl_1/vivado.pb
Normal file
Binary file not shown.
12
Exp1-2-2/Exp1-2-2.runs/impl_1/vivado_5212.backup.jou
Normal file
12
Exp1-2-2/Exp1-2-2.runs/impl_1/vivado_5212.backup.jou
Normal file
@@ -0,0 +1,12 @@
|
||||
#-----------------------------------------------------------
|
||||
# Vivado v2018.1 (64-bit)
|
||||
# SW Build 2188600 on Wed Apr 4 18:40:38 MDT 2018
|
||||
# IP Build 2185939 on Wed Apr 4 20:55:05 MDT 2018
|
||||
# Start of session at: Thu Sep 26 11:15:35 2024
|
||||
# Process ID: 5212
|
||||
# Current directory: F:/Schoolwork/DigitalLogic/Exp1-2-2/Exp1-2-2.runs/impl_1
|
||||
# Command line: vivado.exe -log mux41.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source mux41.tcl -notrace
|
||||
# Log file: F:/Schoolwork/DigitalLogic/Exp1-2-2/Exp1-2-2.runs/impl_1/mux41.vdi
|
||||
# Journal file: F:/Schoolwork/DigitalLogic/Exp1-2-2/Exp1-2-2.runs/impl_1\vivado.jou
|
||||
#-----------------------------------------------------------
|
||||
source mux41.tcl -notrace
|
||||
BIN
Exp1-2-2/Exp1-2-2.runs/impl_1/write_bitstream.pb
Normal file
BIN
Exp1-2-2/Exp1-2-2.runs/impl_1/write_bitstream.pb
Normal file
Binary file not shown.
15
Exp1-2-2/Exp1-2-2.runs/synth_1/.Xil/mux41_propImpl.xdc
Normal file
15
Exp1-2-2/Exp1-2-2.runs/synth_1/.Xil/mux41_propImpl.xdc
Normal file
@@ -0,0 +1,15 @@
|
||||
set_property SRC_FILE_INFO {cfile:F:/Schoolwork/DigitalLogic/Exp1-2-2/Exp1-2-2.srcs/constrs_1/new/mux41.xdc rfile:../../../Exp1-2-2.srcs/constrs_1/new/mux41.xdc id:1} [current_design]
|
||||
set_property src_info {type:XDC file:1 line:1 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PACKAGE_PIN P5 [get_ports {I[0]}]
|
||||
set_property src_info {type:XDC file:1 line:2 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PACKAGE_PIN P4 [get_ports {I[1]}]
|
||||
set_property src_info {type:XDC file:1 line:3 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PACKAGE_PIN P3 [get_ports {I[2]}]
|
||||
set_property src_info {type:XDC file:1 line:4 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PACKAGE_PIN P2 [get_ports {I[3]}]
|
||||
set_property src_info {type:XDC file:1 line:5 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PACKAGE_PIN R2 [get_ports {S[1]}]
|
||||
set_property src_info {type:XDC file:1 line:6 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PACKAGE_PIN M4 [get_ports {S[0]}]
|
||||
set_property src_info {type:XDC file:1 line:13 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PACKAGE_PIN F6 [get_ports Y]
|
||||
48
Exp1-2-2/Exp1-2-2.runs/synth_1/gen_run.xml
Normal file
48
Exp1-2-2/Exp1-2-2.runs/synth_1/gen_run.xml
Normal file
@@ -0,0 +1,48 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<GenRun Id="synth_1" LaunchPart="xc7a35tcsg324-1" LaunchTime="1727320500">
|
||||
<File Type="PA-TCL" Name="mux41.tcl"/>
|
||||
<File Type="REPORTS-TCL" Name="mux41_reports.tcl"/>
|
||||
<File Type="RDS-RDS" Name="mux41.vds"/>
|
||||
<File Type="RDS-UTIL" Name="mux41_utilization_synth.rpt"/>
|
||||
<File Type="RDS-UTIL-PB" Name="mux41_utilization_synth.pb"/>
|
||||
<File Type="RDS-DCP" Name="mux41.dcp"/>
|
||||
<FileSet Name="sources" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1">
|
||||
<Filter Type="Srcs"/>
|
||||
<File Path="$PSRCDIR/sources_1/new/mux21.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PSRCDIR/sources_1/new/mux41.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<Config>
|
||||
<Option Name="DesignMode" Val="RTL"/>
|
||||
<Option Name="TopModule" Val="mux41"/>
|
||||
<Option Name="TopAutoSet" Val="TRUE"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="constrs_in" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1">
|
||||
<Filter Type="Constrs"/>
|
||||
<File Path="$PSRCDIR/constrs_1/new/mux41.xdc">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<Config>
|
||||
<Option Name="TargetConstrsFile" Val="$PSRCDIR/constrs_1/new/mux41.xdc"/>
|
||||
<Option Name="ConstrsType" Val="XDC"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2018"/>
|
||||
<Step Id="synth_design"/>
|
||||
</Strategy>
|
||||
</GenRun>
|
||||
9
Exp1-2-2/Exp1-2-2.runs/synth_1/htr.txt
Normal file
9
Exp1-2-2/Exp1-2-2.runs/synth_1/htr.txt
Normal file
@@ -0,0 +1,9 @@
|
||||
REM
|
||||
REM Vivado(TM)
|
||||
REM htr.txt: a Vivado-generated description of how-to-repeat the
|
||||
REM the basic steps of a run. Note that runme.bat/sh needs
|
||||
REM to be invoked for Vivado to track run status.
|
||||
REM Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
|
||||
REM
|
||||
|
||||
vivado -log mux41.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source mux41.tcl
|
||||
BIN
Exp1-2-2/Exp1-2-2.runs/synth_1/mux41.dcp
Normal file
BIN
Exp1-2-2/Exp1-2-2.runs/synth_1/mux41.dcp
Normal file
Binary file not shown.
57
Exp1-2-2/Exp1-2-2.runs/synth_1/mux41.tcl
Normal file
57
Exp1-2-2/Exp1-2-2.runs/synth_1/mux41.tcl
Normal file
@@ -0,0 +1,57 @@
|
||||
#
|
||||
# Synthesis run script generated by Vivado
|
||||
#
|
||||
|
||||
proc create_report { reportName command } {
|
||||
set status "."
|
||||
append status $reportName ".fail"
|
||||
if { [file exists $status] } {
|
||||
eval file delete [glob $status]
|
||||
}
|
||||
send_msg_id runtcl-4 info "Executing : $command"
|
||||
set retval [eval catch { $command } msg]
|
||||
if { $retval != 0 } {
|
||||
set fp [open $status w]
|
||||
close $fp
|
||||
send_msg_id runtcl-5 warning "$msg"
|
||||
}
|
||||
}
|
||||
set_param xicom.use_bs_reader 1
|
||||
create_project -in_memory -part xc7a35tcsg324-1
|
||||
|
||||
set_param project.singleFileAddWarning.threshold 0
|
||||
set_param project.compositeFile.enableAutoGeneration 0
|
||||
set_param synth.vivado.isSynthRun true
|
||||
set_property webtalk.parent_dir F:/Schoolwork/DigitalLogic/Exp1-2-2/Exp1-2-2.cache/wt [current_project]
|
||||
set_property parent.project_path F:/Schoolwork/DigitalLogic/Exp1-2-2/Exp1-2-2.xpr [current_project]
|
||||
set_property default_lib xil_defaultlib [current_project]
|
||||
set_property target_language Verilog [current_project]
|
||||
set_property ip_output_repo f:/Schoolwork/DigitalLogic/Exp1-2-2/Exp1-2-2.cache/ip [current_project]
|
||||
set_property ip_cache_permissions {read write} [current_project]
|
||||
read_verilog -library xil_defaultlib {
|
||||
F:/Schoolwork/DigitalLogic/Exp1-2-2/Exp1-2-2.srcs/sources_1/new/mux21.v
|
||||
F:/Schoolwork/DigitalLogic/Exp1-2-2/Exp1-2-2.srcs/sources_1/new/mux41.v
|
||||
}
|
||||
# Mark all dcp files as not used in implementation to prevent them from being
|
||||
# stitched into the results of this synthesis run. Any black boxes in the
|
||||
# design are intentionally left as such for best results. Dcp files will be
|
||||
# stitched into the design at a later time, either when this synthesis run is
|
||||
# opened, or when it is stitched into a dependent implementation run.
|
||||
foreach dcp [get_files -quiet -all -filter file_type=="Design\ Checkpoint"] {
|
||||
set_property used_in_implementation false $dcp
|
||||
}
|
||||
read_xdc F:/Schoolwork/DigitalLogic/Exp1-2-2/Exp1-2-2.srcs/constrs_1/new/mux41.xdc
|
||||
set_property used_in_implementation false [get_files F:/Schoolwork/DigitalLogic/Exp1-2-2/Exp1-2-2.srcs/constrs_1/new/mux41.xdc]
|
||||
|
||||
set_param ips.enableIPCacheLiteLoad 0
|
||||
close [open __synthesis_is_running__ w]
|
||||
|
||||
synth_design -top mux41 -part xc7a35tcsg324-1
|
||||
|
||||
|
||||
# disable binary constraint mode for synth run checkpoints
|
||||
set_param constraints.enableBinaryConstraints false
|
||||
write_checkpoint -force -noxdef mux41.dcp
|
||||
create_report "synth_1_synth_report_utilization_0" "report_utilization -file mux41_utilization_synth.rpt -pb mux41_utilization_synth.pb"
|
||||
file delete __synthesis_is_running__
|
||||
close [open __synthesis_is_complete__ w]
|
||||
264
Exp1-2-2/Exp1-2-2.runs/synth_1/mux41.vds
Normal file
264
Exp1-2-2/Exp1-2-2.runs/synth_1/mux41.vds
Normal file
@@ -0,0 +1,264 @@
|
||||
#-----------------------------------------------------------
|
||||
# Vivado v2018.1 (64-bit)
|
||||
# SW Build 2188600 on Wed Apr 4 18:40:38 MDT 2018
|
||||
# IP Build 2185939 on Wed Apr 4 20:55:05 MDT 2018
|
||||
# Start of session at: Thu Sep 26 11:15:01 2024
|
||||
# Process ID: 2832
|
||||
# Current directory: F:/Schoolwork/DigitalLogic/Exp1-2-2/Exp1-2-2.runs/synth_1
|
||||
# Command line: vivado.exe -log mux41.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source mux41.tcl
|
||||
# Log file: F:/Schoolwork/DigitalLogic/Exp1-2-2/Exp1-2-2.runs/synth_1/mux41.vds
|
||||
# Journal file: F:/Schoolwork/DigitalLogic/Exp1-2-2/Exp1-2-2.runs/synth_1\vivado.jou
|
||||
#-----------------------------------------------------------
|
||||
source mux41.tcl -notrace
|
||||
Command: synth_design -top mux41 -part xc7a35tcsg324-1
|
||||
Starting synth_design
|
||||
Attempting to get a license for feature 'Synthesis' and/or device 'xc7a35t'
|
||||
INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7a35t'
|
||||
INFO: Launching helper process for spawning children vivado processes
|
||||
INFO: Helper process launched with PID 1156
|
||||
---------------------------------------------------------------------------------
|
||||
Starting RTL Elaboration : Time (s): cpu = 00:00:04 ; elapsed = 00:00:03 . Memory (MB): peak = 409.477 ; gain = 96.402
|
||||
---------------------------------------------------------------------------------
|
||||
INFO: [Synth 8-6157] synthesizing module 'mux41' [F:/Schoolwork/DigitalLogic/Exp1-2-2/Exp1-2-2.srcs/sources_1/new/mux41.v:23]
|
||||
INFO: [Synth 8-6157] synthesizing module 'mux21' [F:/Schoolwork/DigitalLogic/Exp1-2-2/Exp1-2-2.srcs/sources_1/new/mux21.v:23]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'mux21' (1#1) [F:/Schoolwork/DigitalLogic/Exp1-2-2/Exp1-2-2.srcs/sources_1/new/mux21.v:23]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'mux41' (2#1) [F:/Schoolwork/DigitalLogic/Exp1-2-2/Exp1-2-2.srcs/sources_1/new/mux41.v:23]
|
||||
---------------------------------------------------------------------------------
|
||||
Finished RTL Elaboration : Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 464.418 ; gain = 151.344
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report Check Netlist:
|
||||
+------+------------------+-------+---------+-------+------------------+
|
||||
| |Item |Errors |Warnings |Status |Description |
|
||||
+------+------------------+-------+---------+-------+------------------+
|
||||
|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets |
|
||||
+------+------------------+-------+---------+-------+------------------+
|
||||
---------------------------------------------------------------------------------
|
||||
Start Handling Custom Attributes
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Handling Custom Attributes : Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 464.418 ; gain = 151.344
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 464.418 ; gain = 151.344
|
||||
---------------------------------------------------------------------------------
|
||||
INFO: [Device 21-403] Loading part xc7a35tcsg324-1
|
||||
INFO: [Project 1-570] Preparing netlist for logic optimization
|
||||
|
||||
Processing XDC Constraints
|
||||
Initializing timing engine
|
||||
Parsing XDC File [F:/Schoolwork/DigitalLogic/Exp1-2-2/Exp1-2-2.srcs/constrs_1/new/mux41.xdc]
|
||||
Finished Parsing XDC File [F:/Schoolwork/DigitalLogic/Exp1-2-2/Exp1-2-2.srcs/constrs_1/new/mux41.xdc]
|
||||
INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [F:/Schoolwork/DigitalLogic/Exp1-2-2/Exp1-2-2.srcs/constrs_1/new/mux41.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/mux41_propImpl.xdc].
|
||||
Resolution: To avoid this warning, move constraints listed in [.Xil/mux41_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
|
||||
Completed Processing XDC Constraints
|
||||
|
||||
INFO: [Project 1-111] Unisim Transformation Summary:
|
||||
No Unisim elements were transformed.
|
||||
|
||||
Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 715.266 ; gain = 0.000
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Constraint Validation : Time (s): cpu = 00:00:12 ; elapsed = 00:00:13 . Memory (MB): peak = 715.266 ; gain = 402.191
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Loading Part and Timing Information
|
||||
---------------------------------------------------------------------------------
|
||||
Loading part: xc7a35tcsg324-1
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Loading Part and Timing Information : Time (s): cpu = 00:00:12 ; elapsed = 00:00:13 . Memory (MB): peak = 715.266 ; gain = 402.191
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Applying 'set_property' XDC Constraints
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:12 ; elapsed = 00:00:13 . Memory (MB): peak = 715.266 ; gain = 402.191
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:12 ; elapsed = 00:00:13 . Memory (MB): peak = 715.266 ; gain = 402.191
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report RTL Partitions:
|
||||
+-+--------------+------------+----------+
|
||||
| |RTL Partition |Replication |Instances |
|
||||
+-+--------------+------------+----------+
|
||||
+-+--------------+------------+----------+
|
||||
---------------------------------------------------------------------------------
|
||||
Start RTL Component Statistics
|
||||
---------------------------------------------------------------------------------
|
||||
Detailed RTL Component Info :
|
||||
+---Muxes :
|
||||
2 Input 1 Bit Muxes := 3
|
||||
---------------------------------------------------------------------------------
|
||||
Finished RTL Component Statistics
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start RTL Hierarchical Component Statistics
|
||||
---------------------------------------------------------------------------------
|
||||
Hierarchical RTL Component report
|
||||
Module mux21
|
||||
Detailed RTL Component Info :
|
||||
+---Muxes :
|
||||
2 Input 1 Bit Muxes := 1
|
||||
---------------------------------------------------------------------------------
|
||||
Finished RTL Hierarchical Component Statistics
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Part Resource Summary
|
||||
---------------------------------------------------------------------------------
|
||||
Part Resources:
|
||||
DSPs: 90 (col length:60)
|
||||
BRAMs: 100 (col length: RAMB18 60 RAMB36 30)
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Part Resource Summary
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Cross Boundary and Area Optimization
|
||||
---------------------------------------------------------------------------------
|
||||
Warning: Parallel synthesis criteria is not met
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:12 ; elapsed = 00:00:13 . Memory (MB): peak = 715.266 ; gain = 402.191
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report RTL Partitions:
|
||||
+-+--------------+------------+----------+
|
||||
| |RTL Partition |Replication |Instances |
|
||||
+-+--------------+------------+----------+
|
||||
+-+--------------+------------+----------+
|
||||
---------------------------------------------------------------------------------
|
||||
Start Applying XDC Timing Constraints
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:18 ; elapsed = 00:00:21 . Memory (MB): peak = 785.012 ; gain = 471.938
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Timing Optimization
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Timing Optimization : Time (s): cpu = 00:00:18 ; elapsed = 00:00:21 . Memory (MB): peak = 785.012 ; gain = 471.938
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report RTL Partitions:
|
||||
+-+--------------+------------+----------+
|
||||
| |RTL Partition |Replication |Instances |
|
||||
+-+--------------+------------+----------+
|
||||
+-+--------------+------------+----------+
|
||||
---------------------------------------------------------------------------------
|
||||
Start Technology Mapping
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Technology Mapping : Time (s): cpu = 00:00:18 ; elapsed = 00:00:21 . Memory (MB): peak = 785.012 ; gain = 471.938
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report RTL Partitions:
|
||||
+-+--------------+------------+----------+
|
||||
| |RTL Partition |Replication |Instances |
|
||||
+-+--------------+------------+----------+
|
||||
+-+--------------+------------+----------+
|
||||
---------------------------------------------------------------------------------
|
||||
Start IO Insertion
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Flattening Before IO Insertion
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Flattening Before IO Insertion
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Final Netlist Cleanup
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Final Netlist Cleanup
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished IO Insertion : Time (s): cpu = 00:00:19 ; elapsed = 00:00:21 . Memory (MB): peak = 786.141 ; gain = 473.066
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report Check Netlist:
|
||||
+------+------------------+-------+---------+-------+------------------+
|
||||
| |Item |Errors |Warnings |Status |Description |
|
||||
+------+------------------+-------+---------+-------+------------------+
|
||||
|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets |
|
||||
+------+------------------+-------+---------+-------+------------------+
|
||||
---------------------------------------------------------------------------------
|
||||
Start Renaming Generated Instances
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Renaming Generated Instances : Time (s): cpu = 00:00:19 ; elapsed = 00:00:21 . Memory (MB): peak = 786.141 ; gain = 473.066
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report RTL Partitions:
|
||||
+-+--------------+------------+----------+
|
||||
| |RTL Partition |Replication |Instances |
|
||||
+-+--------------+------------+----------+
|
||||
+-+--------------+------------+----------+
|
||||
---------------------------------------------------------------------------------
|
||||
Start Rebuilding User Hierarchy
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:19 ; elapsed = 00:00:21 . Memory (MB): peak = 786.141 ; gain = 473.066
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Renaming Generated Ports
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Renaming Generated Ports : Time (s): cpu = 00:00:19 ; elapsed = 00:00:21 . Memory (MB): peak = 786.141 ; gain = 473.066
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Handling Custom Attributes
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Handling Custom Attributes : Time (s): cpu = 00:00:19 ; elapsed = 00:00:21 . Memory (MB): peak = 786.141 ; gain = 473.066
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Renaming Generated Nets
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Renaming Generated Nets : Time (s): cpu = 00:00:19 ; elapsed = 00:00:21 . Memory (MB): peak = 786.141 ; gain = 473.066
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Writing Synthesis Report
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report BlackBoxes:
|
||||
+-+--------------+----------+
|
||||
| |BlackBox name |Instances |
|
||||
+-+--------------+----------+
|
||||
+-+--------------+----------+
|
||||
|
||||
Report Cell Usage:
|
||||
+------+-----+------+
|
||||
| |Cell |Count |
|
||||
+------+-----+------+
|
||||
|1 |LUT6 | 1|
|
||||
|2 |IBUF | 6|
|
||||
|3 |OBUF | 1|
|
||||
+------+-----+------+
|
||||
|
||||
Report Instance Areas:
|
||||
+------+---------+-------+------+
|
||||
| |Instance |Module |Cells |
|
||||
+------+---------+-------+------+
|
||||
|1 |top | | 8|
|
||||
+------+---------+-------+------+
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Writing Synthesis Report : Time (s): cpu = 00:00:19 ; elapsed = 00:00:21 . Memory (MB): peak = 786.141 ; gain = 473.066
|
||||
---------------------------------------------------------------------------------
|
||||
Synthesis finished with 0 errors, 0 critical warnings and 0 warnings.
|
||||
Synthesis Optimization Runtime : Time (s): cpu = 00:00:10 ; elapsed = 00:00:16 . Memory (MB): peak = 786.168 ; gain = 222.246
|
||||
Synthesis Optimization Complete : Time (s): cpu = 00:00:19 ; elapsed = 00:00:21 . Memory (MB): peak = 786.168 ; gain = 473.094
|
||||
INFO: [Project 1-571] Translating synthesized netlist
|
||||
INFO: [Netlist 29-17] Analyzing 6 Unisim elements for replacement
|
||||
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
|
||||
INFO: [Project 1-570] Preparing netlist for logic optimization
|
||||
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
|
||||
INFO: [Project 1-111] Unisim Transformation Summary:
|
||||
No Unisim elements were transformed.
|
||||
|
||||
INFO: [Common 17-83] Releasing license: Synthesis
|
||||
16 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
||||
synth_design completed successfully
|
||||
synth_design: Time (s): cpu = 00:00:20 ; elapsed = 00:00:24 . Memory (MB): peak = 804.129 ; gain = 503.848
|
||||
INFO: [Common 17-1381] The checkpoint 'F:/Schoolwork/DigitalLogic/Exp1-2-2/Exp1-2-2.runs/synth_1/mux41.dcp' has been generated.
|
||||
INFO: [runtcl-4] Executing : report_utilization -file mux41_utilization_synth.rpt -pb mux41_utilization_synth.pb
|
||||
report_utilization: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.012 . Memory (MB): peak = 804.129 ; gain = 0.000
|
||||
INFO: [Common 17-206] Exiting Vivado at Thu Sep 26 11:15:29 2024...
|
||||
BIN
Exp1-2-2/Exp1-2-2.runs/synth_1/mux41_utilization_synth.pb
Normal file
BIN
Exp1-2-2/Exp1-2-2.runs/synth_1/mux41_utilization_synth.pb
Normal file
Binary file not shown.
170
Exp1-2-2/Exp1-2-2.runs/synth_1/mux41_utilization_synth.rpt
Normal file
170
Exp1-2-2/Exp1-2-2.runs/synth_1/mux41_utilization_synth.rpt
Normal file
@@ -0,0 +1,170 @@
|
||||
Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
|
||||
-----------------------------------------------------------------------------------------------------
|
||||
| Tool Version : Vivado v.2018.1 (win64) Build 2188600 Wed Apr 4 18:40:38 MDT 2018
|
||||
| Date : Thu Sep 26 11:15:29 2024
|
||||
| Host : W10-20240912132 running 64-bit major release (build 9200)
|
||||
| Command : report_utilization -file mux41_utilization_synth.rpt -pb mux41_utilization_synth.pb
|
||||
| Design : mux41
|
||||
| Device : 7a35tcsg324-1
|
||||
| Design State : Synthesized
|
||||
-----------------------------------------------------------------------------------------------------
|
||||
|
||||
Utilization Design Information
|
||||
|
||||
Table of Contents
|
||||
-----------------
|
||||
1. Slice Logic
|
||||
1.1 Summary of Registers by Type
|
||||
2. Memory
|
||||
3. DSP
|
||||
4. IO and GT Specific
|
||||
5. Clocking
|
||||
6. Specific Feature
|
||||
7. Primitives
|
||||
8. Black Boxes
|
||||
9. Instantiated Netlists
|
||||
|
||||
1. Slice Logic
|
||||
--------------
|
||||
|
||||
+-------------------------+------+-------+-----------+-------+
|
||||
| Site Type | Used | Fixed | Available | Util% |
|
||||
+-------------------------+------+-------+-----------+-------+
|
||||
| Slice LUTs* | 1 | 0 | 20800 | <0.01 |
|
||||
| LUT as Logic | 1 | 0 | 20800 | <0.01 |
|
||||
| LUT as Memory | 0 | 0 | 9600 | 0.00 |
|
||||
| Slice Registers | 0 | 0 | 41600 | 0.00 |
|
||||
| Register as Flip Flop | 0 | 0 | 41600 | 0.00 |
|
||||
| Register as Latch | 0 | 0 | 41600 | 0.00 |
|
||||
| F7 Muxes | 0 | 0 | 16300 | 0.00 |
|
||||
| F8 Muxes | 0 | 0 | 8150 | 0.00 |
|
||||
+-------------------------+------+-------+-----------+-------+
|
||||
* Warning! The Final LUT count, after physical optimizations and full implementation, is typically lower. Run opt_design after synthesis, if not already completed, for a more realistic count.
|
||||
|
||||
|
||||
1.1 Summary of Registers by Type
|
||||
--------------------------------
|
||||
|
||||
+-------+--------------+-------------+--------------+
|
||||
| Total | Clock Enable | Synchronous | Asynchronous |
|
||||
+-------+--------------+-------------+--------------+
|
||||
| 0 | _ | - | - |
|
||||
| 0 | _ | - | Set |
|
||||
| 0 | _ | - | Reset |
|
||||
| 0 | _ | Set | - |
|
||||
| 0 | _ | Reset | - |
|
||||
| 0 | Yes | - | - |
|
||||
| 0 | Yes | - | Set |
|
||||
| 0 | Yes | - | Reset |
|
||||
| 0 | Yes | Set | - |
|
||||
| 0 | Yes | Reset | - |
|
||||
+-------+--------------+-------------+--------------+
|
||||
|
||||
|
||||
2. Memory
|
||||
---------
|
||||
|
||||
+----------------+------+-------+-----------+-------+
|
||||
| Site Type | Used | Fixed | Available | Util% |
|
||||
+----------------+------+-------+-----------+-------+
|
||||
| Block RAM Tile | 0 | 0 | 50 | 0.00 |
|
||||
| RAMB36/FIFO* | 0 | 0 | 50 | 0.00 |
|
||||
| RAMB18 | 0 | 0 | 100 | 0.00 |
|
||||
+----------------+------+-------+-----------+-------+
|
||||
* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1
|
||||
|
||||
|
||||
3. DSP
|
||||
------
|
||||
|
||||
+-----------+------+-------+-----------+-------+
|
||||
| Site Type | Used | Fixed | Available | Util% |
|
||||
+-----------+------+-------+-----------+-------+
|
||||
| DSPs | 0 | 0 | 90 | 0.00 |
|
||||
+-----------+------+-------+-----------+-------+
|
||||
|
||||
|
||||
4. IO and GT Specific
|
||||
---------------------
|
||||
|
||||
+-----------------------------+------+-------+-----------+-------+
|
||||
| Site Type | Used | Fixed | Available | Util% |
|
||||
+-----------------------------+------+-------+-----------+-------+
|
||||
| Bonded IOB | 7 | 0 | 210 | 3.33 |
|
||||
| Bonded IPADs | 0 | 0 | 2 | 0.00 |
|
||||
| PHY_CONTROL | 0 | 0 | 5 | 0.00 |
|
||||
| PHASER_REF | 0 | 0 | 5 | 0.00 |
|
||||
| OUT_FIFO | 0 | 0 | 20 | 0.00 |
|
||||
| IN_FIFO | 0 | 0 | 20 | 0.00 |
|
||||
| IDELAYCTRL | 0 | 0 | 5 | 0.00 |
|
||||
| IBUFDS | 0 | 0 | 202 | 0.00 |
|
||||
| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 20 | 0.00 |
|
||||
| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 20 | 0.00 |
|
||||
| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 250 | 0.00 |
|
||||
| ILOGIC | 0 | 0 | 210 | 0.00 |
|
||||
| OLOGIC | 0 | 0 | 210 | 0.00 |
|
||||
+-----------------------------+------+-------+-----------+-------+
|
||||
|
||||
|
||||
5. Clocking
|
||||
-----------
|
||||
|
||||
+------------+------+-------+-----------+-------+
|
||||
| Site Type | Used | Fixed | Available | Util% |
|
||||
+------------+------+-------+-----------+-------+
|
||||
| BUFGCTRL | 0 | 0 | 32 | 0.00 |
|
||||
| BUFIO | 0 | 0 | 20 | 0.00 |
|
||||
| MMCME2_ADV | 0 | 0 | 5 | 0.00 |
|
||||
| PLLE2_ADV | 0 | 0 | 5 | 0.00 |
|
||||
| BUFMRCE | 0 | 0 | 10 | 0.00 |
|
||||
| BUFHCE | 0 | 0 | 72 | 0.00 |
|
||||
| BUFR | 0 | 0 | 20 | 0.00 |
|
||||
+------------+------+-------+-----------+-------+
|
||||
|
||||
|
||||
6. Specific Feature
|
||||
-------------------
|
||||
|
||||
+-------------+------+-------+-----------+-------+
|
||||
| Site Type | Used | Fixed | Available | Util% |
|
||||
+-------------+------+-------+-----------+-------+
|
||||
| BSCANE2 | 0 | 0 | 4 | 0.00 |
|
||||
| CAPTUREE2 | 0 | 0 | 1 | 0.00 |
|
||||
| DNA_PORT | 0 | 0 | 1 | 0.00 |
|
||||
| EFUSE_USR | 0 | 0 | 1 | 0.00 |
|
||||
| FRAME_ECCE2 | 0 | 0 | 1 | 0.00 |
|
||||
| ICAPE2 | 0 | 0 | 2 | 0.00 |
|
||||
| PCIE_2_1 | 0 | 0 | 1 | 0.00 |
|
||||
| STARTUPE2 | 0 | 0 | 1 | 0.00 |
|
||||
| XADC | 0 | 0 | 1 | 0.00 |
|
||||
+-------------+------+-------+-----------+-------+
|
||||
|
||||
|
||||
7. Primitives
|
||||
-------------
|
||||
|
||||
+----------+------+---------------------+
|
||||
| Ref Name | Used | Functional Category |
|
||||
+----------+------+---------------------+
|
||||
| IBUF | 6 | IO |
|
||||
| OBUF | 1 | IO |
|
||||
| LUT6 | 1 | LUT |
|
||||
+----------+------+---------------------+
|
||||
|
||||
|
||||
8. Black Boxes
|
||||
--------------
|
||||
|
||||
+----------+------+
|
||||
| Ref Name | Used |
|
||||
+----------+------+
|
||||
|
||||
|
||||
9. Instantiated Netlists
|
||||
------------------------
|
||||
|
||||
+----------+------+
|
||||
| Ref Name | Used |
|
||||
+----------+------+
|
||||
|
||||
|
||||
12
Exp1-2-2/Exp1-2-2.runs/synth_1/vivado.jou
Normal file
12
Exp1-2-2/Exp1-2-2.runs/synth_1/vivado.jou
Normal file
@@ -0,0 +1,12 @@
|
||||
#-----------------------------------------------------------
|
||||
# Vivado v2018.1 (64-bit)
|
||||
# SW Build 2188600 on Wed Apr 4 18:40:38 MDT 2018
|
||||
# IP Build 2185939 on Wed Apr 4 20:55:05 MDT 2018
|
||||
# Start of session at: Thu Sep 26 11:15:01 2024
|
||||
# Process ID: 2832
|
||||
# Current directory: F:/Schoolwork/DigitalLogic/Exp1-2-2/Exp1-2-2.runs/synth_1
|
||||
# Command line: vivado.exe -log mux41.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source mux41.tcl
|
||||
# Log file: F:/Schoolwork/DigitalLogic/Exp1-2-2/Exp1-2-2.runs/synth_1/mux41.vds
|
||||
# Journal file: F:/Schoolwork/DigitalLogic/Exp1-2-2/Exp1-2-2.runs/synth_1\vivado.jou
|
||||
#-----------------------------------------------------------
|
||||
source mux41.tcl -notrace
|
||||
BIN
Exp1-2-2/Exp1-2-2.runs/synth_1/vivado.pb
Normal file
BIN
Exp1-2-2/Exp1-2-2.runs/synth_1/vivado.pb
Normal file
Binary file not shown.
Reference in New Issue
Block a user