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2025-11-06 10:08:01 +08:00
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Exp1-2-3/Exp1-2-3.cache/wt/webtalk_pa.xml Normal file
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<?xml version="1.0" encoding="UTF-8" ?>
<document>
<!--The data in this file is primarily intended for consumption by Xilinx tools.
The structure and the elements are likely to change over the next few releases.
This means code written to parse this file will need to be revisited each subsequent release.-->
<application name="pa" timeStamp="Thu Oct 31 21:59:59 2024">
<section name="Project Information" visible="false">
<property name="ProjectID" value="8b7373f0d2104f3486de18a02029c6fe" type="ProjectID"/>
<property name="ProjectIteration" value="1" type="ProjectIteration"/>
</section>
<section name="PlanAhead Usage" visible="true">
<item name="Project Data">
<property name="SrcSetCount" value="1" type="SrcSetCount"/>
<property name="ConstraintSetCount" value="1" type="ConstraintSetCount"/>
<property name="DesignMode" value="RTL" type="DesignMode"/>
<property name="SynthesisStrategy" value="Vivado Synthesis Defaults" type="SynthesisStrategy"/>
<property name="ImplStrategy" value="Vivado Implementation Defaults" type="ImplStrategy"/>
</item>
<item name="Java Command Handlers">
<property name="AddSources" value="3" type="JavaHandler"/>
<property name="CloseDesign" value="1" type="JavaHandler"/>
<property name="CloseProject" value="1" type="JavaHandler"/>
<property name="NewProject" value="1" type="JavaHandler"/>
<property name="OpenDesign" value="1" type="JavaHandler"/>
<property name="RunSchematic" value="1" type="JavaHandler"/>
<property name="SimulationRun" value="4" type="JavaHandler"/>
<property name="ToolsSettings" value="2" type="JavaHandler"/>
<property name="ViewTaskRTLAnalysis" value="4" type="JavaHandler"/>
</item>
<item name="Gui Handlers">
<property name="BaseDialog_APPLY" value="2" type="GuiHandlerData"/>
<property name="BaseDialog_CANCEL" value="2" type="GuiHandlerData"/>
<property name="BaseDialog_OK" value="12" type="GuiHandlerData"/>
<property name="CmdMsgDialog_OK" value="1" type="GuiHandlerData"/>
<property name="CreateSrcFileDialog_FILE_NAME" value="2" type="GuiHandlerData"/>
<property name="FPGAChooser_FPGA_TABLE" value="1" type="GuiHandlerData"/>
<property name="FileSetPanel_FILE_SET_PANEL_TREE" value="49" type="GuiHandlerData"/>
<property name="FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE" value="20" type="GuiHandlerData"/>
<property name="GraphicalView_ZOOM_FIT" value="1" type="GuiHandlerData"/>
<property name="MainMenuMgr_CHECKPOINT" value="2" type="GuiHandlerData"/>
<property name="MainMenuMgr_EDIT" value="4" type="GuiHandlerData"/>
<property name="MainMenuMgr_FILE" value="18" type="GuiHandlerData"/>
<property name="MainMenuMgr_FLOW" value="2" type="GuiHandlerData"/>
<property name="MainMenuMgr_OPEN_RECENT_PROJECT" value="9" type="GuiHandlerData"/>
<property name="MainMenuMgr_PROJECT" value="16" type="GuiHandlerData"/>
<property name="MainMenuMgr_REPORTS" value="4" type="GuiHandlerData"/>
<property name="MainMenuMgr_SIMULATION_WAVEFORM" value="3" type="GuiHandlerData"/>
<property name="MainMenuMgr_TOOLS" value="4" type="GuiHandlerData"/>
<property name="MainMenuMgr_WINDOW" value="4" type="GuiHandlerData"/>
<property name="PACommandNames_AUTO_UPDATE_HIER" value="7" type="GuiHandlerData"/>
<property name="PACommandNames_CLOSE_PROJECT" value="1" type="GuiHandlerData"/>
<property name="PACommandNames_CLOSE_RTL_DESIGN" value="1" type="GuiHandlerData"/>
<property name="PACommandNames_NEW_PROJECT" value="1" type="GuiHandlerData"/>
<property name="PACommandNames_OPEN_RTL_DESIGN" value="1" type="GuiHandlerData"/>
<property name="PACommandNames_SIMULATION_RESET" value="7" type="GuiHandlerData"/>
<property name="PACommandNames_SIMULATION_RESET_BEHAVIORAL" value="1" type="GuiHandlerData"/>
<property name="PACommandNames_SIMULATION_RUN" value="4" type="GuiHandlerData"/>
<property name="PACommandNames_SIMULATION_RUN_BEHAVIORAL" value="3" type="GuiHandlerData"/>
<property name="PACommandNames_SYNTH_SETTINGS" value="1" type="GuiHandlerData"/>
<property name="PAViews_SCHEMATIC" value="1" type="GuiHandlerData"/>
<property name="ProgressDialog_CANCEL" value="1" type="GuiHandlerData"/>
<property name="ProjectNameChooser_PROJECT_NAME" value="1" type="GuiHandlerData"/>
<property name="ProjectTab_RELOAD" value="3" type="GuiHandlerData"/>
<property name="RDICommands_CUSTOM_COMMANDS" value="1" type="GuiHandlerData"/>
<property name="RDICommands_SETTINGS" value="1" type="GuiHandlerData"/>
<property name="SaveProjectUtils_CANCEL" value="1" type="GuiHandlerData"/>
<property name="SettingsDialog_OPTIONS_TREE" value="4" type="GuiHandlerData"/>
<property name="SrcChooserPanel_CREATE_FILE" value="2" type="GuiHandlerData"/>
<property name="SrcMenu_IP_HIERARCHY" value="4" type="GuiHandlerData"/>
<property name="SyntheticaGettingStartedView_RECENT_PROJECTS" value="6" type="GuiHandlerData"/>
<property name="TaskBanner_CLOSE" value="1" type="GuiHandlerData"/>
</item>
<item name="Other">
<property name="GuiMode" value="20" type="GuiMode"/>
<property name="BatchMode" value="0" type="BatchMode"/>
<property name="TclMode" value="11" type="TclMode"/>
</item>
</section>
</application>
</document>

1
Exp1-2-3/Exp1-2-3.ip_user_files/README.txt Normal file
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The files in this directory structure are automatically generated and managed by Vivado. Editing these files is not recommended.

10
Exp1-2-3/Exp1-2-3.sim/sim_1/behav/xsim/LU_sim_vlog.prj Normal file
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# compile verilog/system verilog design source files
verilog xil_defaultlib \
"../../../../Exp1-2-3.srcs/sources_1/new/LU.v" \
"../../../../Exp1-2-3.srcs/sim_1/new/LU_sim.v" \
# compile glbl module
verilog xil_defaultlib "glbl.v"
# Do not sort compile order
nosort

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Exp1-2-3/Exp1-2-3.sim/sim_1/behav/xsim/glbl.v Normal file
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// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (strong1, weak0) GSR = GSR_int;
assign (strong1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif

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Exp1-2-3/Exp1-2-3.sim/sim_1/behav/xsim/sim_LU.tcl Normal file
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set curr_wave [current_wave_config]
if { [string length $curr_wave] == 0 } {
if { [llength [get_objects]] > 0} {
add_wave /
set_property needs_save false [current_wave_config]
} else {
send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
}
}
run 1000ns

10
Exp1-2-3/Exp1-2-3.sim/sim_1/behav/xsim/sim_LU_vlog.prj Normal file
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# compile verilog/system verilog design source files
verilog xil_defaultlib \
"../../../../Exp1-2-3.srcs/sources_1/new/LU.v" \
"../../../../Exp1-2-3.srcs/sim_1/new/LU_sim.v" \
# compile glbl module
verilog xil_defaultlib "glbl.v"
# Do not sort compile order
nosort

12
Exp1-2-3/Exp1-2-3.sim/sim_1/behav/xsim/webtalk.jou Normal file
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#-----------------------------------------------------------
# Webtalk v2018.1 (64-bit)
# SW Build 2188600 on Wed Apr 4 18:40:38 MDT 2018
# IP Build 2185939 on Wed Apr 4 20:55:05 MDT 2018
# Start of session at: Thu Oct 24 00:04:57 2024
# Process ID: 15972
# Current directory: F:/Schoolwork/DigitalLogic/Exp1-2-3/Exp1-2-3.sim/sim_1/behav/xsim
# Command line: wbtcv.exe -mode batch -source F:/Schoolwork/DigitalLogic/Exp1-2-3/Exp1-2-3.sim/sim_1/behav/xsim/xsim.dir/sim_LU_behav/webtalk/xsim_webtalk.tcl -notrace
# Log file: F:/Schoolwork/DigitalLogic/Exp1-2-3/Exp1-2-3.sim/sim_1/behav/xsim/webtalk.log
# Journal file: F:/Schoolwork/DigitalLogic/Exp1-2-3/Exp1-2-3.sim/sim_1/behav/xsim\webtalk.jou
#-----------------------------------------------------------
source F:/Schoolwork/DigitalLogic/Exp1-2-3/Exp1-2-3.sim/sim_1/behav/xsim/xsim.dir/sim_LU_behav/webtalk/xsim_webtalk.tcl -notrace

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Exp1-2-3/Exp1-2-3.sim/sim_1/behav/xsim/webtalk_18216.backup.jou Normal file
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#-----------------------------------------------------------
# Webtalk v2018.1 (64-bit)
# SW Build 2188600 on Wed Apr 4 18:40:38 MDT 2018
# IP Build 2185939 on Wed Apr 4 20:55:05 MDT 2018
# Start of session at: Thu Oct 24 00:03:53 2024
# Process ID: 18216
# Current directory: F:/Schoolwork/DigitalLogic/Exp1-2-3/Exp1-2-3.sim/sim_1/behav/xsim
# Command line: wbtcv.exe -mode batch -source F:/Schoolwork/DigitalLogic/Exp1-2-3/Exp1-2-3.sim/sim_1/behav/xsim/xsim.dir/sim_LU_behav/webtalk/xsim_webtalk.tcl -notrace
# Log file: F:/Schoolwork/DigitalLogic/Exp1-2-3/Exp1-2-3.sim/sim_1/behav/xsim/webtalk.log
# Journal file: F:/Schoolwork/DigitalLogic/Exp1-2-3/Exp1-2-3.sim/sim_1/behav/xsim\webtalk.jou
#-----------------------------------------------------------
source F:/Schoolwork/DigitalLogic/Exp1-2-3/Exp1-2-3.sim/sim_1/behav/xsim/xsim.dir/sim_LU_behav/webtalk/xsim_webtalk.tcl -notrace

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Exp1-2-3/Exp1-2-3.sim/sim_1/behav/xsim/xelab.pb Normal file
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1
Exp1-2-3/Exp1-2-3.sim/sim_1/behav/xsim/xsim.dir/sim_LU_behav/Compile_Options.txt Normal file
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-wto "530f3e30324548dd8d8037ace6e40f69" --incr --debug "typical" --relax --mt "2" -L "xil_defaultlib" -L "unisims_ver" -L "unimacro_ver" -L "secureip" --snapshot "sim_LU_behav" "xil_defaultlib.sim_LU" "xil_defaultlib.glbl" -log "elaborate.log"

1
Exp1-2-3/Exp1-2-3.sim/sim_1/behav/xsim/xsim.dir/sim_LU_behav/TempBreakPointFile.txt Normal file
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Breakpoint File Version 1.0

109
Exp1-2-3/Exp1-2-3.sim/sim_1/behav/xsim/xsim.dir/sim_LU_behav/obj/xsim_1.c Normal file
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/**********************************************************************/
/* ____ ____ */
/* / /\/ / */
/* /___/ \ / */
/* \ \ \/ */
/* \ \ Copyright (c) 2003-2013 Xilinx, Inc. */
/* / / All Right Reserved. */
/* /---/ /\ */
/* \ \ / \ */
/* \___\/\___\ */
/**********************************************************************/
#include "iki.h"
#include <string.h>
#include <math.h>
#ifdef __GNUC__
#include <stdlib.h>
#else
#include <malloc.h>
#define alloca _alloca
#endif
/**********************************************************************/
/* ____ ____ */
/* / /\/ / */
/* /___/ \ / */
/* \ \ \/ */
/* \ \ Copyright (c) 2003-2013 Xilinx, Inc. */
/* / / All Right Reserved. */
/* /---/ /\ */
/* \ \ / \ */
/* \___\/\___\ */
/**********************************************************************/
#include "iki.h"
#include <string.h>
#include <math.h>
#ifdef __GNUC__
#include <stdlib.h>
#else
#include <malloc.h>
#define alloca _alloca
#endif
typedef void (*funcp)(char *, char *);
extern int main(int, char**);
extern void execute_4(char*, char *);
extern void execute_9(char*, char *);
extern void execute_10(char*, char *);
extern void execute_11(char*, char *);
extern void execute_12(char*, char *);
extern void execute_3(char*, char *);
extern void execute_6(char*, char *);
extern void execute_7(char*, char *);
extern void execute_8(char*, char *);
extern void execute_13(char*, char *);
extern void execute_14(char*, char *);
extern void execute_15(char*, char *);
extern void execute_16(char*, char *);
extern void execute_17(char*, char *);
extern void vlog_transfunc_eventcallback(char*, char*, unsigned, unsigned, unsigned, char *);
funcp funcTab[15] = {(funcp)execute_4, (funcp)execute_9, (funcp)execute_10, (funcp)execute_11, (funcp)execute_12, (funcp)execute_3, (funcp)execute_6, (funcp)execute_7, (funcp)execute_8, (funcp)execute_13, (funcp)execute_14, (funcp)execute_15, (funcp)execute_16, (funcp)execute_17, (funcp)vlog_transfunc_eventcallback};
const int NumRelocateId= 15;
void relocate(char *dp)
{
iki_relocate(dp, "xsim.dir/sim_LU_behav/xsim.reloc", (void **)funcTab, 15);
/*Populate the transaction function pointer field in the whole net structure */
}
void sensitize(char *dp)
{
iki_sensitize(dp, "xsim.dir/sim_LU_behav/xsim.reloc");
}
void simulate(char *dp)
{
iki_schedule_processes_at_time_zero(dp, "xsim.dir/sim_LU_behav/xsim.reloc");
// Initialize Verilog nets in mixed simulation, for the cases when the value at time 0 should be propagated from the mixed language Vhdl net
iki_execute_processes();
// Schedule resolution functions for the multiply driven Verilog nets that have strength
// Schedule transaction functions for the singly driven Verilog nets that have strength
}
#include "iki_bridge.h"
void relocate(char *);
void sensitize(char *);
void simulate(char *);
extern SYSTEMCLIB_IMP_DLLSPEC void local_register_implicit_channel(int, char*);
extern void implicit_HDL_SCinstatiate();
extern int xsim_argc_copy ;
extern char** xsim_argv_copy ;
int main(int argc, char **argv)
{
iki_heap_initialize("ms", "isimmm", 0, 2147483648) ;
iki_set_sv_type_file_path_name("xsim.dir/sim_LU_behav/xsim.svtype");
iki_set_crvs_dump_file_path_name("xsim.dir/sim_LU_behav/xsim.crvsdump");
void* design_handle = iki_create_design("xsim.dir/sim_LU_behav/xsim.mem", (void *)relocate, (void *)sensitize, (void *)simulate, 0, isimBridge_getWdbWriter(), 0, argc, argv);
iki_set_rc_trial_count(100);
(void) design_handle;
return iki_simulate_design();
}

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Exp1-2-3/Exp1-2-3.sim/sim_1/behav/xsim/xsim.dir/sim_LU_behav/webtalk/xsim_webtalk.tcl Normal file
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webtalk_init -webtalk_dir F:/Schoolwork/DigitalLogic/Exp1-2-3/Exp1-2-3.sim/sim_1/behav/xsim/xsim.dir/sim_LU_behav/webtalk/
webtalk_register_client -client project
webtalk_add_data -client project -key date_generated -value "Thu Oct 24 00:16:14 2024" -context "software_version_and_target_device"
webtalk_add_data -client project -key product_version -value "XSIM v2018.1 (64-bit)" -context "software_version_and_target_device"
webtalk_add_data -client project -key build_version -value "2188600" -context "software_version_and_target_device"
webtalk_add_data -client project -key os_platform -value "WIN64" -context "software_version_and_target_device"
webtalk_add_data -client project -key registration_id -value "" -context "software_version_and_target_device"
webtalk_add_data -client project -key tool_flow -value "xsim_vivado" -context "software_version_and_target_device"
webtalk_add_data -client project -key beta -value "FALSE" -context "software_version_and_target_device"
webtalk_add_data -client project -key route_design -value "FALSE" -context "software_version_and_target_device"
webtalk_add_data -client project -key target_family -value "not_applicable" -context "software_version_and_target_device"
webtalk_add_data -client project -key target_device -value "not_applicable" -context "software_version_and_target_device"
webtalk_add_data -client project -key target_package -value "not_applicable" -context "software_version_and_target_device"
webtalk_add_data -client project -key target_speed -value "not_applicable" -context "software_version_and_target_device"
webtalk_add_data -client project -key random_id -value "78ec1a93-fd1a-4b14-8c4b-87f04256706b" -context "software_version_and_target_device"
webtalk_add_data -client project -key project_id -value "530f3e30324548dd8d8037ace6e40f69" -context "software_version_and_target_device"
webtalk_add_data -client project -key project_iteration -value "4" -context "software_version_and_target_device"
webtalk_add_data -client project -key os_name -value "Microsoft Windows 8 or later , 64-bit" -context "user_environment"
webtalk_add_data -client project -key os_release -value "major release (build 9200)" -context "user_environment"
webtalk_add_data -client project -key cpu_name -value "13th Gen Intel(R) Core(TM) i7-13700H" -context "user_environment"
webtalk_add_data -client project -key cpu_speed -value "2918 MHz" -context "user_environment"
webtalk_add_data -client project -key total_processors -value "1" -context "user_environment"
webtalk_add_data -client project -key system_ram -value "16.000 GB" -context "user_environment"
webtalk_register_client -client xsim
webtalk_add_data -client xsim -key Command -value "xsim" -context "xsim\\command_line_options"
webtalk_add_data -client xsim -key trace_waveform -value "true" -context "xsim\\usage"
webtalk_add_data -client xsim -key runtime -value "1 us" -context "xsim\\usage"
webtalk_add_data -client xsim -key iteration -value "0" -context "xsim\\usage"
webtalk_add_data -client xsim -key Simulation_Time -value "0.00_sec" -context "xsim\\usage"
webtalk_add_data -client xsim -key Simulation_Memory -value "8508_KB" -context "xsim\\usage"
webtalk_transmit -clientid 2261735523 -regid "" -xml F:/Schoolwork/DigitalLogic/Exp1-2-3/Exp1-2-3.sim/sim_1/behav/xsim/xsim.dir/sim_LU_behav/webtalk/usage_statistics_ext_xsim.xml -html F:/Schoolwork/DigitalLogic/Exp1-2-3/Exp1-2-3.sim/sim_1/behav/xsim/xsim.dir/sim_LU_behav/webtalk/usage_statistics_ext_xsim.html -wdm F:/Schoolwork/DigitalLogic/Exp1-2-3/Exp1-2-3.sim/sim_1/behav/xsim/xsim.dir/sim_LU_behav/webtalk/usage_statistics_ext_xsim.wdm -intro "<H3>XSIM Usage Report</H3><BR>"
webtalk_terminate

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Exp1-2-3/Exp1-2-3.srcs/sim_1/new/LU_sim.v Normal file
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`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2024/09/26 10:31:31
// Design Name:
// Module Name: LU_sim
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module sim_LU();
reg a,b;
reg [1:0]s;
LU u3(.a(a),.b(b),.s(s),.Y(Y));
initial begin
a=0;b=0;s=2'b00;#50;
a=0;b=0;s=2'b01;#50;
a=0;b=0;s=2'b10;#50;
a=0;b=0;s=2'b11;#50;
a=0;b=1;s=2'b00;#50;
a=0;b=1;s=2'b01;#50;
a=0;b=1;s=2'b10;#50;
a=0;b=1;s=2'b11;#50;
a=1;b=0;s=2'b00;#50;
a=1;b=0;s=2'b01;#50;
a=1;b=0;s=2'b10;#50;
a=1;b=0;s=2'b11;#50;
a=1;b=1;s=2'b00;#50;
a=1;b=1;s=2'b01;#50;
a=1;b=1;s=2'b10;#50;
a=1;b=1;s=2'b11;#50;
end
endmodule

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Exp1-2-3/Exp1-2-3.srcs/sources_1/new/LU.v Normal file
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`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2024/09/25 20:04:39
// Design Name:
// Module Name: LU
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module LU(a, b, s, Y);
input a, b;
input [1:0] s;
output Y;
reg Y;
always @(*) begin
case (s)
2'b00: Y = a & b;
2'b01: Y = a | b;
2'b10: Y = a ^ b;
2'b11: Y = 0;
default: Y = 0;
endcase
end
endmodule

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<?xml version="1.0" encoding="UTF-8"?>
<!-- Product Version: Vivado v2018.1 (64-bit) -->
<!-- -->
<!-- Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. -->
<Project Version="7" Minor="36" Path="F:/Schoolwork/DigitalLogic/Exp1-2-3/Exp1-2-3.xpr">
<DefaultLaunch Dir="$PRUNDIR"/>
<Configuration>
<Option Name="Id" Val="530f3e30324548dd8d8037ace6e40f69"/>
<Option Name="Part" Val="xc7a35tcsg324-1"/>
<Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
<Option Name="CompiledLibDirXSim" Val=""/>
<Option Name="CompiledLibDirModelSim" Val="$PCACHEDIR/compile_simlib/modelsim"/>
<Option Name="CompiledLibDirQuesta" Val="$PCACHEDIR/compile_simlib/questa"/>
<Option Name="CompiledLibDirIES" Val="$PCACHEDIR/compile_simlib/ies"/>
<Option Name="CompiledLibDirXcelium" Val="$PCACHEDIR/compile_simlib/xcelium"/>
<Option Name="CompiledLibDirVCS" Val="$PCACHEDIR/compile_simlib/vcs"/>
<Option Name="CompiledLibDirRiviera" Val="$PCACHEDIR/compile_simlib/riviera"/>
<Option Name="CompiledLibDirActivehdl" Val="$PCACHEDIR/compile_simlib/activehdl"/>
<Option Name="BoardPart" Val=""/>
<Option Name="ActiveSimSet" Val="sim_1"/>
<Option Name="DefaultLib" Val="xil_defaultlib"/>
<Option Name="ProjectType" Val="Default"/>
<Option Name="IPOutputRepo" Val="$PCACHEDIR/ip"/>
<Option Name="IPCachePermission" Val="read"/>
<Option Name="IPCachePermission" Val="write"/>
<Option Name="EnableCoreContainer" Val="FALSE"/>
<Option Name="CreateRefXciForCoreContainers" Val="FALSE"/>
<Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
<Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
<Option Name="EnableBDX" Val="FALSE"/>
<Option Name="DSAVendor" Val="xilinx"/>
<Option Name="DSANumComputeUnits" Val="60"/>
<Option Name="WTXSimLaunchSim" Val="3"/>
<Option Name="WTModelSimLaunchSim" Val="0"/>
<Option Name="WTQuestaLaunchSim" Val="0"/>
<Option Name="WTIesLaunchSim" Val="0"/>
<Option Name="WTVcsLaunchSim" Val="0"/>
<Option Name="WTRivieraLaunchSim" Val="0"/>
<Option Name="WTActivehdlLaunchSim" Val="0"/>
<Option Name="WTXSimExportSim" Val="0"/>
<Option Name="WTModelSimExportSim" Val="0"/>
<Option Name="WTQuestaExportSim" Val="0"/>
<Option Name="WTIesExportSim" Val="0"/>
<Option Name="WTVcsExportSim" Val="0"/>
<Option Name="WTRivieraExportSim" Val="0"/>
<Option Name="WTActivehdlExportSim" Val="0"/>
<Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
<Option Name="XSimRadix" Val="hex"/>
<Option Name="XSimTimeUnit" Val="ns"/>
<Option Name="XSimArrayDisplayLimit" Val="1024"/>
<Option Name="XSimTraceLimit" Val="65536"/>
<Option Name="SimTypes" Val="rtl"/>
</Configuration>
<FileSets Version="1" Minor="31">
<FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1">
<Filter Type="Srcs"/>
<File Path="$PSRCDIR/sources_1/new/LU.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<Config>
<Option Name="DesignMode" Val="RTL"/>
<Option Name="TopModule" Val="LU"/>
<Option Name="TopAutoSet" Val="TRUE"/>
</Config>
</FileSet>
<FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1">
<Filter Type="Constrs"/>
<Config>
<Option Name="ConstrsType" Val="XDC"/>
</Config>
</FileSet>
<FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1">
<Filter Type="Srcs"/>
<File Path="$PSRCDIR/sim_1/new/LU_sim.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<Config>
<Option Name="DesignMode" Val="RTL"/>
<Option Name="TopModule" Val="sim_LU"/>
<Option Name="TopLib" Val="xil_defaultlib"/>
<Option Name="TopAutoSet" Val="TRUE"/>
<Option Name="TransportPathDelay" Val="0"/>
<Option Name="TransportIntDelay" Val="0"/>
<Option Name="SrcSet" Val="sources_1"/>
</Config>
</FileSet>
</FileSets>
<Simulators>
<Simulator Name="XSim">
<Option Name="Description" Val="Vivado Simulator"/>
<Option Name="CompiledLib" Val="0"/>
</Simulator>
<Simulator Name="ModelSim">
<Option Name="Description" Val="ModelSim Simulator"/>
</Simulator>
<Simulator Name="Questa">
<Option Name="Description" Val="Questa Advanced Simulator"/>
</Simulator>
<Simulator Name="Riviera">
<Option Name="Description" Val="Riviera-PRO Simulator"/>
</Simulator>
<Simulator Name="ActiveHDL">
<Option Name="Description" Val="Active-HDL Simulator"/>
</Simulator>
</Simulators>
<Runs Version="1" Minor="10">
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a35tcsg324-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2018"/>
<Step Id="synth_design"/>
</Strategy>
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2018"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
</Run>
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcsg324-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2018"/>
<Step Id="init_design"/>
<Step Id="opt_design"/>
<Step Id="power_opt_design"/>
<Step Id="place_design"/>
<Step Id="post_place_power_opt_design"/>
<Step Id="phys_opt_design"/>
<Step Id="route_design"/>
<Step Id="post_route_phys_opt_design"/>
<Step Id="write_bitstream"/>
</Strategy>
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2018"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
</Run>
</Runs>
<Board/>
</Project>