Initial commit

Exp1-2-3/Exp1-2-3.srcs/sim_1/new/LU_sim.v

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+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date: 2024/09/26 10:31:31
+// Design Name: 
+// Module Name: LU_sim
+// Project Name: 
+// Target Devices: 
+// Tool Versions: 
+// Description: 
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module sim_LU();
+reg a,b;
+reg [1:0]s;
+LU u3(.a(a),.b(b),.s(s),.Y(Y));
+initial begin
+    a=0;b=0;s=2'b00;#50;
+    a=0;b=0;s=2'b01;#50;
+    a=0;b=0;s=2'b10;#50;
+    a=0;b=0;s=2'b11;#50;
+    a=0;b=1;s=2'b00;#50;
+    a=0;b=1;s=2'b01;#50;
+    a=0;b=1;s=2'b10;#50;
+    a=0;b=1;s=2'b11;#50;
+    a=1;b=0;s=2'b00;#50;
+    a=1;b=0;s=2'b01;#50;
+    a=1;b=0;s=2'b10;#50;
+    a=1;b=0;s=2'b11;#50;
+    a=1;b=1;s=2'b00;#50;
+    a=1;b=1;s=2'b01;#50;
+    a=1;b=1;s=2'b10;#50;
+    a=1;b=1;s=2'b11;#50;
+    end
+endmodule

Exp1-2-3/Exp1-2-3.srcs/sources_1/new/LU.v

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+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date: 2024/09/25 20:04:39
+// Design Name: 
+// Module Name: LU
+// Project Name: 
+// Target Devices: 
+// Tool Versions: 
+// Description: 
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module LU(a, b, s, Y);
+input a, b;
+input [1:0] s;
+output Y;
+reg Y;
+always @(*) begin
+    case (s)
+        2'b00: Y = a & b;
+        2'b01: Y = a | b;
+        2'b10: Y = a ^ b;
+        2'b11: Y = 0;
+        default: Y = 0;
+    endcase
+end
+endmodule