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`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2024/10/30 23:15:29
// Design Name:
// Module Name: SegDisplayCtrl
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module SegDisplayCtrl(
input wire [2:0] Y,
input wire out,
output reg [6:0] seg1,
output reg [7:0] seg2
);
always @(*) begin
case (Y)
3'b000: seg1 = 7'b1111110; // 0
3'b001: seg1 = 7'b0110000; // 1
3'b010: seg1 = 7'b1101101; // 2
3'b011: seg1 = 7'b1111001; // 3
3'b100: seg1 = 7'b0110011; // 4
3'b101: seg1 = 7'b1011011; // 5
3'b110: seg1 = 7'b1011111; // 6
3'b111: seg1 = 7'b1110000; // 7
default: seg1 = 7'b0000000;
endcase
if (out)
seg2 = 8'b00000001;
else
seg2 = 8'b10011110;
end
endmodule