launchcore/DigitalLogic
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

Initial commit

Browse Source
This commit is contained in:
綾瀬桃桃
2025-11-06 10:08:01 +08:00
commit 0bded5b86e
1033 changed files with 55966 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

97
Exp4/Exp4.cache/wt/webtalk_pa.xml Normal file
View File

@@ -0,0 +1,97 @@
<?xml version="1.0" encoding="UTF-8" ?>
<document>
<!--The data in this file is primarily intended for consumption by Xilinx tools.
The structure and the elements are likely to change over the next few releases.
This means code written to parse this file will need to be revisited each subsequent release.-->
<application name="pa" timeStamp="Thu Dec 5 10:16:09 2024">
<section name="Project Information" visible="false">
<property name="ProjectID" value="fb54b501f285483d86097c07db688697" type="ProjectID"/>
<property name="ProjectIteration" value="6" type="ProjectIteration"/>
</section>
<section name="PlanAhead Usage" visible="true">
<item name="Project Data">
<property name="SrcSetCount" value="1" type="SrcSetCount"/>
<property name="ConstraintSetCount" value="1" type="ConstraintSetCount"/>
<property name="DesignMode" value="RTL" type="DesignMode"/>
<property name="SynthesisStrategy" value="Vivado Synthesis Defaults" type="SynthesisStrategy"/>
<property name="ImplStrategy" value="Vivado Implementation Defaults" type="ImplStrategy"/>
</item>
<item name="Java Command Handlers">
<property name="AddSources" value="5" type="JavaHandler"/>
<property name="AddXvcTarget" value="1" type="JavaHandler"/>
<property name="AutoConnectTarget" value="7" type="JavaHandler"/>
<property name="CloseServer" value="2" type="JavaHandler"/>
<property name="CloseTarget" value="2" type="JavaHandler"/>
<property name="EditCopy" value="1" type="JavaHandler"/>
<property name="EditDelete" value="1" type="JavaHandler"/>
<property name="HelpAbout" value="1" type="JavaHandler"/>
<property name="LaunchProgramFpga" value="6" type="JavaHandler"/>
<property name="NewProject" value="1" type="JavaHandler"/>
<property name="OpenHardwareManager" value="6" type="JavaHandler"/>
<property name="OpenRecentTarget" value="1" type="JavaHandler"/>
<property name="OpenTarget" value="2" type="JavaHandler"/>
<property name="RefreshServer" value="1" type="JavaHandler"/>
<property name="RunBitgen" value="6" type="JavaHandler"/>
<property name="RunImplementation" value="2" type="JavaHandler"/>
<property name="RunSynthesis" value="5" type="JavaHandler"/>
<property name="SaveDesign" value="2" type="JavaHandler"/>
<property name="SaveFileProxyHandler" value="1" type="JavaHandler"/>
<property name="ShowView" value="1" type="JavaHandler"/>
<property name="SimulationRun" value="1" type="JavaHandler"/>
<property name="ViewTaskRTLAnalysis" value="1" type="JavaHandler"/>
<property name="ViewTaskSynthesis" value="2" type="JavaHandler"/>
</item>
<item name="Gui Handlers">
<property name="AddSrcWizard_SPECIFY_SIMULATION_SPECIFIC_HDL_FILES" value="1" type="GuiHandlerData"/>
<property name="BaseDialog_CANCEL" value="3" type="GuiHandlerData"/>
<property name="BaseDialog_OK" value="34" type="GuiHandlerData"/>
<property name="BaseDialog_YES" value="2" type="GuiHandlerData"/>
<property name="CreateConstraintsFilePanel_FILE_NAME" value="1" type="GuiHandlerData"/>
<property name="CreateSrcFileDialog_FILE_NAME" value="6" type="GuiHandlerData"/>
<property name="FPGAChooser_FPGA_TABLE" value="1" type="GuiHandlerData"/>
<property name="FileSetPanel_FILE_SET_PANEL_TREE" value="48" type="GuiHandlerData"/>
<property name="FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE" value="21" type="GuiHandlerData"/>
<property name="GettingStartedView_CREATE_NEW_PROJECT" value="1" type="GuiHandlerData"/>
<property name="GraphicalView_ZOOM_FIT" value="1" type="GuiHandlerData"/>
<property name="HardwareTreePanel_HARDWARE_TREE_TABLE" value="32" type="GuiHandlerData"/>
<property name="LabtoolsMenu_JTAG_SCAN_RATE" value="1" type="GuiHandlerData"/>
<property name="MainMenuMgr_HELP" value="2" type="GuiHandlerData"/>
<property name="MessageWithOptionDialog_DONT_SHOW_THIS_DIALOG_AGAIN" value="1" type="GuiHandlerData"/>
<property name="MsgTreePanel_MESSAGE_VIEW_TREE" value="1" type="GuiHandlerData"/>
<property name="PACommandNames_ABOUT" value="1" type="GuiHandlerData"/>
<property name="PACommandNames_ADD_SOURCES" value="3" type="GuiHandlerData"/>
<property name="PACommandNames_ADD_XVC_TARGET" value="1" type="GuiHandlerData"/>
<property name="PACommandNames_AUTO_CONNECT_TARGET" value="7" type="GuiHandlerData"/>
<property name="PACommandNames_AUTO_UPDATE_HIER" value="3" type="GuiHandlerData"/>
<property name="PACommandNames_CLOSE_SERVER" value="2" type="GuiHandlerData"/>
<property name="PACommandNames_CLOSE_TARGET" value="2" type="GuiHandlerData"/>
<property name="PACommandNames_GOTO_NETLIST_DESIGN" value="2" type="GuiHandlerData"/>
<property name="PACommandNames_OPEN_HARDWARE_MANAGER" value="2" type="GuiHandlerData"/>
<property name="PACommandNames_OPEN_TARGET" value="2" type="GuiHandlerData"/>
<property name="PACommandNames_PROGRAM_FPGA" value="2" type="GuiHandlerData"/>
<property name="PACommandNames_REFRESH_SERVER" value="1" type="GuiHandlerData"/>
<property name="PACommandNames_RUN_BITGEN" value="2" type="GuiHandlerData"/>
<property name="PACommandNames_SIMULATION_RUN_BEHAVIORAL" value="1" type="GuiHandlerData"/>
<property name="PACommandNames_WRITE_CONFIG_MEMORY_FILE" value="1" type="GuiHandlerData"/>
<property name="ProgramDebugTab_OPEN_TARGET" value="6" type="GuiHandlerData"/>
<property name="ProgramDebugTab_PROGRAM_DEVICE" value="4" type="GuiHandlerData"/>
<property name="ProgramFpgaDialog_PROGRAM" value="6" type="GuiHandlerData"/>
<property name="ProjectNameChooser_PROJECT_NAME" value="1" type="GuiHandlerData"/>
<property name="RDICommands_COPY" value="1" type="GuiHandlerData"/>
<property name="RDICommands_DELETE" value="1" type="GuiHandlerData"/>
<property name="RemoveSourcesDialog_ALSO_DELETE" value="1" type="GuiHandlerData"/>
<property name="SaveProjectUtils_CANCEL" value="1" type="GuiHandlerData"/>
<property name="SignalTreePanel_SIGNAL_TREE_TABLE" value="32" type="GuiHandlerData"/>
<property name="SrcChooserPanel_CREATE_FILE" value="5" type="GuiHandlerData"/>
<property name="SyntheticaGettingStartedView_RECENT_PROJECTS" value="2" type="GuiHandlerData"/>
<property name="TaskBanner_CLOSE" value="2" type="GuiHandlerData"/>
<property name="WaveformNameTree_WAVEFORM_NAME_TREE" value="4" type="GuiHandlerData"/>
</item>
<item name="Other">
<property name="GuiMode" value="37" type="GuiMode"/>
<property name="BatchMode" value="0" type="BatchMode"/>
<property name="TclMode" value="23" type="TclMode"/>
</item>
</section>
</application>
</document>

17
Exp4/Exp4.hw/hw_1/hw.xml Normal file
View File

@@ -0,0 +1,17 @@
<?xml version="1.0" encoding="UTF-8"?>
<!-- Product Version: Vivado v2018.1 (64-bit) -->
<!-- -->
<!-- Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. -->
<hwsession version="1" minor="2">
<device name="xc7a35t_0" gui_info=""/>
<ObjectList object_type="hw_device" gui_info="">
<Object name="xc7a35t_0" gui_info="">
<Properties Property="FULL_PROBES.FILE" value=""/>
<Properties Property="PROBES.FILE" value=""/>
<Properties Property="PROGRAM.HW_BITSTREAM" value="$_project_name_.runs/impl_1/calc.bit"/>
<Properties Property="SLR.COUNT" value="1"/>
</Object>
</ObjectList>
<probeset name="hw project" active="false"/>
</hwsession>

1
Exp4/Exp4.ip_user_files/README.txt Normal file
View File

@@ -0,0 +1 @@
The files in this directory structure are automatically generated and managed by Vivado. Editing these files is not recommended.

5
Exp4/Exp4.runs/.jobs/vrs_config_1.xml Normal file
View File

@@ -0,0 +1,5 @@
<?xml version="1.0"?>
<Runs Version="1" Minor="0">
<Run Id="synth_1" LaunchDir="F:/Schoolwork/DigitalLogic/Exp4/Exp4.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
</Runs>

5
Exp4/Exp4.runs/.jobs/vrs_config_2.xml Normal file
View File

@@ -0,0 +1,5 @@
<?xml version="1.0"?>
<Runs Version="1" Minor="0">
<Run Id="synth_1" LaunchDir="F:/Schoolwork/DigitalLogic/Exp4/Exp4.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
</Runs>

8
Exp4/Exp4.runs/.jobs/vrs_config_3.xml Normal file
View File

@@ -0,0 +1,8 @@
<?xml version="1.0"?>
<Runs Version="1" Minor="0">
<Run Id="synth_1" LaunchDir="F:/Schoolwork/DigitalLogic/Exp4/Exp4.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
<Run Id="impl_1" LaunchDir="F:/Schoolwork/DigitalLogic/Exp4/Exp4.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="init_design" ToStepId="route_design">
<Parent Id="synth_1"/>
</Run>
</Runs>

5
Exp4/Exp4.runs/.jobs/vrs_config_4.xml Normal file
View File

@@ -0,0 +1,5 @@
<?xml version="1.0"?>
<Runs Version="1" Minor="0">
<Run Id="impl_1" LaunchDir="F:/Schoolwork/DigitalLogic/Exp4/Exp4.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="write_bitstream" ToStepId="write_bitstream"/>
</Runs>

5
Exp4/Exp4.runs/.jobs/vrs_config_5.xml Normal file
View File

@@ -0,0 +1,5 @@
<?xml version="1.0"?>
<Runs Version="1" Minor="0">
<Run Id="synth_1" LaunchDir="F:/Schoolwork/DigitalLogic/Exp4/Exp4.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
</Runs>

5
Exp4/Exp4.runs/.jobs/vrs_config_6.xml Normal file
View File

@@ -0,0 +1,5 @@
<?xml version="1.0"?>
<Runs Version="1" Minor="0">
<Run Id="impl_1" LaunchDir="F:/Schoolwork/DigitalLogic/Exp4/Exp4.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="init_design" ToStepId="route_design"/>
</Runs>

5
Exp4/Exp4.runs/.jobs/vrs_config_7.xml Normal file
View File

@@ -0,0 +1,5 @@
<?xml version="1.0"?>
<Runs Version="1" Minor="0">
<Run Id="impl_1" LaunchDir="F:/Schoolwork/DigitalLogic/Exp4/Exp4.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="write_bitstream" ToStepId="write_bitstream"/>
</Runs>

8
Exp4/Exp4.runs/.jobs/vrs_config_8.xml Normal file
View File

@@ -0,0 +1,8 @@
<?xml version="1.0"?>
<Runs Version="1" Minor="0">
<Run Id="synth_1" LaunchDir="F:/Schoolwork/DigitalLogic/Exp4/Exp4.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
<Run Id="impl_1" LaunchDir="F:/Schoolwork/DigitalLogic/Exp4/Exp4.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="init_design" ToStepId="write_bitstream">
<Parent Id="synth_1"/>
</Run>
</Runs>

170
Exp4/Exp4.runs/impl_1/calc.tcl Normal file
View File

@@ -0,0 +1,170 @@
#
# Report generation script generated by Vivado
#
proc create_report { reportName command } {
set status "."
append status $reportName ".fail"
if { [file exists $status] } {
eval file delete [glob $status]
}
send_msg_id runtcl-4 info "Executing : $command"
set retval [eval catch { $command } msg]
if { $retval != 0 } {
set fp [open $status w]
close $fp
send_msg_id runtcl-5 warning "$msg"
}
}
proc start_step { step } {
set stopFile ".stop.rst"
if {[file isfile .stop.rst]} {
puts ""
puts "*** Halting run - EA reset detected ***"
puts ""
puts ""
return -code error
}
set beginFile ".$step.begin.rst"
set platform "$::tcl_platform(platform)"
set user "$::tcl_platform(user)"
set pid [pid]
set host ""
if { [string equal $platform unix] } {
if { [info exist ::env(HOSTNAME)] } {
set host $::env(HOSTNAME)
}
} else {
if { [info exist ::env(COMPUTERNAME)] } {
set host $::env(COMPUTERNAME)
}
}
set ch [open $beginFile w]
puts $ch "<?xml version=\"1.0\"?>"
puts $ch "<ProcessHandle Version=\"1\" Minor=\"0\">"
puts $ch " <Process Command=\".planAhead.\" Owner=\"$user\" Host=\"$host\" Pid=\"$pid\">"
puts $ch " </Process>"
puts $ch "</ProcessHandle>"
close $ch
}
proc end_step { step } {
set endFile ".$step.end.rst"
set ch [open $endFile w]
close $ch
}
proc step_failed { step } {
set endFile ".$step.error.rst"
set ch [open $endFile w]
close $ch
}
start_step init_design
set ACTIVE_STEP init_design
set rc [catch {
create_msg_db init_design.pb
set_param xicom.use_bs_reader 1
create_project -in_memory -part xc7a35tcsg324-1
set_property design_mode GateLvl [current_fileset]
set_param project.singleFileAddWarning.threshold 0
set_property webtalk.parent_dir F:/Schoolwork/DigitalLogic/Exp4/Exp4.cache/wt [current_project]
set_property parent.project_path F:/Schoolwork/DigitalLogic/Exp4/Exp4.xpr [current_project]
set_property ip_output_repo F:/Schoolwork/DigitalLogic/Exp4/Exp4.cache/ip [current_project]
set_property ip_cache_permissions {read write} [current_project]
add_files -quiet F:/Schoolwork/DigitalLogic/Exp4/Exp4.runs/synth_1/calc.dcp
read_xdc F:/Schoolwork/DigitalLogic/Exp4/Exp4.srcs/constrs_1/new/calc.xdc
link_design -top calc -part xc7a35tcsg324-1
close_msg_db -file init_design.pb
} RESULT]
if {$rc} {
step_failed init_design
return -code error $RESULT
} else {
end_step init_design
unset ACTIVE_STEP
}
start_step opt_design
set ACTIVE_STEP opt_design
set rc [catch {
create_msg_db opt_design.pb
opt_design
write_checkpoint -force calc_opt.dcp
create_report "impl_1_opt_report_drc_0" "report_drc -file calc_drc_opted.rpt -pb calc_drc_opted.pb -rpx calc_drc_opted.rpx"
close_msg_db -file opt_design.pb
} RESULT]
if {$rc} {
step_failed opt_design
return -code error $RESULT
} else {
end_step opt_design
unset ACTIVE_STEP
}
start_step place_design
set ACTIVE_STEP place_design
set rc [catch {
create_msg_db place_design.pb
if { [llength [get_debug_cores -quiet] ] > 0 } {
implement_debug_core
}
place_design
write_checkpoint -force calc_placed.dcp
create_report "impl_1_place_report_io_0" "report_io -file calc_io_placed.rpt"
create_report "impl_1_place_report_utilization_0" "report_utilization -file calc_utilization_placed.rpt -pb calc_utilization_placed.pb"
create_report "impl_1_place_report_control_sets_0" "report_control_sets -verbose -file calc_control_sets_placed.rpt"
close_msg_db -file place_design.pb
} RESULT]
if {$rc} {
step_failed place_design
return -code error $RESULT
} else {
end_step place_design
unset ACTIVE_STEP
}
start_step route_design
set ACTIVE_STEP route_design
set rc [catch {
create_msg_db route_design.pb
route_design
write_checkpoint -force calc_routed.dcp
create_report "impl_1_route_report_drc_0" "report_drc -file calc_drc_routed.rpt -pb calc_drc_routed.pb -rpx calc_drc_routed.rpx"
create_report "impl_1_route_report_methodology_0" "report_methodology -file calc_methodology_drc_routed.rpt -pb calc_methodology_drc_routed.pb -rpx calc_methodology_drc_routed.rpx"
create_report "impl_1_route_report_power_0" "report_power -file calc_power_routed.rpt -pb calc_power_summary_routed.pb -rpx calc_power_routed.rpx"
create_report "impl_1_route_report_route_status_0" "report_route_status -file calc_route_status.rpt -pb calc_route_status.pb"
create_report "impl_1_route_report_timing_summary_0" "report_timing_summary -max_paths 10 -file calc_timing_summary_routed.rpt -pb calc_timing_summary_routed.pb -rpx calc_timing_summary_routed.rpx -warn_on_violation "
create_report "impl_1_route_report_incremental_reuse_0" "report_incremental_reuse -file calc_incremental_reuse_routed.rpt"
create_report "impl_1_route_report_clock_utilization_0" "report_clock_utilization -file calc_clock_utilization_routed.rpt"
create_report "impl_1_route_report_bus_skew_0" "report_bus_skew -warn_on_violation -file route_report_bus_skew_0.rpt -rpx route_report_bus_skew_0.rpx"
close_msg_db -file route_design.pb
} RESULT]
if {$rc} {
write_checkpoint -force calc_routed_error.dcp
step_failed route_design
return -code error $RESULT
} else {
end_step route_design
unset ACTIVE_STEP
}
start_step write_bitstream
set ACTIVE_STEP write_bitstream
set rc [catch {
create_msg_db write_bitstream.pb
catch { write_mem_info -force calc.mmi }
write_bitstream -force calc.bit
catch {write_debug_probes -quiet -force calc}
catch {file copy -force calc.ltx debug_nets.ltx}
close_msg_db -file write_bitstream.pb
} RESULT]
if {$rc} {
step_failed write_bitstream
return -code error $RESULT
} else {
end_step write_bitstream
unset ACTIVE_STEP
}

450
Exp4/Exp4.runs/impl_1/calc.vdi Normal file
View File

@@ -0,0 +1,450 @@
#-----------------------------------------------------------
# Vivado v2018.1 (64-bit)
# SW Build 2188600 on Wed Apr 4 18:40:38 MDT 2018
# IP Build 2185939 on Wed Apr 4 20:55:05 MDT 2018
# Start of session at: Thu Nov 7 02:28:43 2024
# Process ID: 25584
# Current directory: F:/Schoolwork/DigitalLogic/Exp4/Exp4.runs/impl_1
# Command line: vivado.exe -log calc.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source calc.tcl -notrace
# Log file: F:/Schoolwork/DigitalLogic/Exp4/Exp4.runs/impl_1/calc.vdi
# Journal file: F:/Schoolwork/DigitalLogic/Exp4/Exp4.runs/impl_1\vivado.jou
#-----------------------------------------------------------
source calc.tcl -notrace
Command: link_design -top calc -part xc7a35tcsg324-1
Design is defaulting to srcset: sources_1
Design is defaulting to constrset: constrs_1
INFO: [Netlist 29-17] Analyzing 16 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-479] Netlist was created with Vivado 2018.1
INFO: [Device 21-403] Loading part xc7a35tcsg324-1
INFO: [Project 1-570] Preparing netlist for logic optimization
Parsing XDC File [F:/Schoolwork/DigitalLogic/Exp4/Exp4.srcs/constrs_1/new/calc.xdc]
Finished Parsing XDC File [F:/Schoolwork/DigitalLogic/Exp4/Exp4.srcs/constrs_1/new/calc.xdc]
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
INFO: [Project 1-111] Unisim Transformation Summary:
A total of 2 instances were transformed.
LDCP => LDCP (GND, LUT3, LUT3, LDCE, VCC): 2 instances
7 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
link_design completed successfully
link_design: Time (s): cpu = 00:00:04 ; elapsed = 00:00:06 . Memory (MB): peak = 608.344 ; gain = 303.082
Command: opt_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t'
Running DRC as a precondition to command opt_design
Starting DRC Task
INFO: [DRC 23-27] Running DRC with 2 threads
INFO: [Project 1-461] DRC finished with 0 Errors
INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information.
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.373 . Memory (MB): peak = 623.590 ; gain = 15.246
INFO: [Timing 38-35] Done setting XDC timing constraints.
Starting Logic Optimization Task
Phase 1 Retarget
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
INFO: [Opt 31-49] Retargeted 0 cell(s).
Phase 1 Retarget | Checksum: 276aac3f7
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.004 . Memory (MB): peak = 1170.543 ; gain = 0.000
INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 0 cells
Phase 2 Constant propagation
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Phase 2 Constant propagation | Checksum: 276aac3f7
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.005 . Memory (MB): peak = 1170.543 ; gain = 0.000
INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells
Phase 3 Sweep
Phase 3 Sweep | Checksum: 276aac3f7
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.006 . Memory (MB): peak = 1170.543 ; gain = 0.000
INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 0 cells
Phase 4 BUFG optimization
Phase 4 BUFG optimization | Checksum: 276aac3f7
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.007 . Memory (MB): peak = 1170.543 ; gain = 0.000
INFO: [Opt 31-389] Phase BUFG optimization created 0 cells and removed 0 cells
Phase 5 Shift Register Optimization
Phase 5 Shift Register Optimization | Checksum: 276aac3f7
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.008 . Memory (MB): peak = 1170.543 ; gain = 0.000
INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells
Phase 6 Post Processing Netlist
Phase 6 Post Processing Netlist | Checksum: 276aac3f7
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.009 . Memory (MB): peak = 1170.543 ; gain = 0.000
INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells
Starting Connectivity Check Task
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1170.543 ; gain = 0.000
Ending Logic Optimization Task | Checksum: 276aac3f7
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.009 . Memory (MB): peak = 1170.543 ; gain = 0.000
Starting Power Optimization Task
INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns.
Ending Power Optimization Task | Checksum: 276aac3f7
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.005 . Memory (MB): peak = 1170.543 ; gain = 0.000
INFO: [Common 17-83] Releasing license: Implementation
23 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
opt_design completed successfully
opt_design: Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 1170.543 ; gain = 562.199
INFO: [Timing 38-480] Writing timing data to binary archive.
Writing placer database...
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.017 . Memory (MB): peak = 1170.543 ; gain = 0.000
INFO: [Common 17-1381] The checkpoint 'F:/Schoolwork/DigitalLogic/Exp4/Exp4.runs/impl_1/calc_opt.dcp' has been generated.
INFO: [runtcl-4] Executing : report_drc -file calc_drc_opted.rpt -pb calc_drc_opted.pb -rpx calc_drc_opted.rpx
Command: report_drc -file calc_drc_opted.rpt -pb calc_drc_opted.pb -rpx calc_drc_opted.rpx
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'D:/Xilinx/Vivado/2018.1/data/ip'.
INFO: [DRC 23-27] Running DRC with 2 threads
INFO: [Coretcl 2-168] The results of DRC are in file F:/Schoolwork/DigitalLogic/Exp4/Exp4.runs/impl_1/calc_drc_opted.rpt.
report_drc completed successfully
Command: place_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t'
INFO: [DRC 23-27] Running DRC with 2 threads
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
Running DRC as a precondition to command place_design
INFO: [DRC 23-27] Running DRC with 2 threads
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
Starting Placer Task
INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 2 CPUs
Phase 1 Placer Initialization
Phase 1.1 Placer Initialization Netlist Sorting
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1170.543 ; gain = 0.000
Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 1e2929c37
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.002 . Memory (MB): peak = 1170.543 ; gain = 0.000
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1170.543 ; gain = 0.000
Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device
INFO: [Timing 38-35] Done setting XDC timing constraints.
Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 137b1e3de
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.322 . Memory (MB): peak = 1183.531 ; gain = 12.988
Phase 1.3 Build Placer Netlist Model
Phase 1.3 Build Placer Netlist Model | Checksum: 1dab45a3d
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.330 . Memory (MB): peak = 1183.531 ; gain = 12.988
Phase 1.4 Constrain Clocks/Macros
Phase 1.4 Constrain Clocks/Macros | Checksum: 1dab45a3d
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.330 . Memory (MB): peak = 1183.531 ; gain = 12.988
Phase 1 Placer Initialization | Checksum: 1dab45a3d
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.331 . Memory (MB): peak = 1183.531 ; gain = 12.988
Phase 2 Global Placement
Phase 2 Global Placement | Checksum: 1e6d939ab
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.463 . Memory (MB): peak = 1183.531 ; gain = 12.988
Phase 3 Detail Placement
Phase 3.1 Commit Multi Column Macros
Phase 3.1 Commit Multi Column Macros | Checksum: 1e6d939ab
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.464 . Memory (MB): peak = 1183.531 ; gain = 12.988
Phase 3.2 Commit Most Macros & LUTRAMs
Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 219db61c9
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.470 . Memory (MB): peak = 1183.531 ; gain = 12.988
Phase 3.3 Area Swap Optimization
Phase 3.3 Area Swap Optimization | Checksum: 151450402
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.474 . Memory (MB): peak = 1183.531 ; gain = 12.988
Phase 3.4 Pipeline Register Optimization
Phase 3.4 Pipeline Register Optimization | Checksum: 151450402
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.474 . Memory (MB): peak = 1183.531 ; gain = 12.988
Phase 3.5 Small Shape Detail Placement
Phase 3.5 Small Shape Detail Placement | Checksum: 14e2b920e
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.516 . Memory (MB): peak = 1183.531 ; gain = 12.988
Phase 3.6 Re-assign LUT pins
Phase 3.6 Re-assign LUT pins | Checksum: 14e2b920e
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.519 . Memory (MB): peak = 1183.531 ; gain = 12.988
Phase 3.7 Pipeline Register Optimization
Phase 3.7 Pipeline Register Optimization | Checksum: 14e2b920e
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.519 . Memory (MB): peak = 1183.531 ; gain = 12.988
Phase 3 Detail Placement | Checksum: 14e2b920e
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.519 . Memory (MB): peak = 1183.531 ; gain = 12.988
Phase 4 Post Placement Optimization and Clean-Up
Phase 4.1 Post Commit Optimization
Phase 4.1 Post Commit Optimization | Checksum: 14e2b920e
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.521 . Memory (MB): peak = 1183.531 ; gain = 12.988
Phase 4.2 Post Placement Cleanup
Phase 4.2 Post Placement Cleanup | Checksum: 14e2b920e
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.522 . Memory (MB): peak = 1183.531 ; gain = 12.988
Phase 4.3 Placer Reporting
Phase 4.3 Placer Reporting | Checksum: 14e2b920e
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.523 . Memory (MB): peak = 1183.531 ; gain = 12.988
Phase 4.4 Final Placement Cleanup
Phase 4.4 Final Placement Cleanup | Checksum: 14e2b920e
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.523 . Memory (MB): peak = 1183.531 ; gain = 12.988
Phase 4 Post Placement Optimization and Clean-Up | Checksum: 14e2b920e
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.523 . Memory (MB): peak = 1183.531 ; gain = 12.988
Ending Placer Task | Checksum: 1015e41ce
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.525 . Memory (MB): peak = 1183.531 ; gain = 12.988
INFO: [Common 17-83] Releasing license: Implementation
41 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
place_design completed successfully
INFO: [Timing 38-480] Writing timing data to binary archive.
Writing placer database...
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.019 . Memory (MB): peak = 1183.531 ; gain = 0.000
INFO: [Common 17-1381] The checkpoint 'F:/Schoolwork/DigitalLogic/Exp4/Exp4.runs/impl_1/calc_placed.dcp' has been generated.
INFO: [runtcl-4] Executing : report_io -file calc_io_placed.rpt
report_io: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.028 . Memory (MB): peak = 1188.391 ; gain = 0.000
INFO: [runtcl-4] Executing : report_utilization -file calc_utilization_placed.rpt -pb calc_utilization_placed.pb
report_utilization: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.013 . Memory (MB): peak = 1188.391 ; gain = 0.000
INFO: [runtcl-4] Executing : report_control_sets -verbose -file calc_control_sets_placed.rpt
report_control_sets: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1188.391 ; gain = 0.000
Command: route_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t'
Running DRC as a precondition to command route_design
INFO: [DRC 23-27] Running DRC with 2 threads
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
Starting Routing Task
INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 2 CPUs
Checksum: PlaceDB: 37ead21 ConstDB: 0 ShapeSum: fddf94ad RouteDB: 0
Phase 1 Build RT Design
Phase 1 Build RT Design | Checksum: bf67df9b
Time (s): cpu = 00:00:12 ; elapsed = 00:00:11 . Memory (MB): peak = 1302.117 ; gain = 113.727
Post Restoration Checksum: NetGraph: 4572a9c8 NumContArr: 79f535d3 Constraints: 0 Timing: 0
Phase 2 Router Initialization
INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode.
Phase 2.1 Fix Topology Constraints
Phase 2.1 Fix Topology Constraints | Checksum: bf67df9b
Time (s): cpu = 00:00:12 ; elapsed = 00:00:11 . Memory (MB): peak = 1308.117 ; gain = 119.727
Phase 2.2 Pre Route Cleanup
Phase 2.2 Pre Route Cleanup | Checksum: bf67df9b
Time (s): cpu = 00:00:12 ; elapsed = 00:00:11 . Memory (MB): peak = 1308.117 ; gain = 119.727
Number of Nodes with overlaps = 0
Phase 2 Router Initialization | Checksum: 11937b63c
Time (s): cpu = 00:00:12 ; elapsed = 00:00:11 . Memory (MB): peak = 1310.898 ; gain = 122.508
Phase 3 Initial Routing
Phase 3 Initial Routing | Checksum: 1a7a41aad
Time (s): cpu = 00:00:12 ; elapsed = 00:00:11 . Memory (MB): peak = 1310.898 ; gain = 122.508
Phase 4 Rip-up And Reroute
Phase 4.1 Global Iteration 0
Number of Nodes with overlaps = 6
Number of Nodes with overlaps = 0
Phase 4.1 Global Iteration 0 | Checksum: b875e9c3
Time (s): cpu = 00:00:12 ; elapsed = 00:00:11 . Memory (MB): peak = 1310.898 ; gain = 122.508
Phase 4 Rip-up And Reroute | Checksum: b875e9c3
Time (s): cpu = 00:00:12 ; elapsed = 00:00:11 . Memory (MB): peak = 1310.898 ; gain = 122.508
Phase 5 Delay and Skew Optimization
Phase 5 Delay and Skew Optimization | Checksum: b875e9c3
Time (s): cpu = 00:00:12 ; elapsed = 00:00:11 . Memory (MB): peak = 1310.898 ; gain = 122.508
Phase 6 Post Hold Fix
Phase 6.1 Hold Fix Iter
Phase 6.1 Hold Fix Iter | Checksum: b875e9c3
Time (s): cpu = 00:00:12 ; elapsed = 00:00:11 . Memory (MB): peak = 1310.898 ; gain = 122.508
Phase 6 Post Hold Fix | Checksum: b875e9c3
Time (s): cpu = 00:00:12 ; elapsed = 00:00:11 . Memory (MB): peak = 1310.898 ; gain = 122.508
Phase 7 Route finalize
Router Utilization Summary
Global Vertical Routing Utilization = 0.0557283 %
Global Horizontal Routing Utilization = 0.0265487 %
Routable Net Status*
*Does not include unroutable nets such as driverless and loadless.
Run report_route_status for detailed report.
Number of Failed Nets = 0
Number of Unrouted Nets = 0
Number of Partially Routed Nets = 0
Number of Node Overlaps = 0
Congestion Report
North Dir 1x1 Area, Max Cong = 16.2162%, No Congested Regions.
South Dir 1x1 Area, Max Cong = 26.1261%, No Congested Regions.
East Dir 1x1 Area, Max Cong = 13.2353%, No Congested Regions.
West Dir 1x1 Area, Max Cong = 8.82353%, No Congested Regions.
------------------------------
Reporting congestion hotspots
------------------------------
Direction: North
----------------
Congested clusters found at Level 0
Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0
Direction: South
----------------
Congested clusters found at Level 0
Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0
Direction: East
----------------
Congested clusters found at Level 0
Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0
Direction: West
----------------
Congested clusters found at Level 0
Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0
Phase 7 Route finalize | Checksum: b875e9c3
Time (s): cpu = 00:00:12 ; elapsed = 00:00:11 . Memory (MB): peak = 1310.898 ; gain = 122.508
Phase 8 Verifying routed nets
Verification completed successfully
Phase 8 Verifying routed nets | Checksum: b875e9c3
Time (s): cpu = 00:00:12 ; elapsed = 00:00:11 . Memory (MB): peak = 1312.164 ; gain = 123.773
Phase 9 Depositing Routes
Phase 9 Depositing Routes | Checksum: 144801a5b
Time (s): cpu = 00:00:12 ; elapsed = 00:00:11 . Memory (MB): peak = 1312.164 ; gain = 123.773
INFO: [Route 35-16] Router Completed Successfully
Time (s): cpu = 00:00:12 ; elapsed = 00:00:11 . Memory (MB): peak = 1312.164 ; gain = 123.773
Routing Is Done.
INFO: [Common 17-83] Releasing license: Implementation
54 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
route_design completed successfully
route_design: Time (s): cpu = 00:00:13 ; elapsed = 00:00:11 . Memory (MB): peak = 1312.164 ; gain = 123.773
INFO: [Timing 38-480] Writing timing data to binary archive.
Writing placer database...
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.022 . Memory (MB): peak = 1312.164 ; gain = 0.000
INFO: [Common 17-1381] The checkpoint 'F:/Schoolwork/DigitalLogic/Exp4/Exp4.runs/impl_1/calc_routed.dcp' has been generated.
INFO: [runtcl-4] Executing : report_drc -file calc_drc_routed.rpt -pb calc_drc_routed.pb -rpx calc_drc_routed.rpx
Command: report_drc -file calc_drc_routed.rpt -pb calc_drc_routed.pb -rpx calc_drc_routed.rpx
INFO: [DRC 23-27] Running DRC with 2 threads
INFO: [Coretcl 2-168] The results of DRC are in file F:/Schoolwork/DigitalLogic/Exp4/Exp4.runs/impl_1/calc_drc_routed.rpt.
report_drc completed successfully
INFO: [runtcl-4] Executing : report_methodology -file calc_methodology_drc_routed.rpt -pb calc_methodology_drc_routed.pb -rpx calc_methodology_drc_routed.rpx
Command: report_methodology -file calc_methodology_drc_routed.rpt -pb calc_methodology_drc_routed.pb -rpx calc_methodology_drc_routed.rpx
INFO: [Timing 38-35] Done setting XDC timing constraints.
INFO: [Timing 38-35] Done setting XDC timing constraints.
INFO: [DRC 23-133] Running Methodology with 2 threads
INFO: [Coretcl 2-1520] The results of Report Methodology are in file F:/Schoolwork/DigitalLogic/Exp4/Exp4.runs/impl_1/calc_methodology_drc_routed.rpt.
report_methodology completed successfully
INFO: [runtcl-4] Executing : report_power -file calc_power_routed.rpt -pb calc_power_summary_routed.pb -rpx calc_power_routed.rpx
Command: report_power -file calc_power_routed.rpt -pb calc_power_summary_routed.pb -rpx calc_power_routed.rpx
WARNING: [Power 33-232] No user defined clocks were found in the design!
Resolution: Please specify clocks using create_clock/create_generated_clock for sequential elements. For pure combinatorial circuits, please specify a virtual clock, otherwise the vectorless estimation might be inaccurate
INFO: [Timing 38-35] Done setting XDC timing constraints.
Running Vector-less Activity Propagation...
Finished Running Vector-less Activity Propagation
66 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered.
report_power completed successfully
INFO: [runtcl-4] Executing : report_route_status -file calc_route_status.rpt -pb calc_route_status.pb
INFO: [runtcl-4] Executing : report_timing_summary -max_paths 10 -file calc_timing_summary_routed.rpt -pb calc_timing_summary_routed.pb -rpx calc_timing_summary_routed.rpx -warn_on_violation
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max, Timing Stage: Requireds.
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs
WARNING: [Timing 38-313] There are no user specified timing constraints. Timing constraints are needed for proper timing analysis.
INFO: [runtcl-4] Executing : report_incremental_reuse -file calc_incremental_reuse_routed.rpt
INFO: [Vivado_Tcl 4-545] No incremental reuse to report, no incremental placement and routing data was found.
INFO: [runtcl-4] Executing : report_clock_utilization -file calc_clock_utilization_routed.rpt
INFO: [runtcl-4] Executing : report_bus_skew -warn_on_violation -file route_report_bus_skew_0.rpt -rpx route_report_bus_skew_0.rpx
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max, Timing Stage: Requireds.
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs
Command: write_bitstream -force calc.bit
Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t'
Running DRC as a precondition to command write_bitstream
INFO: [DRC 23-27] Running DRC with 2 threads
WARNING: [DRC CFGBVS-1] Missing CFGBVS and CONFIG_VOLTAGE Design Properties: Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design. Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0. It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax:
set_property CFGBVS value1 [current_design]
#where value1 is either VCCO or GND
set_property CONFIG_VOLTAGE value2 [current_design]
#where value2 is the voltage provided to configuration bank 0
Refer to the device configuration user guide for more information.
WARNING: [DRC PDRC-153] Gated clock check: Net run/result_reg[2]/G0 is a gated clock net sourced by a combinational pin run/result_reg[2]/L3_2/O, cell run/result_reg[2]/L3_2. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.
WARNING: [DRC PDRC-153] Gated clock check: Net run/result_reg[3]/G0 is a gated clock net sourced by a combinational pin run/result_reg[3]/L3_2/O, cell run/result_reg[3]/L3_2. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.
WARNING: [DRC PDRC-153] Gated clock check: Net run/result_reg[3]_i_1_n_0 is a gated clock net sourced by a combinational pin run/result_reg[3]_i_1/O, cell run/result_reg[3]_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.
INFO: [Vivado 12-3199] DRC finished with 0 Errors, 4 Warnings
INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information.
INFO: [Designutils 20-2272] Running write_bitstream with 2 threads.
Loading data files...
Loading site data...
Loading route data...
Processing options...
Creating bitmap...
Creating bitstream...
Writing bitstream ./calc.bit...
INFO: [Vivado 12-1842] Bitgen Completed Successfully.
INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory.
INFO: [Common 17-83] Releasing license: Implementation
84 Infos, 6 Warnings, 0 Critical Warnings and 0 Errors encountered.
write_bitstream completed successfully
write_bitstream: Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 1766.340 ; gain = 420.117
INFO: [Common 17-206] Exiting Vivado at Thu Nov 7 02:29:25 2024...

424
Exp4/Exp4.runs/impl_1/calc_20992.backup.vdi Normal file
View File

@@ -0,0 +1,424 @@
#-----------------------------------------------------------
# Vivado v2018.1 (64-bit)
# SW Build 2188600 on Wed Apr 4 18:40:38 MDT 2018
# IP Build 2185939 on Wed Apr 4 20:55:05 MDT 2018
# Start of session at: Thu Nov 7 02:25:03 2024
# Process ID: 20992
# Current directory: F:/Schoolwork/DigitalLogic/Exp4/Exp4.runs/impl_1
# Command line: vivado.exe -log calc.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source calc.tcl -notrace
# Log file: F:/Schoolwork/DigitalLogic/Exp4/Exp4.runs/impl_1/calc.vdi
# Journal file: F:/Schoolwork/DigitalLogic/Exp4/Exp4.runs/impl_1\vivado.jou
#-----------------------------------------------------------
source calc.tcl -notrace
Command: open_checkpoint F:/Schoolwork/DigitalLogic/Exp4/Exp4.runs/impl_1/calc.dcp
Starting open_checkpoint Task
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.021 . Memory (MB): peak = 241.820 ; gain = 0.000
INFO: [Netlist 29-17] Analyzing 16 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 1 CPU seconds
INFO: [Project 1-479] Netlist was created with Vivado 2018.1
INFO: [Device 21-403] Loading part xc7a35tcsg324-1
INFO: [Project 1-570] Preparing netlist for logic optimization
INFO: [Timing 38-478] Restoring timing data from binary archive.
INFO: [Timing 38-479] Binary timing data restore complete.
INFO: [Project 1-856] Restoring constraints from binary archive.
INFO: [Project 1-853] Binary constraint restore complete.
Reading XDEF placement.
Reading placer database...
Reading XDEF routing.
Read XDEF File: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.051 . Memory (MB): peak = 1100.367 ; gain = 0.000
Restored from archive | CPU: 0.000000 secs | Memory: 0.000000 MB |
Finished XDEF File Restore: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.051 . Memory (MB): peak = 1100.367 ; gain = 0.000
INFO: [Project 1-111] Unisim Transformation Summary:
A total of 2 instances were transformed.
LDCP => LDCP (GND, LUT3, LUT3, LDCE, VCC): 2 instances
INFO: [Project 1-604] Checkpoint was created with Vivado v2018.1 (64-bit) build 2188600
open_checkpoint: Time (s): cpu = 00:00:12 ; elapsed = 00:00:15 . Memory (MB): peak = 1100.367 ; gain = 867.789
Command: opt_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t'
Running DRC as a precondition to command opt_design
Starting DRC Task
INFO: [DRC 23-27] Running DRC with 2 threads
INFO: [Project 1-461] DRC finished with 0 Errors
INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information.
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.315 . Memory (MB): peak = 1100.367 ; gain = 0.000
INFO: [Timing 38-35] Done setting XDC timing constraints.
Starting Logic Optimization Task
Phase 1 Retarget
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
INFO: [Opt 31-49] Retargeted 0 cell(s).
Phase 1 Retarget | Checksum: 22bbafb85
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.014 . Memory (MB): peak = 1182.973 ; gain = 0.000
INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 0 cells
Phase 2 Constant propagation
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Phase 2 Constant propagation | Checksum: 22bbafb85
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.016 . Memory (MB): peak = 1182.973 ; gain = 0.000
INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells
Phase 3 Sweep
Phase 3 Sweep | Checksum: 22bbafb85
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.019 . Memory (MB): peak = 1182.973 ; gain = 0.000
INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 0 cells
Phase 4 BUFG optimization
Phase 4 BUFG optimization | Checksum: 22bbafb85
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.022 . Memory (MB): peak = 1182.973 ; gain = 0.000
INFO: [Opt 31-389] Phase BUFG optimization created 0 cells and removed 0 cells
Phase 5 Shift Register Optimization
Phase 5 Shift Register Optimization | Checksum: 22bbafb85
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.023 . Memory (MB): peak = 1182.973 ; gain = 0.000
INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells
Phase 6 Post Processing Netlist
Phase 6 Post Processing Netlist | Checksum: 22bbafb85
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.023 . Memory (MB): peak = 1182.973 ; gain = 0.000
INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells
Starting Connectivity Check Task
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1182.973 ; gain = 0.000
Ending Logic Optimization Task | Checksum: 22bbafb85
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.024 . Memory (MB): peak = 1182.973 ; gain = 0.000
Starting Power Optimization Task
INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns.
Ending Power Optimization Task | Checksum: 22bbafb85
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.007 . Memory (MB): peak = 1182.973 ; gain = 0.000
INFO: [Common 17-83] Releasing license: Implementation
27 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
opt_design completed successfully
INFO: [Timing 38-480] Writing timing data to binary archive.
Writing placer database...
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.016 . Memory (MB): peak = 1182.973 ; gain = 0.000
INFO: [Common 17-1381] The checkpoint 'F:/Schoolwork/DigitalLogic/Exp4/Exp4.runs/impl_1/calc_opt.dcp' has been generated.
INFO: [runtcl-4] Executing : report_drc -file calc_drc_opted.rpt -pb calc_drc_opted.pb -rpx calc_drc_opted.rpx
Command: report_drc -file calc_drc_opted.rpt -pb calc_drc_opted.pb -rpx calc_drc_opted.rpx
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'D:/Xilinx/Vivado/2018.1/data/ip'.
INFO: [DRC 23-27] Running DRC with 2 threads
INFO: [Coretcl 2-168] The results of DRC are in file F:/Schoolwork/DigitalLogic/Exp4/Exp4.runs/impl_1/calc_drc_opted.rpt.
report_drc completed successfully
Command: place_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t'
INFO: [DRC 23-27] Running DRC with 2 threads
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
Running DRC as a precondition to command place_design
INFO: [DRC 23-27] Running DRC with 2 threads
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
Starting Placer Task
INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 2 CPUs
Phase 1 Placer Initialization
Phase 1.1 Placer Initialization Netlist Sorting
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1182.973 ; gain = 0.000
Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 1e2929c37
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.005 . Memory (MB): peak = 1182.973 ; gain = 0.000
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1182.973 ; gain = 0.000
Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device
INFO: [Timing 38-35] Done setting XDC timing constraints.
Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 137b1e3de
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.353 . Memory (MB): peak = 1184.621 ; gain = 1.648
Phase 1.3 Build Placer Netlist Model
Phase 1.3 Build Placer Netlist Model | Checksum: 1a38e33f2
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.372 . Memory (MB): peak = 1184.621 ; gain = 1.648
Phase 1.4 Constrain Clocks/Macros
Phase 1.4 Constrain Clocks/Macros | Checksum: 1a38e33f2
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.374 . Memory (MB): peak = 1184.621 ; gain = 1.648
Phase 1 Placer Initialization | Checksum: 1a38e33f2
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.376 . Memory (MB): peak = 1184.621 ; gain = 1.648
Phase 2 Global Placement
Phase 2 Global Placement | Checksum: 165725f0a
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.517 . Memory (MB): peak = 1184.621 ; gain = 1.648
Phase 3 Detail Placement
Phase 3.1 Commit Multi Column Macros
Phase 3.1 Commit Multi Column Macros | Checksum: 165725f0a
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.519 . Memory (MB): peak = 1184.621 ; gain = 1.648
Phase 3.2 Commit Most Macros & LUTRAMs
Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 1c30658d9
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.527 . Memory (MB): peak = 1184.621 ; gain = 1.648
Phase 3.3 Area Swap Optimization
Phase 3.3 Area Swap Optimization | Checksum: 151c71063
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.530 . Memory (MB): peak = 1184.621 ; gain = 1.648
Phase 3.4 Pipeline Register Optimization
Phase 3.4 Pipeline Register Optimization | Checksum: 151c71063
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.531 . Memory (MB): peak = 1184.621 ; gain = 1.648
Phase 3.5 Small Shape Detail Placement
Phase 3.5 Small Shape Detail Placement | Checksum: 1f97b56aa
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.574 . Memory (MB): peak = 1184.621 ; gain = 1.648
Phase 3.6 Re-assign LUT pins
Phase 3.6 Re-assign LUT pins | Checksum: 1f97b56aa
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.577 . Memory (MB): peak = 1184.621 ; gain = 1.648
Phase 3.7 Pipeline Register Optimization
Phase 3.7 Pipeline Register Optimization | Checksum: 1f97b56aa
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.577 . Memory (MB): peak = 1184.621 ; gain = 1.648
Phase 3 Detail Placement | Checksum: 1f97b56aa
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.578 . Memory (MB): peak = 1184.621 ; gain = 1.648
Phase 4 Post Placement Optimization and Clean-Up
Phase 4.1 Post Commit Optimization
Phase 4.1 Post Commit Optimization | Checksum: 1f97b56aa
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.579 . Memory (MB): peak = 1184.621 ; gain = 1.648
Phase 4.2 Post Placement Cleanup
Phase 4.2 Post Placement Cleanup | Checksum: 1f97b56aa
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.583 . Memory (MB): peak = 1184.621 ; gain = 1.648
Phase 4.3 Placer Reporting
Phase 4.3 Placer Reporting | Checksum: 1f97b56aa
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.583 . Memory (MB): peak = 1184.621 ; gain = 1.648
Phase 4.4 Final Placement Cleanup
Phase 4.4 Final Placement Cleanup | Checksum: 1f97b56aa
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.584 . Memory (MB): peak = 1184.621 ; gain = 1.648
Phase 4 Post Placement Optimization and Clean-Up | Checksum: 1f97b56aa
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.584 . Memory (MB): peak = 1184.621 ; gain = 1.648
Ending Placer Task | Checksum: 14b4f553e
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.586 . Memory (MB): peak = 1184.621 ; gain = 1.648
INFO: [Common 17-83] Releasing license: Implementation
45 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
place_design completed successfully
INFO: [Timing 38-480] Writing timing data to binary archive.
Writing placer database...
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.018 . Memory (MB): peak = 1184.621 ; gain = 0.000
INFO: [Common 17-1381] The checkpoint 'F:/Schoolwork/DigitalLogic/Exp4/Exp4.runs/impl_1/calc_placed.dcp' has been generated.
INFO: [runtcl-4] Executing : report_io -file calc_io_placed.rpt
report_io: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.026 . Memory (MB): peak = 1189.809 ; gain = 0.000
INFO: [runtcl-4] Executing : report_utilization -file calc_utilization_placed.rpt -pb calc_utilization_placed.pb
report_utilization: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.013 . Memory (MB): peak = 1189.809 ; gain = 0.000
INFO: [runtcl-4] Executing : report_control_sets -verbose -file calc_control_sets_placed.rpt
report_control_sets: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1189.809 ; gain = 0.000
Command: route_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t'
Running DRC as a precondition to command route_design
INFO: [DRC 23-27] Running DRC with 2 threads
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
Starting Routing Task
INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 2 CPUs
Checksum: PlaceDB: 4d6fc091 ConstDB: 0 ShapeSum: fddf94ad RouteDB: 0
Phase 1 Build RT Design
Phase 1 Build RT Design | Checksum: 98e94c16
Time (s): cpu = 00:00:12 ; elapsed = 00:00:10 . Memory (MB): peak = 1302.215 ; gain = 112.406
Post Restoration Checksum: NetGraph: 3ae684d6 NumContArr: 5e02c740 Constraints: 0 Timing: 0
Phase 2 Router Initialization
INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode.
Phase 2.1 Fix Topology Constraints
Phase 2.1 Fix Topology Constraints | Checksum: 98e94c16
Time (s): cpu = 00:00:12 ; elapsed = 00:00:11 . Memory (MB): peak = 1308.246 ; gain = 118.438
Phase 2.2 Pre Route Cleanup
Phase 2.2 Pre Route Cleanup | Checksum: 98e94c16
Time (s): cpu = 00:00:12 ; elapsed = 00:00:11 . Memory (MB): peak = 1308.246 ; gain = 118.438
Number of Nodes with overlaps = 0
Phase 2 Router Initialization | Checksum: 123501692
Time (s): cpu = 00:00:12 ; elapsed = 00:00:11 . Memory (MB): peak = 1312.078 ; gain = 122.270
Phase 3 Initial Routing
Phase 3 Initial Routing | Checksum: 10ee29832
Time (s): cpu = 00:00:12 ; elapsed = 00:00:11 . Memory (MB): peak = 1312.078 ; gain = 122.270
Phase 4 Rip-up And Reroute
Phase 4.1 Global Iteration 0
Number of Nodes with overlaps = 5
Number of Nodes with overlaps = 0
Phase 4.1 Global Iteration 0 | Checksum: fb0c9e35
Time (s): cpu = 00:00:12 ; elapsed = 00:00:11 . Memory (MB): peak = 1312.078 ; gain = 122.270
Phase 4 Rip-up And Reroute | Checksum: fb0c9e35
Time (s): cpu = 00:00:12 ; elapsed = 00:00:11 . Memory (MB): peak = 1312.078 ; gain = 122.270
Phase 5 Delay and Skew Optimization
Phase 5 Delay and Skew Optimization | Checksum: fb0c9e35
Time (s): cpu = 00:00:12 ; elapsed = 00:00:11 . Memory (MB): peak = 1312.078 ; gain = 122.270
Phase 6 Post Hold Fix
Phase 6.1 Hold Fix Iter
Phase 6.1 Hold Fix Iter | Checksum: fb0c9e35
Time (s): cpu = 00:00:12 ; elapsed = 00:00:11 . Memory (MB): peak = 1312.078 ; gain = 122.270
Phase 6 Post Hold Fix | Checksum: fb0c9e35
Time (s): cpu = 00:00:12 ; elapsed = 00:00:11 . Memory (MB): peak = 1312.078 ; gain = 122.270
Phase 7 Route finalize
Router Utilization Summary
Global Vertical Routing Utilization = 0.0416168 %
Global Horizontal Routing Utilization = 0.0260281 %
Routable Net Status*
*Does not include unroutable nets such as driverless and loadless.
Run report_route_status for detailed report.
Number of Failed Nets = 0
Number of Unrouted Nets = 0
Number of Partially Routed Nets = 0
Number of Node Overlaps = 0
Congestion Report
North Dir 1x1 Area, Max Cong = 5.40541%, No Congested Regions.
South Dir 1x1 Area, Max Cong = 19.8198%, No Congested Regions.
East Dir 1x1 Area, Max Cong = 13.2353%, No Congested Regions.
West Dir 1x1 Area, Max Cong = 7.35294%, No Congested Regions.
------------------------------
Reporting congestion hotspots
------------------------------
Direction: North
----------------
Congested clusters found at Level 0
Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0
Direction: South
----------------
Congested clusters found at Level 0
Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0
Direction: East
----------------
Congested clusters found at Level 0
Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0
Direction: West
----------------
Congested clusters found at Level 0
Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0
Phase 7 Route finalize | Checksum: fb0c9e35
Time (s): cpu = 00:00:12 ; elapsed = 00:00:11 . Memory (MB): peak = 1312.078 ; gain = 122.270
Phase 8 Verifying routed nets
Verification completed successfully
Phase 8 Verifying routed nets | Checksum: fb0c9e35
Time (s): cpu = 00:00:12 ; elapsed = 00:00:11 . Memory (MB): peak = 1313.828 ; gain = 124.020
Phase 9 Depositing Routes
Phase 9 Depositing Routes | Checksum: 1664a9788
Time (s): cpu = 00:00:12 ; elapsed = 00:00:11 . Memory (MB): peak = 1313.828 ; gain = 124.020
INFO: [Route 35-16] Router Completed Successfully
Time (s): cpu = 00:00:12 ; elapsed = 00:00:11 . Memory (MB): peak = 1313.828 ; gain = 124.020
Routing Is Done.
INFO: [Common 17-83] Releasing license: Implementation
58 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
route_design completed successfully
route_design: Time (s): cpu = 00:00:13 ; elapsed = 00:00:11 . Memory (MB): peak = 1313.828 ; gain = 124.020
INFO: [Timing 38-480] Writing timing data to binary archive.
Writing placer database...
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.019 . Memory (MB): peak = 1313.828 ; gain = 0.000
INFO: [Common 17-1381] The checkpoint 'F:/Schoolwork/DigitalLogic/Exp4/Exp4.runs/impl_1/calc_routed.dcp' has been generated.
INFO: [runtcl-4] Executing : report_drc -file calc_drc_routed.rpt -pb calc_drc_routed.pb -rpx calc_drc_routed.rpx
Command: report_drc -file calc_drc_routed.rpt -pb calc_drc_routed.pb -rpx calc_drc_routed.rpx
INFO: [DRC 23-27] Running DRC with 2 threads
INFO: [Coretcl 2-168] The results of DRC are in file F:/Schoolwork/DigitalLogic/Exp4/Exp4.runs/impl_1/calc_drc_routed.rpt.
report_drc completed successfully
INFO: [runtcl-4] Executing : report_methodology -file calc_methodology_drc_routed.rpt -pb calc_methodology_drc_routed.pb -rpx calc_methodology_drc_routed.rpx
Command: report_methodology -file calc_methodology_drc_routed.rpt -pb calc_methodology_drc_routed.pb -rpx calc_methodology_drc_routed.rpx
INFO: [Timing 38-35] Done setting XDC timing constraints.
INFO: [Timing 38-35] Done setting XDC timing constraints.
INFO: [DRC 23-133] Running Methodology with 2 threads
INFO: [Coretcl 2-1520] The results of Report Methodology are in file F:/Schoolwork/DigitalLogic/Exp4/Exp4.runs/impl_1/calc_methodology_drc_routed.rpt.
report_methodology completed successfully
INFO: [runtcl-4] Executing : report_power -file calc_power_routed.rpt -pb calc_power_summary_routed.pb -rpx calc_power_routed.rpx
Command: report_power -file calc_power_routed.rpt -pb calc_power_summary_routed.pb -rpx calc_power_routed.rpx
WARNING: [Power 33-232] No user defined clocks were found in the design!
Resolution: Please specify clocks using create_clock/create_generated_clock for sequential elements. For pure combinatorial circuits, please specify a virtual clock, otherwise the vectorless estimation might be inaccurate
INFO: [Timing 38-35] Done setting XDC timing constraints.
Running Vector-less Activity Propagation...
Finished Running Vector-less Activity Propagation
70 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered.
report_power completed successfully
INFO: [runtcl-4] Executing : report_route_status -file calc_route_status.rpt -pb calc_route_status.pb
INFO: [runtcl-4] Executing : report_timing_summary -max_paths 10 -file calc_timing_summary_routed.rpt -pb calc_timing_summary_routed.pb -rpx calc_timing_summary_routed.rpx -warn_on_violation
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max, Timing Stage: Requireds.
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs
WARNING: [Timing 38-313] There are no user specified timing constraints. Timing constraints are needed for proper timing analysis.
INFO: [runtcl-4] Executing : report_incremental_reuse -file calc_incremental_reuse_routed.rpt
INFO: [Vivado_Tcl 4-545] No incremental reuse to report, no incremental placement and routing data was found.
INFO: [runtcl-4] Executing : report_clock_utilization -file calc_clock_utilization_routed.rpt
INFO: [runtcl-4] Executing : report_bus_skew -warn_on_violation -file route_report_bus_skew_0.rpt -rpx route_report_bus_skew_0.rpx
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max, Timing Stage: Requireds.
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs
INFO: [Common 17-206] Exiting Vivado at Thu Nov 7 02:25:37 2024...

145
Exp4/Exp4.runs/impl_1/calc_clock_utilization_routed.rpt Normal file
View File

@@ -0,0 +1,145 @@
Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
------------------------------------------------------------------------------------
| Tool Version : Vivado v.2018.1 (win64) Build 2188600 Wed Apr 4 18:40:38 MDT 2018
| Date : Thu Nov 7 02:29:18 2024
| Host : W10-20240912132 running 64-bit major release (build 9200)
| Command : report_clock_utilization -file calc_clock_utilization_routed.rpt
| Design : calc
| Device : 7a35t-csg324
| Speed File : -1 PRODUCTION 1.21 2018-02-08
------------------------------------------------------------------------------------
Clock Utilization Report
Table of Contents
-----------------
1. Clock Primitive Utilization
2. Global Clock Resources
3. Global Clock Source Details
4. Clock Regions: Key Resource Utilization
5. Clock Regions : Global Clock Summary
6. Device Cell Placement Summary for Global Clock g0
7. Clock Region Cell Placement per Global Clock: Region X1Y0
1. Clock Primitive Utilization
------------------------------
+----------+------+-----------+-----+--------------+--------+
| Type | Used | Available | LOC | Clock Region | Pblock |
+----------+------+-----------+-----+--------------+--------+
| BUFGCTRL | 1 | 32 | 0 | 0 | 0 |
| BUFH | 0 | 72 | 0 | 0 | 0 |
| BUFIO | 0 | 20 | 0 | 0 | 0 |
| BUFMR | 0 | 10 | 0 | 0 | 0 |
| BUFR | 0 | 20 | 0 | 0 | 0 |
| MMCM | 0 | 5 | 0 | 0 | 0 |
| PLL | 0 | 5 | 0 | 0 | 0 |
+----------+------+-----------+-----+--------------+--------+
2. Global Clock Resources
-------------------------
+-----------+-----------+-----------------+------------+---------------+--------------+-------------------+-------------+-----------------+--------------+-------+----------------------+---------------+
| Global Id | Source Id | Driver Type/Pin | Constraint | Site | Clock Region | Load Clock Region | Clock Loads | Non-Clock Loads | Clock Period | Clock | Driver Pin | Net |
+-----------+-----------+-----------------+------------+---------------+--------------+-------------------+-------------+-----------------+--------------+-------+----------------------+---------------+
| g0 | src0 | BUFG/O | None | BUFGCTRL_X0Y0 | n/a | 1 | 5 | 0 | | | clk_IBUF_BUFG_inst/O | clk_IBUF_BUFG |
+-----------+-----------+-----------------+------------+---------------+--------------+-------------------+-------------+-----------------+--------------+-------+----------------------+---------------+
* Clock Loads column represents the clock pin loads (pin count)
** Non-Clock Loads column represents the non-clock pin loads (pin count)
3. Global Clock Source Details
------------------------------
+-----------+-----------+-----------------+------------+-----------+--------------+-------------+-----------------+---------------------+--------------+-----------------+----------+
| Source Id | Global Id | Driver Type/Pin | Constraint | Site | Clock Region | Clock Loads | Non-Clock Loads | Source Clock Period | Source Clock | Driver Pin | Net |
+-----------+-----------+-----------------+------------+-----------+--------------+-------------+-----------------+---------------------+--------------+-----------------+----------+
| src0 | g0 | IBUF/O | IOB_X0Y26 | IOB_X0Y26 | X0Y0 | 1 | 0 | | | clk_IBUF_inst/O | clk_IBUF |
+-----------+-----------+-----------------+------------+-----------+--------------+-------------+-----------------+---------------------+--------------+-----------------+----------+
* Clock Loads column represents the clock pin loads (pin count)
** Non-Clock Loads column represents the non-clock pin loads (pin count)
4. Clock Regions: Key Resource Utilization
------------------------------------------
+-------------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+
| | Global Clock | BUFRs | BUFMRs | BUFIOs | MMCM | PLL | GT | PCI | ILOGIC | OLOGIC | FF | LUTM | RAMB18 | RAMB36 | DSP48E2 |
+-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+
| Clock Region Name | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail |
+-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+
| X0Y0 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 1200 | 0 | 400 | 0 | 20 | 0 | 10 | 0 | 20 |
| X1Y0 | 1 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 5 | 1500 | 0 | 450 | 0 | 40 | 0 | 20 | 0 | 20 |
| X0Y1 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 1200 | 0 | 400 | 0 | 20 | 0 | 10 | 0 | 20 |
| X1Y1 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 1500 | 0 | 450 | 0 | 40 | 0 | 20 | 0 | 20 |
| X0Y2 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 1800 | 0 | 400 | 0 | 20 | 0 | 10 | 0 | 20 |
| X1Y2 | 0 | 12 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 950 | 0 | 300 | 0 | 10 | 0 | 5 | 0 | 20 |
+-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+
* Global Clock column represents track count; while other columns represents cell counts
5. Clock Regions : Global Clock Summary
---------------------------------------
All Modules
+----+----+----+
| | X0 | X1 |
+----+----+----+
| Y2 | 0 | 0 |
| Y1 | 0 | 0 |
| Y0 | 0 | 1 |
+----+----+----+
6. Device Cell Placement Summary for Global Clock g0
----------------------------------------------------
+-----------+-----------------+-------------------+-------+-------------+---------------+-------------+----------+----------------+----------+---------------+
| Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net |
+-----------+-----------------+-------------------+-------+-------------+---------------+-------------+----------+----------------+----------+---------------+
| g0 | BUFG/O | n/a | | | | 5 | 0 | 0 | 0 | clk_IBUF_BUFG |
+-----------+-----------------+-------------------+-------+-------------+---------------+-------------+----------+----------------+----------+---------------+
* Logic Loads column represents load cell count of all cell types other than IO, GT and clock resources
** IO Loads column represents load cell count of IO types
*** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc)
**** GT Loads column represents load cell count of GT types
+----+----+----+
| | X0 | X1 |
+----+----+----+
| Y2 | 0 | 0 |
| Y1 | 0 | 0 |
| Y0 | 0 | 5 |
+----+----+----+
7. Clock Region Cell Placement per Global Clock: Region X1Y0
------------------------------------------------------------
+-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+---------------+
| Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | LUTRAM | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net |
+-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+---------------+
| g0 | n/a | BUFG/O | None | 5 | 0 | 5 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | clk_IBUF_BUFG |
+-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+---------------+
* Clock Loads column represents the clock pin loads (pin count)
** Non-Clock Loads column represents the non-clock pin loads (pin count)
*** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts
# Location of BUFG Primitives
set_property LOC BUFGCTRL_X0Y0 [get_cells clk_IBUF_BUFG_inst]
# Location of IO Primitives which is load of clock spine
# Location of clock ports
set_property LOC IOB_X0Y26 [get_ports clk]
# Clock net "clk_IBUF_BUFG" driven by instance "clk_IBUF_BUFG_inst" located at site "BUFGCTRL_X0Y0"
#startgroup
create_pblock {CLKAG_clk_IBUF_BUFG}
add_cells_to_pblock [get_pblocks {CLKAG_clk_IBUF_BUFG}] [get_cells -filter { PRIMITIVE_GROUP != I/O && IS_PRIMITIVE==1 && PRIMITIVE_LEVEL !=INTERNAL } -of_object [get_pins -filter {DIRECTION==IN} -of_objects [get_nets -hierarchical -filter {PARENT=="clk_IBUF_BUFG"}]]]
resize_pblock [get_pblocks {CLKAG_clk_IBUF_BUFG}] -add {CLOCKREGION_X1Y0:CLOCKREGION_X1Y0}
#endgroup

69
Exp4/Exp4.runs/impl_1/calc_control_sets_placed.rpt Normal file
View File

@@ -0,0 +1,69 @@
Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
------------------------------------------------------------------------------------
| Tool Version : Vivado v.2018.1 (win64) Build 2188600 Wed Apr 4 18:40:38 MDT 2018
| Date : Thu Nov 7 02:29:04 2024
| Host : W10-20240912132 running 64-bit major release (build 9200)
| Command : report_control_sets -verbose -file calc_control_sets_placed.rpt
| Design : calc
| Device : xc7a35t
------------------------------------------------------------------------------------
Control Set Information
Table of Contents
-----------------
1. Summary
2. Histogram
3. Flip-Flop Distribution
4. Detailed Control Set Information
1. Summary
----------
+----------------------------------------------------------+-------+
| Status | Count |
+----------------------------------------------------------+-------+
| Number of unique control sets | 4 |
| Unused register locations in slices containing registers | 24 |
+----------------------------------------------------------+-------+
2. Histogram
------------
+--------+--------------+
| Fanout | Control Sets |
+--------+--------------+
| 1 | 3 |
| 5 | 1 |
+--------+--------------+
3. Flip-Flop Distribution
-------------------------
+--------------+-----------------------+------------------------+-----------------+--------------+
| Clock Enable | Synchronous Set/Reset | Asynchronous Set/Reset | Total Registers | Total Slices |
+--------------+-----------------------+------------------------+-----------------+--------------+
| No | No | No | 2 | 2 |
| No | No | Yes | 0 | 0 |
| No | Yes | No | 1 | 1 |
| Yes | No | No | 5 | 2 |
| Yes | No | Yes | 0 | 0 |
| Yes | Yes | No | 0 | 0 |
+--------------+-----------------------+------------------------+-----------------+--------------+
4. Detailed Control Set Information
-----------------------------------
+----------------------------+------------------------+---------------------------+------------------+----------------+
| Clock Signal | Enable Signal | Set/Reset Signal | Slice Load Count | Bel Load Count |
+----------------------------+------------------------+---------------------------+------------------+----------------+
| run/result_reg[2]/G0 | | | 1 | 1 |
| run/result_reg[3]_i_1_n_0 | | run/result_reg[1]_i_1_n_0 | 1 | 1 |
| run/result_reg[3]/G0 | | | 1 | 1 |
| clk_IBUF_BUFG | stored_type[4]_i_1_n_0 | | 2 | 5 |
+----------------------------+------------------------+---------------------------+------------------+----------------+

BIN
Exp4/Exp4.runs/impl_1/calc_drc_opted.pb Normal file
View File

Binary file not shown.

49
Exp4/Exp4.runs/impl_1/calc_drc_opted.rpt Normal file
View File

@@ -0,0 +1,49 @@
Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
---------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2018.1 (win64) Build 2188600 Wed Apr 4 18:40:38 MDT 2018
| Date : Thu Nov 7 02:29:03 2024
| Host : W10-20240912132 running 64-bit major release (build 9200)
| Command : report_drc -file calc_drc_opted.rpt -pb calc_drc_opted.pb -rpx calc_drc_opted.rpx
| Design : calc
| Device : xc7a35tcsg324-1
| Speed File : -1
| Design State : Synthesized
---------------------------------------------------------------------------------------------------
Report DRC
Table of Contents
-----------------
1. REPORT SUMMARY
2. REPORT DETAILS
1. REPORT SUMMARY
-----------------
Netlist: netlist
Floorplan: design_1
Design limits: <entire design considered>
Ruledeck: default
Max violations: <unlimited>
Violations found: 1
+----------+----------+-----------------------------------------------------+------------+
| Rule | Severity | Description | Violations |
+----------+----------+-----------------------------------------------------+------------+
| CFGBVS-1 | Warning | Missing CFGBVS and CONFIG_VOLTAGE Design Properties | 1 |
+----------+----------+-----------------------------------------------------+------------+
2. REPORT DETAILS
-----------------
CFGBVS-1#1 Warning
Missing CFGBVS and CONFIG_VOLTAGE Design Properties
Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design. Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0. It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax:
set_property CFGBVS value1 [current_design]
#where value1 is either VCCO or GND
set_property CONFIG_VOLTAGE value2 [current_design]
#where value2 is the voltage provided to configuration bank 0
Refer to the device configuration user guide for more information.
Related violations: <none>

BIN
Exp4/Exp4.runs/impl_1/calc_drc_routed.pb Normal file
View File

Binary file not shown.

65
Exp4/Exp4.runs/impl_1/calc_drc_routed.rpt Normal file
View File

@@ -0,0 +1,65 @@
Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2018.1 (win64) Build 2188600 Wed Apr 4 18:40:38 MDT 2018
| Date : Thu Nov 7 02:29:17 2024
| Host : W10-20240912132 running 64-bit major release (build 9200)
| Command : report_drc -file calc_drc_routed.rpt -pb calc_drc_routed.pb -rpx calc_drc_routed.rpx
| Design : calc
| Device : xc7a35tcsg324-1
| Speed File : -1
| Design State : Routed
------------------------------------------------------------------------------------------------------
Report DRC
Table of Contents
-----------------
1. REPORT SUMMARY
2. REPORT DETAILS
1. REPORT SUMMARY
-----------------
Netlist: netlist
Floorplan: design_1
Design limits: <entire design considered>
Ruledeck: default
Max violations: <unlimited>
Violations found: 4
+----------+----------+-----------------------------------------------------+------------+
| Rule | Severity | Description | Violations |
+----------+----------+-----------------------------------------------------+------------+
| CFGBVS-1 | Warning | Missing CFGBVS and CONFIG_VOLTAGE Design Properties | 1 |
| PDRC-153 | Warning | Gated clock check | 3 |
+----------+----------+-----------------------------------------------------+------------+
2. REPORT DETAILS
-----------------
CFGBVS-1#1 Warning
Missing CFGBVS and CONFIG_VOLTAGE Design Properties
Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design. Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0. It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax:
set_property CFGBVS value1 [current_design]
#where value1 is either VCCO or GND
set_property CONFIG_VOLTAGE value2 [current_design]
#where value2 is the voltage provided to configuration bank 0
Refer to the device configuration user guide for more information.
Related violations: <none>
PDRC-153#1 Warning
Gated clock check
Net run/result_reg[2]/G0 is a gated clock net sourced by a combinational pin run/result_reg[2]/L3_2/O, cell run/result_reg[2]/L3_2 (in run/result_reg[2] macro). This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.
Related violations: <none>
PDRC-153#2 Warning
Gated clock check
Net run/result_reg[3]/G0 is a gated clock net sourced by a combinational pin run/result_reg[3]/L3_2/O, cell run/result_reg[3]/L3_2 (in run/result_reg[3] macro). This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.
Related violations: <none>
PDRC-153#3 Warning
Gated clock check
Net run/result_reg[3]_i_1_n_0 is a gated clock net sourced by a combinational pin run/result_reg[3]_i_1/O, cell run/result_reg[3]_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.
Related violations: <none>

366
Exp4/Exp4.runs/impl_1/calc_io_placed.rpt Normal file
View File

@@ -0,0 +1,366 @@
Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
-------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2018.1 (win64) Build 2188600 Wed Apr 4 18:40:38 MDT 2018
| Date : Thu Nov 7 02:29:04 2024
| Host : W10-20240912132 running 64-bit major release (build 9200)
| Command : report_io -file calc_io_placed.rpt
| Design : calc
| Device : xc7a35t
| Speed File : -1
| Package : csg324
| Package Version : FINAL 2013-12-19
| Package Pin Delay Version : VERS. 2.0 2013-12-19
-------------------------------------------------------------------------------------------------
IO Information
Table of Contents
-----------------
1. Summary
2. IO Assignments by Package Pin
1. Summary
----------
+---------------+
| Total User IO |
+---------------+
| 30 |
+---------------+
2. IO Assignments by Package Pin
--------------------------------
+------------+-------------+------------+------------------------------+-------------+-------------+---------+------------+------+---------------------+----------------------+---------+------------+-----------+----------+------+------------------+--------------+-------------------+--------------+
| Pin Number | Signal Name | Bank Type | Pin Name | Use | IO Standard | IO Bank | Drive (mA) | Slew | On-Chip Termination | Off-Chip Termination | Voltage | Constraint | Pull Type | DQS Bias | Vref | Signal Integrity | Pre Emphasis | Lvds Pre Emphasis | Equalization |
+------------+-------------+------------+------------------------------+-------------+-------------+---------+------------+------+---------------------+----------------------+---------+------------+-----------+----------+------+------------------+--------------+-------------------+--------------+
| A1 | | High Range | IO_L9N_T1_DQS_AD7N_35 | User IO | | 35 | | | | | | | | | | | | | |
| A2 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| A3 | | High Range | IO_L8N_T1_AD14N_35 | User IO | | 35 | | | | | | | | | | | | | |
| A4 | | High Range | IO_L8P_T1_AD14P_35 | User IO | | 35 | | | | | | | | | | | | | |
| A5 | | High Range | IO_L3N_T0_DQS_AD5N_35 | User IO | | 35 | | | | | | | | | | | | | |
| A6 | | High Range | IO_L3P_T0_DQS_AD5P_35 | User IO | | 35 | | | | | | | | | | | | | |
| A7 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 3.30 | | | | | | | | |
| A8 | | High Range | IO_L12N_T1_MRCC_16 | User IO | | 16 | | | | | | | | | | | | | |
| A9 | | High Range | IO_L14N_T2_SRCC_16 | User IO | | 16 | | | | | | | | | | | | | |
| A10 | | High Range | IO_L14P_T2_SRCC_16 | User IO | | 16 | | | | | | | | | | | | | |
| A11 | | High Range | IO_L4N_T0_15 | User IO | | 15 | | | | | | | | | | | | | |
| A12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| A13 | | High Range | IO_L9P_T1_DQS_AD3P_15 | User IO | | 15 | | | | | | | | | | | | | |
| A14 | | High Range | IO_L9N_T1_DQS_AD3N_15 | User IO | | 15 | | | | | | | | | | | | | |
| A15 | | High Range | IO_L8P_T1_AD10P_15 | User IO | | 15 | | | | | | | | | | | | | |
| A16 | | High Range | IO_L8N_T1_AD10N_15 | User IO | | 15 | | | | | | | | | | | | | |
| A17 | | High Range | VCCO_15 | VCCO | | 15 | | | | | any** | | | | | | | | |
| A18 | | High Range | IO_L10N_T1_AD11N_15 | User IO | | 15 | | | | | | | | | | | | | |
| B1 | | High Range | IO_L9P_T1_DQS_AD7P_35 | User IO | | 35 | | | | | | | | | | | | | |
| B2 | | High Range | IO_L10N_T1_AD15N_35 | User IO | | 35 | | | | | | | | | | | | | |
| B3 | | High Range | IO_L10P_T1_AD15P_35 | User IO | | 35 | | | | | | | | | | | | | |
| B4 | | High Range | IO_L7N_T1_AD6N_35 | User IO | | 35 | | | | | | | | | | | | | |
| B5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| B6 | | High Range | IO_L2N_T0_AD12N_35 | User IO | | 35 | | | | | | | | | | | | | |
| B7 | | High Range | IO_L2P_T0_AD12P_35 | User IO | | 35 | | | | | | | | | | | | | |
| B8 | | High Range | IO_L12P_T1_MRCC_16 | User IO | | 16 | | | | | | | | | | | | | |
| B9 | | High Range | IO_L11N_T1_SRCC_16 | User IO | | 16 | | | | | | | | | | | | | |
| B10 | | High Range | VCCO_16 | VCCO | | 16 | | | | | any** | | | | | | | | |
| B11 | | High Range | IO_L4P_T0_15 | User IO | | 15 | | | | | | | | | | | | | |
| B12 | | High Range | IO_L3N_T0_DQS_AD1N_15 | User IO | | 15 | | | | | | | | | | | | | |
| B13 | | High Range | IO_L2P_T0_AD8P_15 | User IO | | 15 | | | | | | | | | | | | | |
| B14 | | High Range | IO_L2N_T0_AD8N_15 | User IO | | 15 | | | | | | | | | | | | | |
| B15 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| B16 | | High Range | IO_L7P_T1_AD2P_15 | User IO | | 15 | | | | | | | | | | | | | |
| B17 | | High Range | IO_L7N_T1_AD2N_15 | User IO | | 15 | | | | | | | | | | | | | |
| B18 | | High Range | IO_L10P_T1_AD11P_15 | User IO | | 15 | | | | | | | | | | | | | |
| C1 | | High Range | IO_L16N_T2_35 | User IO | | 35 | | | | | | | | | | | | | |
| C2 | | High Range | IO_L16P_T2_35 | User IO | | 35 | | | | | | | | | | | | | |
| C3 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 3.30 | | | | | | | | |
| C4 | | High Range | IO_L7P_T1_AD6P_35 | User IO | | 35 | | | | | | | | | | | | | |
| C5 | | High Range | IO_L1N_T0_AD4N_35 | User IO | | 35 | | | | | | | | | | | | | |
| C6 | | High Range | IO_L1P_T0_AD4P_35 | User IO | | 35 | | | | | | | | | | | | | |
| C7 | | High Range | IO_L4N_T0_35 | User IO | | 35 | | | | | | | | | | | | | |
| C8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| C9 | | High Range | IO_L11P_T1_SRCC_16 | User IO | | 16 | | | | | | | | | | | | | |
| C10 | | High Range | IO_L13N_T2_MRCC_16 | User IO | | 16 | | | | | | | | | | | | | |
| C11 | | High Range | IO_L13P_T2_MRCC_16 | User IO | | 16 | | | | | | | | | | | | | |
| C12 | | High Range | IO_L3P_T0_DQS_AD1P_15 | User IO | | 15 | | | | | | | | | | | | | |
| C13 | | High Range | VCCO_15 | VCCO | | 15 | | | | | any** | | | | | | | | |
| C14 | | High Range | IO_L1N_T0_AD0N_15 | User IO | | 15 | | | | | | | | | | | | | |
| C15 | | High Range | IO_L12N_T1_MRCC_15 | User IO | | 15 | | | | | | | | | | | | | |
| C16 | | High Range | IO_L20P_T3_A20_15 | User IO | | 15 | | | | | | | | | | | | | |
| C17 | | High Range | IO_L20N_T3_A19_15 | User IO | | 15 | | | | | | | | | | | | | |
| C18 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| D1 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| D2 | seg[0] | High Range | IO_L14N_T2_SRCC_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| D3 | seg[4] | High Range | IO_L12N_T1_MRCC_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| D4 | seg[6] | High Range | IO_L11N_T1_SRCC_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| D5 | | High Range | IO_L11P_T1_SRCC_35 | User IO | | 35 | | | | | | | | | | | | | |
| D6 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 3.30 | | | | | | | | |
| D7 | | High Range | IO_L6N_T0_VREF_35 | User IO | | 35 | | | | | | | | | | | | | |
| D8 | | High Range | IO_L4P_T0_35 | User IO | | 35 | | | | | | | | | | | | | |
| D9 | | High Range | IO_L6N_T0_VREF_16 | User IO | | 16 | | | | | | | | | | | | | |
| D10 | | High Range | IO_L19N_T3_VREF_16 | User IO | | 16 | | | | | | | | | | | | | |
| D11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| D12 | | High Range | IO_L6P_T0_15 | User IO | | 15 | | | | | | | | | | | | | |
| D13 | | High Range | IO_L6N_T0_VREF_15 | User IO | | 15 | | | | | | | | | | | | | |
| D14 | | High Range | IO_L1P_T0_AD0P_15 | User IO | | 15 | | | | | | | | | | | | | |
| D15 | | High Range | IO_L12P_T1_MRCC_15 | User IO | | 15 | | | | | | | | | | | | | |
| D16 | | High Range | VCCO_15 | VCCO | | 15 | | | | | any** | | | | | | | | |
| D17 | | High Range | IO_L16N_T2_A27_15 | User IO | | 15 | | | | | | | | | | | | | |
| D18 | | High Range | IO_L21N_T3_DQS_A18_15 | User IO | | 15 | | | | | | | | | | | | | |
| E1 | seg_cs[1] | High Range | IO_L18N_T2_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| E2 | seg[1] | High Range | IO_L14P_T2_SRCC_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| E3 | seg[5] | High Range | IO_L12P_T1_MRCC_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| E4 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| E5 | | High Range | IO_L5N_T0_AD13N_35 | User IO | | 35 | | | | | | | | | | | | | |
| E6 | | High Range | IO_L5P_T0_AD13P_35 | User IO | | 35 | | | | | | | | | | | | | |
| E7 | | High Range | IO_L6P_T0_35 | User IO | | 35 | | | | | | | | | | | | | |
| E8 | | Dedicated | VCCBATT_0 | Config | | 0 | | | | | | | | | | | | | |
| E9 | | Dedicated | CCLK_0 | Config | | 0 | | | | | | | | | | | | | |
| E10 | | Dedicated | TCK_0 | Config | | 0 | | | | | | | | | | | | | |
| E11 | | Dedicated | TDI_0 | Config | | 0 | | | | | | | | | | | | | |
| E12 | | Dedicated | TMS_0 | Config | | 0 | | | | | | | | | | | | | |
| E13 | | Dedicated | TDO_0 | Config | | 0 | | | | | | | | | | | | | |
| E14 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| E15 | | High Range | IO_L11P_T1_SRCC_15 | User IO | | 15 | | | | | | | | | | | | | |
| E16 | | High Range | IO_L11N_T1_SRCC_15 | User IO | | 15 | | | | | | | | | | | | | |
| E17 | | High Range | IO_L16P_T2_A28_15 | User IO | | 15 | | | | | | | | | | | | | |
| E18 | | High Range | IO_L21P_T3_DQS_15 | User IO | | 15 | | | | | | | | | | | | | |
| F1 | seg_cs[2] | High Range | IO_L18P_T2_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| F2 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 3.30 | | | | | | | | |
| F3 | seg[2] | High Range | IO_L13N_T2_MRCC_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| F4 | seg[3] | High Range | IO_L13P_T2_MRCC_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| F5 | | High Range | IO_0_35 | User IO | | 35 | | | | | | | | | | | | | |
| F6 | result[4] | High Range | IO_L19N_T3_VREF_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| F7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| F8 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
| F9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| F10 | | | VCCBRAM | VCCBRAM | | | | | | | | | | | | | | | |
| F11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| F12 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | |
| F13 | | High Range | IO_L5P_T0_AD9P_15 | User IO | | 15 | | | | | | | | | | | | | |
| F14 | | High Range | IO_L5N_T0_AD9N_15 | User IO | | 15 | | | | | | | | | | | | | |
| F15 | | High Range | IO_L14P_T2_SRCC_15 | User IO | | 15 | | | | | | | | | | | | | |
| F16 | | High Range | IO_L14N_T2_SRCC_15 | User IO | | 15 | | | | | | | | | | | | | |
| F17 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| F18 | | High Range | IO_L22N_T3_A16_15 | User IO | | 15 | | | | | | | | | | | | | |
| G1 | seg_cs[3] | High Range | IO_L17N_T2_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| G2 | | High Range | IO_L15N_T2_DQS_35 | User IO | | 35 | | | | | | | | | | | | | |
| G3 | result[2] | High Range | IO_L20N_T3_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| G4 | result[3] | High Range | IO_L20P_T3_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| G5 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 3.30 | | | | | | | | |
| G6 | seg_cs[0] | High Range | IO_L19P_T3_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| G7 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
| G8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| G9 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
| G10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| G11 | | | VCCBRAM | VCCBRAM | | | | | | | | | | | | | | | |
| G12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| G13 | | High Range | IO_0_15 | User IO | | 15 | | | | | | | | | | | | | |
| G14 | | High Range | IO_L15N_T2_DQS_ADV_B_15 | User IO | | 15 | | | | | | | | | | | | | |
| G15 | | High Range | VCCO_15 | VCCO | | 15 | | | | | any** | | | | | | | | |
| G16 | | High Range | IO_L13N_T2_MRCC_15 | User IO | | 15 | | | | | | | | | | | | | |
| G17 | | High Range | IO_L18N_T2_A23_15 | User IO | | 15 | | | | | | | | | | | | | |
| G18 | | High Range | IO_L22P_T3_A17_15 | User IO | | 15 | | | | | | | | | | | | | |
| H1 | | High Range | IO_L17P_T2_35 | User IO | | 35 | | | | | | | | | | | | | |
| H2 | | High Range | IO_L15P_T2_DQS_35 | User IO | | 35 | | | | | | | | | | | | | |
| H3 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| H4 | result[0] | High Range | IO_L21N_T3_DQS_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| H5 | | High Range | IO_L24N_T3_35 | User IO | | 35 | | | | | | | | | | | | | |
| H6 | | High Range | IO_L24P_T3_35 | User IO | | 35 | | | | | | | | | | | | | |
| H7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| H8 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
| H9 | | Dedicated | GNDADC_0 | XADC | | 0 | | | | | | | | | | | | | |
| H10 | | Dedicated | VCCADC_0 | XADC | | 0 | | | | | | | | | | | | | |
| H11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| H12 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | |
| H13 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| H14 | | High Range | IO_L15P_T2_DQS_15 | User IO | | 15 | | | | | | | | | | | | | |
| H15 | | High Range | IO_L19N_T3_A21_VREF_15 | User IO | | 15 | | | | | | | | | | | | | |
| H16 | | High Range | IO_L13P_T2_MRCC_15 | User IO | | 15 | | | | | | | | | | | | | |
| H17 | | High Range | IO_L18P_T2_A24_15 | User IO | | 15 | | | | | | | | | | | | | |
| H18 | | High Range | VCCO_15 | VCCO | | 15 | | | | | any** | | | | | | | | |
| J1 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 3.30 | | | | | | | | |
| J2 | | High Range | IO_L22N_T3_35 | User IO | | 35 | | | | | | | | | | | | | |
| J3 | | High Range | IO_L22P_T3_35 | User IO | | 35 | | | | | | | | | | | | | |
| J4 | result[1] | High Range | IO_L21P_T3_DQS_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| J5 | | High Range | IO_25_35 | User IO | | 35 | | | | | | | | | | | | | |
| J6 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| J7 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
| J8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| J9 | | Dedicated | VREFN_0 | XADC | | 0 | | | | | | | | | | | | | |
| J10 | | Dedicated | VP_0 | XADC | | 0 | | | | | | | | | | | | | |
| J11 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
| J12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| J13 | | High Range | IO_L17N_T2_A25_15 | User IO | | 15 | | | | | | | | | | | | | |
| J14 | | High Range | IO_L19P_T3_A22_15 | User IO | | 15 | | | | | | | | | | | | | |
| J15 | | High Range | IO_L24N_T3_RS0_15 | User IO | | 15 | | | | | | | | | | | | | |
| J16 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| J17 | | High Range | IO_L23P_T3_FOE_B_15 | User IO | | 15 | | | | | | | | | | | | | |
| J18 | | High Range | IO_L23N_T3_FWE_B_15 | User IO | | 15 | | | | | | | | | | | | | |
| K1 | | High Range | IO_L23N_T3_35 | User IO | | 35 | | | | | | | | | | | | | |
| K2 | | High Range | IO_L23P_T3_35 | User IO | | 35 | | | | | | | | | | | | | |
| K3 | | High Range | IO_L2P_T0_34 | User IO | | 34 | | | | | | | | | | | | | |
| K4 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 3.30 | | | | | | | | |
| K5 | | High Range | IO_L5P_T0_34 | User IO | | 34 | | | | | | | | | | | | | |
| K6 | | High Range | IO_0_34 | User IO | | 34 | | | | | | | | | | | | | |
| K7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| K8 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
| K9 | | Dedicated | VN_0 | XADC | | 0 | | | | | | | | | | | | | |
| K10 | | Dedicated | VREFP_0 | XADC | | 0 | | | | | | | | | | | | | |
| K11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| K12 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | |
| K13 | | High Range | IO_L17P_T2_A26_15 | User IO | | 15 | | | | | | | | | | | | | |
| K14 | | High Range | VCCO_15 | VCCO | | 15 | | | | | any** | | | | | | | | |
| K15 | | High Range | IO_L24P_T3_RS1_15 | User IO | | 15 | | | | | | | | | | | | | |
| K16 | | High Range | IO_25_15 | User IO | | 15 | | | | | | | | | | | | | |
| K17 | | High Range | IO_L1P_T0_D00_MOSI_14 | User IO | | 14 | | | | | | | | | | | | | |
| K18 | | High Range | IO_L1N_T0_D01_DIN_14 | User IO | | 14 | | | | | | | | | | | | | |
| L1 | | High Range | IO_L1P_T0_34 | User IO | | 34 | | | | | | | | | | | | | |
| L2 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| L3 | | High Range | IO_L2N_T0_34 | User IO | | 34 | | | | | | | | | | | | | |
| L4 | | High Range | IO_L5N_T0_34 | User IO | | 34 | | | | | | | | | | | | | |
| L5 | | High Range | IO_L6N_T0_VREF_34 | User IO | | 34 | | | | | | | | | | | | | |
| L6 | | High Range | IO_L6P_T0_34 | User IO | | 34 | | | | | | | | | | | | | |
| L7 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
| L8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| L9 | | Dedicated | DXN_0 | Temp Sensor | | 0 | | | | | | | | | | | | | |
| L10 | | Dedicated | DXP_0 | Temp Sensor | | 0 | | | | | | | | | | | | | |
| L11 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
| L12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| L13 | | High Range | IO_L6P_T0_FCS_B_14 | User IO | | 14 | | | | | | | | | | | | | |
| L14 | | High Range | IO_L2P_T0_D02_14 | User IO | | 14 | | | | | | | | | | | | | |
| L15 | | High Range | IO_L3P_T0_DQS_PUDC_B_14 | User IO | | 14 | | | | | | | | | | | | | |
| L16 | | High Range | IO_L3N_T0_DQS_EMCCLK_14 | User IO | | 14 | | | | | | | | | | | | | |
| L17 | | High Range | VCCO_14 | VCCO | | 14 | | | | | 3.30 | | | | | | | | |
| L18 | | High Range | IO_L4P_T0_D04_14 | User IO | | 14 | | | | | | | | | | | | | |
| M1 | | High Range | IO_L1N_T0_34 | User IO | | 34 | | | | | | | | | | | | | |
| M2 | | High Range | IO_L4N_T0_34 | User IO | | 34 | | | | | | | | | | | | | |
| M3 | | High Range | IO_L4P_T0_34 | User IO | | 34 | | | | | | | | | | | | | |
| M4 | data2[2] | High Range | IO_L16P_T2_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | |
| M5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| M6 | | High Range | IO_L18P_T2_34 | User IO | | 34 | | | | | | | | | | | | | |
| M7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| M8 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
| M9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| M10 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
| M11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| M12 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | |
| M13 | | High Range | IO_L6N_T0_D08_VREF_14 | User IO | | 14 | | | | | | | | | | | | | |
| M14 | | High Range | IO_L2N_T0_D03_14 | User IO | | 14 | | | | | | | | | | | | | |
| M15 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| M16 | | High Range | IO_L10P_T1_D14_14 | User IO | | 14 | | | | | | | | | | | | | |
| M17 | | High Range | IO_L10N_T1_D15_14 | User IO | | 14 | | | | | | | | | | | | | |
| M18 | | High Range | IO_L4N_T0_D05_14 | User IO | | 14 | | | | | | | | | | | | | |
| N1 | | High Range | IO_L3N_T0_DQS_34 | User IO | | 34 | | | | | | | | | | | | | |
| N2 | | High Range | IO_L3P_T0_DQS_34 | User IO | | 34 | | | | | | | | | | | | | |
| N3 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 3.30 | | | | | | | | |
| N4 | data2[1] | High Range | IO_L16N_T2_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | |
| N5 | | High Range | IO_L13P_T2_MRCC_34 | User IO | | 34 | | | | | | | | | | | | | |
| N6 | | High Range | IO_L18N_T2_34 | User IO | | 34 | | | | | | | | | | | | | |
| N7 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
| N8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| N9 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
| N10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| N11 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
| N12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| N13 | | High Range | VCCO_14 | VCCO | | 14 | | | | | 3.30 | | | | | | | | |
| N14 | | High Range | IO_L8P_T1_D11_14 | User IO | | 14 | | | | | | | | | | | | | |
| N15 | | High Range | IO_L11P_T1_SRCC_14 | User IO | | 14 | | | | | | | | | | | | | |
| N16 | | High Range | IO_L11N_T1_SRCC_14 | User IO | | 14 | | | | | | | | | | | | | |
| N17 | | High Range | IO_L9P_T1_DQS_14 | User IO | | 14 | | | | | | | | | | | | | |
| N18 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| P1 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| P2 | data1[0] | High Range | IO_L15P_T2_DQS_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | |
| P3 | data1[1] | High Range | IO_L14N_T2_SRCC_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | |
| P4 | data1[2] | High Range | IO_L14P_T2_SRCC_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | |
| P5 | data1[3] | High Range | IO_L13N_T2_MRCC_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | |
| P6 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 3.30 | | | | | | | | |
| P7 | | Dedicated | INIT_B_0 | Config | | 0 | | | | | | | | | | | | | |
| P8 | | Dedicated | CFGBVS_0 | Config | | 0 | | | | | | | | | | | | | |
| P9 | | Dedicated | PROGRAM_B_0 | Config | | 0 | | | | | | | | | | | | | |
| P10 | | Dedicated | DONE_0 | Config | | 0 | | | | | | | | | | | | | |
| P11 | | Dedicated | M2_0 | Config | | 0 | | | | | | | | | | | | | |
| P12 | | Dedicated | M0_0 | Config | | 0 | | | | | | | | | | | | | |
| P13 | | Dedicated | M1_0 | Config | | 0 | | | | | | | | | | | | | |
| P14 | | High Range | IO_L8N_T1_D12_14 | User IO | | 14 | | | | | | | | | | | | | |
| P15 | | High Range | IO_L13P_T2_MRCC_14 | User IO | | 14 | | | | | | | | | | | | | |
| P16 | | High Range | VCCO_14 | VCCO | | 14 | | | | | 3.30 | | | | | | | | |
| P17 | clk | High Range | IO_L12P_T1_MRCC_14 | INPUT | LVCMOS33 | 14 | | | | NONE | | FIXED | | | | NONE | | | |
| P18 | | High Range | IO_L9N_T1_DQS_D13_14 | User IO | | 14 | | | | | | | | | | | | | |
| R1 | data2[0] | High Range | IO_L17P_T2_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | |
| R2 | data2[3] | High Range | IO_L15N_T2_DQS_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | |
| R3 | | High Range | IO_L11P_T1_SRCC_34 | User IO | | 34 | | | | | | | | | | | | | |
| R4 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| R5 | | High Range | IO_L19N_T3_VREF_34 | User IO | | 34 | | | | | | | | | | | | | |
| R6 | | High Range | IO_L19P_T3_34 | User IO | | 34 | | | | | | | | | | | | | |
| R7 | | High Range | IO_L23P_T3_34 | User IO | | 34 | | | | | | | | | | | | | |
| R8 | | High Range | IO_L24P_T3_34 | User IO | | 34 | | | | | | | | | | | | | |
| R9 | | Dedicated | VCCO_0 | VCCO | | 0 | | | | | any** | | | | | | | | |
| R10 | | High Range | IO_25_14 | User IO | | 14 | | | | | | | | | | | | | |
| R11 | type[1] | High Range | IO_0_14 | INPUT | LVCMOS33 | 14 | | | | NONE | | FIXED | | | | NONE | | | |
| R12 | | High Range | IO_L5P_T0_D06_14 | User IO | | 14 | | | | | | | | | | | | | |
| R13 | | High Range | IO_L5N_T0_D07_14 | User IO | | 14 | | | | | | | | | | | | | |
| R14 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| R15 | type[2] | High Range | IO_L13N_T2_MRCC_14 | INPUT | LVCMOS33 | 14 | | | | NONE | | FIXED | | | | NONE | | | |
| R16 | | High Range | IO_L15P_T2_DQS_RDWR_B_14 | User IO | | 14 | | | | | | | | | | | | | |
| R17 | type[0] | High Range | IO_L12N_T1_MRCC_14 | INPUT | LVCMOS33 | 14 | | | | NONE | | FIXED | | | | NONE | | | |
| R18 | | High Range | IO_L7P_T1_D09_14 | User IO | | 14 | | | | | | | | | | | | | |
| T1 | | High Range | IO_L17N_T2_34 | User IO | | 34 | | | | | | | | | | | | | |
| T2 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 3.30 | | | | | | | | |
| T3 | | High Range | IO_L11N_T1_SRCC_34 | User IO | | 34 | | | | | | | | | | | | | |
| T4 | | High Range | IO_L12N_T1_MRCC_34 | User IO | | 34 | | | | | | | | | | | | | |
| T5 | | High Range | IO_L12P_T1_MRCC_34 | User IO | | 34 | | | | | | | | | | | | | |
| T6 | | High Range | IO_L23N_T3_34 | User IO | | 34 | | | | | | | | | | | | | |
| T7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| T8 | | High Range | IO_L24N_T3_34 | User IO | | 34 | | | | | | | | | | | | | |
| T9 | | High Range | IO_L24P_T3_A01_D17_14 | User IO | | 14 | | | | | | | | | | | | | |
| T10 | | High Range | IO_L24N_T3_A00_D16_14 | User IO | | 14 | | | | | | | | | | | | | |
| T11 | | High Range | IO_L19P_T3_A10_D26_14 | User IO | | 14 | | | | | | | | | | | | | |
| T12 | | High Range | VCCO_14 | VCCO | | 14 | | | | | 3.30 | | | | | | | | |
| T13 | | High Range | IO_L23P_T3_A03_D19_14 | User IO | | 14 | | | | | | | | | | | | | |
| T14 | | High Range | IO_L14P_T2_SRCC_14 | User IO | | 14 | | | | | | | | | | | | | |
| T15 | | High Range | IO_L14N_T2_SRCC_14 | User IO | | 14 | | | | | | | | | | | | | |
| T16 | | High Range | IO_L15N_T2_DQS_DOUT_CSO_B_14 | User IO | | 14 | | | | | | | | | | | | | |
| T17 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| T18 | | High Range | IO_L7N_T1_D10_14 | User IO | | 14 | | | | | | | | | | | | | |
| U1 | | High Range | IO_L7P_T1_34 | User IO | | 34 | | | | | | | | | | | | | |
| U2 | | High Range | IO_L9P_T1_DQS_34 | User IO | | 34 | | | | | | | | | | | | | |
| U3 | | High Range | IO_L8N_T1_34 | User IO | | 34 | | | | | | | | | | | | | |
| U4 | type[4] | High Range | IO_L8P_T1_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | |
| U5 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 3.30 | | | | | | | | |
| U6 | | High Range | IO_L22N_T3_34 | User IO | | 34 | | | | | | | | | | | | | |
| U7 | | High Range | IO_L22P_T3_34 | User IO | | 34 | | | | | | | | | | | | | |
| U8 | | High Range | IO_25_34 | User IO | | 34 | | | | | | | | | | | | | |
| U9 | | High Range | IO_L21P_T3_DQS_34 | User IO | | 34 | | | | | | | | | | | | | |
| U10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| U11 | | High Range | IO_L19N_T3_A09_D25_VREF_14 | User IO | | 14 | | | | | | | | | | | | | |
| U12 | | High Range | IO_L20P_T3_A08_D24_14 | User IO | | 14 | | | | | | | | | | | | | |
| U13 | | High Range | IO_L23N_T3_A02_D18_14 | User IO | | 14 | | | | | | | | | | | | | |
| U14 | | High Range | IO_L22P_T3_A05_D21_14 | User IO | | 14 | | | | | | | | | | | | | |
| U15 | | High Range | VCCO_14 | VCCO | | 14 | | | | | 3.30 | | | | | | | | |
| U16 | | High Range | IO_L18P_T2_A12_D28_14 | User IO | | 14 | | | | | | | | | | | | | |
| U17 | | High Range | IO_L17P_T2_A14_D30_14 | User IO | | 14 | | | | | | | | | | | | | |
| U18 | | High Range | IO_L17N_T2_A13_D29_14 | User IO | | 14 | | | | | | | | | | | | | |
| V1 | type[3] | High Range | IO_L7N_T1_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | |
| V2 | | High Range | IO_L9N_T1_DQS_34 | User IO | | 34 | | | | | | | | | | | | | |
| V3 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| V4 | | High Range | IO_L10N_T1_34 | User IO | | 34 | | | | | | | | | | | | | |
| V5 | | High Range | IO_L10P_T1_34 | User IO | | 34 | | | | | | | | | | | | | |
| V6 | | High Range | IO_L20N_T3_34 | User IO | | 34 | | | | | | | | | | | | | |
| V7 | | High Range | IO_L20P_T3_34 | User IO | | 34 | | | | | | | | | | | | | |
| V8 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 3.30 | | | | | | | | |
| V9 | | High Range | IO_L21N_T3_DQS_34 | User IO | | 34 | | | | | | | | | | | | | |
| V10 | | High Range | IO_L21P_T3_DQS_14 | User IO | | 14 | | | | | | | | | | | | | |
| V11 | | High Range | IO_L21N_T3_DQS_A06_D22_14 | User IO | | 14 | | | | | | | | | | | | | |
| V12 | | High Range | IO_L20N_T3_A07_D23_14 | User IO | | 14 | | | | | | | | | | | | | |
| V13 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| V14 | | High Range | IO_L22N_T3_A04_D20_14 | User IO | | 14 | | | | | | | | | | | | | |
| V15 | | High Range | IO_L16P_T2_CSI_B_14 | User IO | | 14 | | | | | | | | | | | | | |
| V16 | | High Range | IO_L16N_T2_A15_D31_14 | User IO | | 14 | | | | | | | | | | | | | |
| V17 | | High Range | IO_L18N_T2_A11_D27_14 | User IO | | 14 | | | | | | | | | | | | | |
| V18 | | High Range | VCCO_14 | VCCO | | 14 | | | | | 3.30 | | | | | | | | |
+------------+-------------+------------+------------------------------+-------------+-------------+---------+------------+------+---------------------+----------------------+---------+------------+-----------+----------+------+------------------+--------------+-------------------+--------------+
* Default value
** Special VCCO requirements may apply. Please consult the device family datasheet for specific guideline on VCCO requirements.

BIN
Exp4/Exp4.runs/impl_1/calc_methodology_drc_routed.pb Normal file
View File

Binary file not shown.

82
Exp4/Exp4.runs/impl_1/calc_methodology_drc_routed.rpt Normal file
View File

@@ -0,0 +1,82 @@
Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
--------------------------------------------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2018.1 (win64) Build 2188600 Wed Apr 4 18:40:38 MDT 2018
| Date : Thu Nov 7 02:29:17 2024
| Host : W10-20240912132 running 64-bit major release (build 9200)
| Command : report_methodology -file calc_methodology_drc_routed.rpt -pb calc_methodology_drc_routed.pb -rpx calc_methodology_drc_routed.rpx
| Design : calc
| Device : xc7a35tcsg324-1
| Speed File : -1
| Design State : Routed
--------------------------------------------------------------------------------------------------------------------------------------------------
Report Methodology
Table of Contents
-----------------
1. REPORT SUMMARY
2. REPORT DETAILS
1. REPORT SUMMARY
-----------------
Netlist: netlist
Floorplan: design_1
Design limits: <entire design considered>
Max violations: <unlimited>
Violations found: 9
+-----------+----------+------------------------------+------------+
| Rule | Severity | Description | Violations |
+-----------+----------+------------------------------+------------+
| LUTAR-1 | Warning | LUT drives async reset alert | 1 |
| TIMING-17 | Warning | Non-clocked sequential cell | 5 |
| TIMING-20 | Warning | Non-clocked latch | 3 |
+-----------+----------+------------------------------+------------+
2. REPORT DETAILS
-----------------
LUTAR-1#1 Warning
LUT drives async reset alert
LUT cell run/result_reg[1]_i_1, with 2 or more inputs, drives asynchronous reset pin(s) run/result_reg[1]/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.
Related violations: <none>
TIMING-17#1 Warning
Non-clocked sequential cell
The clock pin stored_type_reg[0]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#2 Warning
Non-clocked sequential cell
The clock pin stored_type_reg[1]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#3 Warning
Non-clocked sequential cell
The clock pin stored_type_reg[2]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#4 Warning
Non-clocked sequential cell
The clock pin stored_type_reg[3]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#5 Warning
Non-clocked sequential cell
The clock pin stored_type_reg[4]/C is not reached by a timing clock
Related violations: <none>
TIMING-20#1 Warning
Non-clocked latch
The latch run/result_reg[1] cannot be properly analyzed as its control pin run/result_reg[1]/G is not reached by a timing clock
Related violations: <none>
TIMING-20#2 Warning
Non-clocked latch
The latch run/result_reg[2]/L7 (in run/result_reg[2] macro) cannot be properly analyzed as its control pin run/result_reg[2]/L7/G is not reached by a timing clock
Related violations: <none>
TIMING-20#3 Warning
Non-clocked latch
The latch run/result_reg[3]/L7 (in run/result_reg[3] macro) cannot be properly analyzed as its control pin run/result_reg[3]/L7/G is not reached by a timing clock
Related violations: <none>

BIN
Exp4/Exp4.runs/impl_1/calc_opt.dcp Normal file
View File

Binary file not shown.

BIN
Exp4/Exp4.runs/impl_1/calc_placed.dcp Normal file
View File

Binary file not shown.

146
Exp4/Exp4.runs/impl_1/calc_power_routed.rpt Normal file
View File

@@ -0,0 +1,146 @@
Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
----------------------------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2018.1 (win64) Build 2188600 Wed Apr 4 18:40:38 MDT 2018
| Date : Thu Nov 7 02:29:17 2024
| Host : W10-20240912132 running 64-bit major release (build 9200)
| Command : report_power -file calc_power_routed.rpt -pb calc_power_summary_routed.pb -rpx calc_power_routed.rpx
| Design : calc
| Device : xc7a35tcsg324-1
| Design State : routed
| Grade : commercial
| Process : typical
| Characterization : Production
----------------------------------------------------------------------------------------------------------------------------------
Power Report
Table of Contents
-----------------
1. Summary
1.1 On-Chip Components
1.2 Power Supply Summary
1.3 Confidence Level
2. Settings
2.1 Environment
2.2 Clock Constraints
3. Detailed Reports
3.1 By Hierarchy
1. Summary
----------
+--------------------------+--------------+
| Total On-Chip Power (W) | 7.595 |
| Design Power Budget (W) | Unspecified* |
| Power Budget Margin (W) | NA |
| Dynamic (W) | 7.488 |
| Device Static (W) | 0.107 |
| Effective TJA (C/W) | 4.8 |
| Max Ambient (C) | 48.7 |
| Junction Temperature (C) | 61.3 |
| Confidence Level | Low |
| Setting File | --- |
| Simulation Activity File | --- |
| Design Nets Matched | NA |
+--------------------------+--------------+
* Specify Design Power Budget using, set_operating_conditions -design_power_budget <value in Watts>
1.1 On-Chip Components
----------------------
+----------------+-----------+----------+-----------+-----------------+
| On-Chip | Power (W) | Used | Available | Utilization (%) |
+----------------+-----------+----------+-----------+-----------------+
| Slice Logic | 0.133 | 54 | --- | --- |
| LUT as Logic | 0.126 | 32 | 20800 | 0.15 |
| BUFG | 0.006 | 1 | 32 | 3.13 |
| Register | 0.001 | 8 | 41600 | 0.02 |
| Others | 0.000 | 8 | --- | --- |
| Signals | 0.248 | 58 | --- | --- |
| I/O | 7.107 | 30 | 210 | 14.29 |
| Static Power | 0.107 | | | |
| Total | 7.595 | | | |
+----------------+-----------+----------+-----------+-----------------+
1.2 Power Supply Summary
------------------------
+-----------+-------------+-----------+-------------+------------+
| Source | Voltage (V) | Total (A) | Dynamic (A) | Static (A) |
+-----------+-------------+-----------+-------------+------------+
| Vccint | 1.000 | 0.475 | 0.437 | 0.039 |
| Vccaux | 1.800 | 0.274 | 0.258 | 0.016 |
| Vcco33 | 3.300 | 1.997 | 1.996 | 0.001 |
| Vcco25 | 2.500 | 0.000 | 0.000 | 0.000 |
| Vcco18 | 1.800 | 0.000 | 0.000 | 0.000 |
| Vcco15 | 1.500 | 0.000 | 0.000 | 0.000 |
| Vcco135 | 1.350 | 0.000 | 0.000 | 0.000 |
| Vcco12 | 1.200 | 0.000 | 0.000 | 0.000 |
| Vccaux_io | 1.800 | 0.000 | 0.000 | 0.000 |
| Vccbram | 1.000 | 0.001 | 0.000 | 0.001 |
| MGTAVcc | 1.000 | 0.000 | 0.000 | 0.000 |
| MGTAVtt | 1.200 | 0.000 | 0.000 | 0.000 |
| Vccadc | 1.800 | 0.020 | 0.000 | 0.020 |
+-----------+-------------+-----------+-------------+------------+
1.3 Confidence Level
--------------------
+-----------------------------+------------+--------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------+
| User Input Data | Confidence | Details | Action |
+-----------------------------+------------+--------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------+
| Design implementation state | High | Design is routed | |
| Clock nodes activity | Low | User specified less than 75% of clocks | Provide missing clock activity with a constraint file, simulation results or by editing the "By Clock Domain" view |
| I/O nodes activity | Low | More than 75% of inputs are missing user specification | Provide missing input activity with simulation results or by editing the "By Resource Type -> I/Os" view |
| Internal nodes activity | Medium | User specified less than 25% of internal nodes | Provide missing internal nodes activity with simulation results or by editing the "By Resource Type" views |
| Device models | High | Device models are Production | |
| | | | |
| Overall confidence level | Low | | |
+-----------------------------+------------+--------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------+
2. Settings
-----------
2.1 Environment
---------------
+-----------------------+--------------------------+
| Ambient Temp (C) | 25.0 |
| ThetaJA (C/W) | 4.8 |
| Airflow (LFM) | 250 |
| Heat Sink | medium (Medium Profile) |
| ThetaSA (C/W) | 4.6 |
| Board Selection | medium (10"x10") |
| # of Board Layers | 12to15 (12 to 15 Layers) |
| Board Temperature (C) | 25.0 |
+-----------------------+--------------------------+
2.2 Clock Constraints
---------------------
+-------+--------+-----------------+
| Clock | Domain | Constraint (ns) |
+-------+--------+-----------------+
3. Detailed Reports
-------------------
3.1 By Hierarchy
----------------
+-------------------+-----------+
| Name | Power (W) |
+-------------------+-----------+
| calc | 7.488 |
| run | 0.116 |
| result_reg[2] | 0.012 |
| result_reg[3] | 0.012 |
+-------------------+-----------+

BIN
Exp4/Exp4.runs/impl_1/calc_power_summary_routed.pb Normal file
View File

Binary file not shown.

BIN
Exp4/Exp4.runs/impl_1/calc_route_status.pb Normal file
View File

Binary file not shown.

11
Exp4/Exp4.runs/impl_1/calc_route_status.rpt Normal file
View File

@@ -0,0 +1,11 @@
Design Route Status
: # nets :
------------------------------------------- : ----------- :
# of logical nets.......................... : 92 :
# of nets not needing routing.......... : 32 :
# of internally routed nets........ : 32 :
# of routable nets..................... : 60 :
# of fully routed nets............. : 60 :
# of nets with routing errors.......... : 0 :
------------------------------------------- : ----------- :

BIN
Exp4/Exp4.runs/impl_1/calc_routed.dcp Normal file
View File

Binary file not shown.

2
Exp4/Exp4.runs/impl_1/calc_timing_summary_routed.pb Normal file
View File

@@ -0,0 +1,2 @@
2012.4’)Timing analysis from Implemented netlist.

189
Exp4/Exp4.runs/impl_1/calc_timing_summary_routed.rpt Normal file
View File

@@ -0,0 +1,189 @@
Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2018.1 (win64) Build 2188600 Wed Apr 4 18:40:38 MDT 2018
| Date : Thu Nov 7 02:29:17 2024
| Host : W10-20240912132 running 64-bit major release (build 9200)
| Command : report_timing_summary -max_paths 10 -file calc_timing_summary_routed.rpt -pb calc_timing_summary_routed.pb -rpx calc_timing_summary_routed.rpx -warn_on_violation
| Design : calc
| Device : 7a35t-csg324
| Speed File : -1 PRODUCTION 1.21 2018-02-08
-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
Timing Summary Report
------------------------------------------------------------------------------------------------
| Timer Settings
| --------------
------------------------------------------------------------------------------------------------
Enable Multi Corner Analysis : Yes
Enable Pessimism Removal : Yes
Pessimism Removal Resolution : Nearest Common Node
Enable Input Delay Default Clock : No
Enable Preset / Clear Arcs : No
Disable Flight Delays : No
Ignore I/O Paths : No
Timing Early Launch at Borrowing Latches : false
Corner Analyze Analyze
Name Max Paths Min Paths
------ --------- ---------
Slow Yes Yes
Fast Yes Yes
check_timing report
Table of Contents
-----------------
1. checking no_clock
2. checking constant_clock
3. checking pulse_width_clock
4. checking unconstrained_internal_endpoints
5. checking no_input_delay
6. checking no_output_delay
7. checking multiple_clock
8. checking generated_clocks
9. checking loops
10. checking partial_input_delay
11. checking partial_output_delay
12. checking latch_loops
1. checking no_clock
--------------------
There are 5 register/latch pins with no clock driven by root clock pin: clk (HIGH)
There are 3 register/latch pins with no clock driven by root clock pin: data1[0] (HIGH)
There are 3 register/latch pins with no clock driven by root clock pin: data1[1] (HIGH)
There are 3 register/latch pins with no clock driven by root clock pin: data1[2] (HIGH)
There are 3 register/latch pins with no clock driven by root clock pin: data1[3] (HIGH)
There are 3 register/latch pins with no clock driven by root clock pin: data2[0] (HIGH)
There are 3 register/latch pins with no clock driven by root clock pin: data2[1] (HIGH)
There are 3 register/latch pins with no clock driven by root clock pin: data2[2] (HIGH)
There are 3 register/latch pins with no clock driven by root clock pin: data2[3] (HIGH)
2. checking constant_clock
--------------------------
There are 0 register/latch pins with constant_clock.
3. checking pulse_width_clock
-----------------------------
There are 0 register/latch pins which need pulse_width check
4. checking unconstrained_internal_endpoints
--------------------------------------------
There are 13 pins that are not constrained for maximum delay. (HIGH)
There are 0 pins that are not constrained for maximum delay due to constant clock.
5. checking no_input_delay
--------------------------
There are 13 input ports with no input delay specified. (HIGH)
There are 0 input ports with no input delay but user has a false path constraint.
6. checking no_output_delay
---------------------------
There are 13 ports with no output delay specified. (HIGH)
There are 0 ports with no output delay but user has a false path constraint
There are 0 ports with no output delay but with a timing clock defined on it or propagating through it
7. checking multiple_clock
--------------------------
There are 0 register/latch pins with multiple clocks.
8. checking generated_clocks
----------------------------
There are 0 generated clocks that are not connected to a clock source.
9. checking loops
-----------------
There are 0 combinational loops in the design.
10. checking partial_input_delay
--------------------------------
There are 0 input ports with partial input delay specified.
11. checking partial_output_delay
---------------------------------
There are 0 ports with partial output delay specified.
12. checking latch_loops
------------------------
There are 0 combinational latch loops in the design through latch input
------------------------------------------------------------------------------------------------
| Design Timing Summary
| ---------------------
------------------------------------------------------------------------------------------------
WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints
------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- --------------------
NA NA NA NA NA NA NA NA NA NA NA NA
There are no user specified timing constraints.
------------------------------------------------------------------------------------------------
| Clock Summary
| -------------
------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------
| Intra Clock Table
| -----------------
------------------------------------------------------------------------------------------------
Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints
----- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- --------------------
------------------------------------------------------------------------------------------------
| Inter Clock Table
| -----------------
------------------------------------------------------------------------------------------------
From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints
---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- -------------------
------------------------------------------------------------------------------------------------
| Other Path Groups Table
| -----------------------
------------------------------------------------------------------------------------------------
Path Group From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints
---------- ---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- -------------------
------------------------------------------------------------------------------------------------
| Timing Details
| --------------
------------------------------------------------------------------------------------------------

BIN
Exp4/Exp4.runs/impl_1/calc_utilization_placed.pb Normal file
View File

Binary file not shown.

204
Exp4/Exp4.runs/impl_1/calc_utilization_placed.rpt Normal file
View File

@@ -0,0 +1,204 @@
Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
-----------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2018.1 (win64) Build 2188600 Wed Apr 4 18:40:38 MDT 2018
| Date : Thu Nov 7 02:29:04 2024
| Host : W10-20240912132 running 64-bit major release (build 9200)
| Command : report_utilization -file calc_utilization_placed.rpt -pb calc_utilization_placed.pb
| Design : calc
| Device : 7a35tcsg324-1
| Design State : Fully Placed
-----------------------------------------------------------------------------------------------------
Utilization Design Information
Table of Contents
-----------------
1. Slice Logic
1.1 Summary of Registers by Type
2. Slice Logic Distribution
3. Memory
4. DSP
5. IO and GT Specific
6. Clocking
7. Specific Feature
8. Primitives
9. Black Boxes
10. Instantiated Netlists
1. Slice Logic
--------------
+-------------------------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+-------------------------+------+-------+-----------+-------+
| Slice LUTs | 32 | 0 | 20800 | 0.15 |
| LUT as Logic | 32 | 0 | 20800 | 0.15 |
| LUT as Memory | 0 | 0 | 9600 | 0.00 |
| Slice Registers | 8 | 0 | 41600 | 0.02 |
| Register as Flip Flop | 5 | 0 | 41600 | 0.01 |
| Register as Latch | 3 | 0 | 41600 | <0.01 |
| F7 Muxes | 0 | 0 | 16300 | 0.00 |
| F8 Muxes | 0 | 0 | 8150 | 0.00 |
+-------------------------+------+-------+-----------+-------+
1.1 Summary of Registers by Type
--------------------------------
+-------+--------------+-------------+--------------+
| Total | Clock Enable | Synchronous | Asynchronous |
+-------+--------------+-------------+--------------+
| 2 | _ | - | - |
| 0 | _ | - | Set |
| 0 | _ | - | Reset |
| 0 | _ | Set | - |
| 0 | _ | Reset | - |
| 0 | Yes | - | - |
| 0 | Yes | - | Set |
| 1 | Yes | - | Reset |
| 0 | Yes | Set | - |
| 5 | Yes | Reset | - |
+-------+--------------+-------------+--------------+
2. Slice Logic Distribution
---------------------------
+-------------------------------------------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+-------------------------------------------+------+-------+-----------+-------+
| Slice | 12 | 0 | 8150 | 0.15 |
| SLICEL | 8 | 0 | | |
| SLICEM | 4 | 0 | | |
| LUT as Logic | 32 | 0 | 20800 | 0.15 |
| using O5 output only | 0 | | | |
| using O6 output only | 27 | | | |
| using O5 and O6 | 5 | | | |
| LUT as Memory | 0 | 0 | 9600 | 0.00 |
| LUT as Distributed RAM | 0 | 0 | | |
| LUT as Shift Register | 0 | 0 | | |
| LUT Flip Flop Pairs | 2 | 0 | 20800 | <0.01 |
| fully used LUT-FF pairs | 0 | | | |
| LUT-FF pairs with one unused LUT output | 1 | | | |
| LUT-FF pairs with one unused Flip Flop | 2 | | | |
| Unique Control Sets | 4 | | | |
+-------------------------------------------+------+-------+-----------+-------+
* Note: Review the Control Sets Report for more information regarding control sets.
3. Memory
---------
+----------------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+----------------+------+-------+-----------+-------+
| Block RAM Tile | 0 | 0 | 50 | 0.00 |
| RAMB36/FIFO* | 0 | 0 | 50 | 0.00 |
| RAMB18 | 0 | 0 | 100 | 0.00 |
+----------------+------+-------+-----------+-------+
* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1
4. DSP
------
+-----------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+-----------+------+-------+-----------+-------+
| DSPs | 0 | 0 | 90 | 0.00 |
+-----------+------+-------+-----------+-------+
5. IO and GT Specific
---------------------
+-----------------------------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+-----------------------------+------+-------+-----------+-------+
| Bonded IOB | 30 | 30 | 210 | 14.29 |
| IOB Master Pads | 13 | | | |
| IOB Slave Pads | 16 | | | |
| Bonded IPADs | 0 | 0 | 2 | 0.00 |
| PHY_CONTROL | 0 | 0 | 5 | 0.00 |
| PHASER_REF | 0 | 0 | 5 | 0.00 |
| OUT_FIFO | 0 | 0 | 20 | 0.00 |
| IN_FIFO | 0 | 0 | 20 | 0.00 |
| IDELAYCTRL | 0 | 0 | 5 | 0.00 |
| IBUFDS | 0 | 0 | 202 | 0.00 |
| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 20 | 0.00 |
| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 20 | 0.00 |
| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 250 | 0.00 |
| ILOGIC | 0 | 0 | 210 | 0.00 |
| OLOGIC | 0 | 0 | 210 | 0.00 |
+-----------------------------+------+-------+-----------+-------+
6. Clocking
-----------
+------------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+------------+------+-------+-----------+-------+
| BUFGCTRL | 1 | 0 | 32 | 3.13 |
| BUFIO | 0 | 0 | 20 | 0.00 |
| MMCME2_ADV | 0 | 0 | 5 | 0.00 |
| PLLE2_ADV | 0 | 0 | 5 | 0.00 |
| BUFMRCE | 0 | 0 | 10 | 0.00 |
| BUFHCE | 0 | 0 | 72 | 0.00 |
| BUFR | 0 | 0 | 20 | 0.00 |
+------------+------+-------+-----------+-------+
7. Specific Feature
-------------------
+-------------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+-------------+------+-------+-----------+-------+
| BSCANE2 | 0 | 0 | 4 | 0.00 |
| CAPTUREE2 | 0 | 0 | 1 | 0.00 |
| DNA_PORT | 0 | 0 | 1 | 0.00 |
| EFUSE_USR | 0 | 0 | 1 | 0.00 |
| FRAME_ECCE2 | 0 | 0 | 1 | 0.00 |
| ICAPE2 | 0 | 0 | 2 | 0.00 |
| PCIE_2_1 | 0 | 0 | 1 | 0.00 |
| STARTUPE2 | 0 | 0 | 1 | 0.00 |
| XADC | 0 | 0 | 1 | 0.00 |
+-------------+------+-------+-----------+-------+
8. Primitives
-------------
+----------+------+---------------------+
| Ref Name | Used | Functional Category |
+----------+------+---------------------+
| OBUF | 16 | IO |
| IBUF | 14 | IO |
| LUT6 | 12 | LUT |
| LUT5 | 11 | LUT |
| LUT3 | 8 | LUT |
| FDRE | 5 | Flop & Latch |
| LUT2 | 4 | LUT |
| LDCE | 3 | Flop & Latch |
| LUT4 | 2 | LUT |
| BUFG | 1 | Clock |
+----------+------+---------------------+
9. Black Boxes
--------------
+----------+------+
| Ref Name | Used |
+----------+------+
10. Instantiated Netlists
-------------------------
+----------+------+
| Ref Name | Used |
+----------+------+

104
Exp4/Exp4.runs/impl_1/gen_run.xml Normal file
View File

@@ -0,0 +1,104 @@
<?xml version="1.0" encoding="UTF-8"?>
<GenRun Id="impl_1" LaunchPart="xc7a35tcsg324-1" LaunchTime="1730917691">
<File Type="ROUTE-PWR" Name="calc_power_routed.rpt"/>
<File Type="PA-TCL" Name="calc.tcl"/>
<File Type="PWROPT-DCP" Name="calc_pwropt.dcp"/>
<File Type="ROUTE-PWR-SUM" Name="calc_power_summary_routed.pb"/>
<File Type="REPORTS-TCL" Name="calc_reports.tcl"/>
<File Type="BG-DRC" Name="calc.drc"/>
<File Type="OPT-HWDEF" Name="calc.hwdef"/>
<File Type="OPT-DCP" Name="calc_opt.dcp"/>
<File Type="OPT-DRC" Name="calc_drc_opted.rpt"/>
<File Type="PLACE-DCP" Name="calc_placed.dcp"/>
<File Type="PLACE-IO" Name="calc_io_placed.rpt"/>
<File Type="PLACE-UTIL" Name="calc_utilization_placed.rpt"/>
<File Type="PLACE-UTIL-PB" Name="calc_utilization_placed.pb"/>
<File Type="PLACE-CTRL" Name="calc_control_sets_placed.rpt"/>
<File Type="PLACE-PRE-SIMILARITY" Name="calc_incremental_reuse_pre_placed.rpt"/>
<File Type="POSTPLACE-PWROPT-DCP" Name="calc_postplace_pwropt.dcp"/>
<File Type="PHYSOPT-DCP" Name="calc_physopt.dcp"/>
<File Type="BG-BIT" Name="calc.bit"/>
<File Type="ROUTE-ERROR-DCP" Name="calc_routed_error.dcp"/>
<File Type="ROUTE-DCP" Name="calc_routed.dcp"/>
<File Type="ROUTE-BLACKBOX-DCP" Name="calc_routed_bb.dcp"/>
<File Type="ROUTE-DRC" Name="calc_drc_routed.rpt"/>
<File Type="ROUTE-DRC-PB" Name="calc_drc_routed.pb"/>
<File Type="ROUTE-DRC-RPX" Name="calc_drc_routed.rpx"/>
<File Type="BITSTR-MSK" Name="calc.msk"/>
<File Type="ROUTE-METHODOLOGY-DRC" Name="calc_methodology_drc_routed.rpt"/>
<File Type="BG-BGN" Name="calc.bgn"/>
<File Type="ROUTE-METHODOLOGY-DRC-RPX" Name="calc_methodology_drc_routed.rpx"/>
<File Type="BITSTR-RBT" Name="calc.rbt"/>
<File Type="ROUTE-METHODOLOGY-DRC-PB" Name="calc_methodology_drc_routed.pb"/>
<File Type="BG-BIN" Name="calc.bin"/>
<File Type="ROUTE-PWR-RPX" Name="calc_power_routed.rpx"/>
<File Type="ROUTE-STATUS" Name="calc_route_status.rpt"/>
<File Type="ROUTE-STATUS-PB" Name="calc_route_status.pb"/>
<File Type="ROUTE-TIMINGSUMMARY" Name="calc_timing_summary_routed.rpt"/>
<File Type="ROUTE-TIMING-PB" Name="calc_timing_summary_routed.pb"/>
<File Type="ROUTE-TIMING-RPX" Name="calc_timing_summary_routed.rpx"/>
<File Type="ROUTE-CLK" Name="calc_clock_utilization_routed.rpt"/>
<File Type="RDI-RDI" Name="calc.vdi"/>
<File Type="POSTROUTE-PHYSOPT-DCP" Name="calc_postroute_physopt.dcp"/>
<File Type="POSTROUTE-PHYSOPT-BLACKBOX-DCP" Name="calc_postroute_physopt_bb.dcp"/>
<File Type="BITSTR-NKY" Name="calc.nky"/>
<File Type="BITSTR-BMM" Name="calc_bd.bmm"/>
<File Type="BITSTR-MMI" Name="calc.mmi"/>
<File Type="BITSTR-LTX" Name="calc.ltx"/>
<File Type="BITSTR-SYSDEF" Name="calc.sysdef"/>
<File Type="WBT-USG" Name="usage_statistics_webtalk.html"/>
<FileSet Name="sources" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1">
<Filter Type="Srcs"/>
<File Path="$PSRCDIR/sources_1/new/SegDisplayCtrl.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/new/judge.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/new/calc.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<Config>
<Option Name="DesignMode" Val="RTL"/>
<Option Name="TopModule" Val="calc"/>
<Option Name="TopAutoSet" Val="TRUE"/>
</Config>
</FileSet>
<FileSet Name="constrs_in" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1">
<Filter Type="Constrs"/>
<File Path="$PSRCDIR/constrs_1/new/calc.xdc">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
</FileInfo>
</File>
<Config>
<Option Name="TargetConstrsFile" Val="$PSRCDIR/constrs_1/new/calc.xdc"/>
<Option Name="ConstrsType" Val="XDC"/>
</Config>
</FileSet>
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2018"/>
<Step Id="init_design"/>
<Step Id="opt_design"/>
<Step Id="power_opt_design"/>
<Step Id="place_design"/>
<Step Id="post_place_power_opt_design"/>
<Step Id="phys_opt_design"/>
<Step Id="route_design"/>
<Step Id="post_route_phys_opt_design"/>
<Step Id="write_bitstream"/>
</Strategy>
</GenRun>

9
Exp4/Exp4.runs/impl_1/htr.txt Normal file
View File

@@ -0,0 +1,9 @@
REM
REM Vivado(TM)
REM htr.txt: a Vivado-generated description of how-to-repeat the
REM the basic steps of a run. Note that runme.bat/sh needs
REM to be invoked for Vivado to track run status.
REM Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
REM
vivado -log calc.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source calc.tcl -notrace

BIN
Exp4/Exp4.runs/impl_1/init_design.pb Normal file
View File

Binary file not shown.

BIN
Exp4/Exp4.runs/impl_1/opt_design.pb Normal file
View File

Binary file not shown.

BIN
Exp4/Exp4.runs/impl_1/place_design.pb Normal file
View File

Binary file not shown.

BIN
Exp4/Exp4.runs/impl_1/route_design.pb Normal file
View File

Binary file not shown.

15
Exp4/Exp4.runs/impl_1/route_report_bus_skew_0.rpt Normal file
View File

@@ -0,0 +1,15 @@
Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
-----------------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2018.1 (win64) Build 2188600 Wed Apr 4 18:40:38 MDT 2018
| Date : Thu Nov 7 02:29:18 2024
| Host : W10-20240912132 running 64-bit major release (build 9200)
| Command : report_bus_skew -warn_on_violation -file route_report_bus_skew_0.rpt -rpx route_report_bus_skew_0.rpx
| Design : calc
| Device : 7a35t-csg324
| Speed File : -1 PRODUCTION 1.21 2018-02-08
-----------------------------------------------------------------------------------------------------------------------
Bus Skew Report
No bus skew constraints

609
Exp4/Exp4.runs/impl_1/usage_statistics_webtalk.xml Normal file
View File

@@ -0,0 +1,609 @@
<?xml version="1.0" encoding="UTF-8" ?>
<webTalkData fileName='usage_statistics_webtalk.xml' majorVersion='1' minorVersion='0' timeStamp='Thu Nov 7 02:29:24 2024'>
<section name="__ROOT__" level="0" order="1" description="">
<section name="software_version_and_target_device" level="1" order="1" description="">
<keyValuePair key="beta" value="FALSE" description="" />
<keyValuePair key="build_version" value="2188600" description="" />
<keyValuePair key="date_generated" value="Thu Nov 7 02:29:24 2024" description="" />
<keyValuePair key="os_platform" value="WIN64" description="" />
<keyValuePair key="product_version" value="Vivado v2018.1 (64-bit)" description="" />
<keyValuePair key="project_id" value="56490f59f5644a478a040843011181be" description="" />
<keyValuePair key="project_iteration" value="3" description="" />
<keyValuePair key="random_id" value="78ec1a93-fd1a-4b14-8c4b-87f04256706b" description="" />
<keyValuePair key="registration_id" value="78ec1a93-fd1a-4b14-8c4b-87f04256706b" description="" />
<keyValuePair key="route_design" value="TRUE" description="" />
<keyValuePair key="target_device" value="xc7a35t" description="" />
<keyValuePair key="target_family" value="artix7" description="" />
<keyValuePair key="target_package" value="csg324" description="" />
<keyValuePair key="target_speed" value="-1" description="" />
<keyValuePair key="tool_flow" value="Vivado" description="" />
</section>
<section name="user_environment" level="1" order="2" description="">
<keyValuePair key="cpu_name" value="13th Gen Intel(R) Core(TM) i7-13700H" description="" />
<keyValuePair key="cpu_speed" value="2918 MHz" description="" />
<keyValuePair key="os_name" value="Microsoft Windows 8 or later , 64-bit" description="" />
<keyValuePair key="os_release" value="major release (build 9200)" description="" />
<keyValuePair key="system_ram" value="16.000 GB" description="" />
<keyValuePair key="total_processors" value="1" description="" />
</section>
<section name="report_drc" level="1" order="3" description="">
<section name="command_line_options" level="2" order="1" description="">
<keyValuePair key="-append" value="default::[not_specified]" description="" />
<keyValuePair key="-checks" value="default::[not_specified]" description="" />
<keyValuePair key="-fail_on" value="default::[not_specified]" description="" />
<keyValuePair key="-force" value="default::[not_specified]" description="" />
<keyValuePair key="-format" value="default::[not_specified]" description="" />
<keyValuePair key="-internal" value="default::[not_specified]" description="" />
<keyValuePair key="-internal_only" value="default::[not_specified]" description="" />
<keyValuePair key="-messages" value="default::[not_specified]" description="" />
<keyValuePair key="-name" value="default::[not_specified]" description="" />
<keyValuePair key="-no_waivers" value="default::[not_specified]" description="" />
<keyValuePair key="-return_string" value="default::[not_specified]" description="" />
<keyValuePair key="-ruledecks" value="default::[not_specified]" description="" />
<keyValuePair key="-upgrade_cw" value="default::[not_specified]" description="" />
<keyValuePair key="-waived" value="default::[not_specified]" description="" />
</section>
<section name="results" level="2" order="2" description="">
<keyValuePair key="cfgbvs-1" value="1" description="" />
<keyValuePair key="pdrc-153" value="3" description="" />
</section>
</section>
<section name="report_methodology" level="1" order="4" description="">
<section name="command_line_options" level="2" order="1" description="">
<keyValuePair key="-append" value="default::[not_specified]" description="" />
<keyValuePair key="-checks" value="default::[not_specified]" description="" />
<keyValuePair key="-fail_on" value="default::[not_specified]" description="" />
<keyValuePair key="-force" value="default::[not_specified]" description="" />
<keyValuePair key="-format" value="default::[not_specified]" description="" />
<keyValuePair key="-messages" value="default::[not_specified]" description="" />
<keyValuePair key="-name" value="default::[not_specified]" description="" />
<keyValuePair key="-return_string" value="default::[not_specified]" description="" />
<keyValuePair key="-waived" value="default::[not_specified]" description="" />
</section>
<section name="results" level="2" order="2" description="">
<keyValuePair key="lutar-1" value="1" description="" />
<keyValuePair key="timing-17" value="5" description="" />
<keyValuePair key="timing-20" value="3" description="" />
</section>
</section>
<section name="report_power" level="1" order="5" description="">
<section name="command_line_options" level="2" order="1" description="">
<keyValuePair key="-advisory" value="default::[not_specified]" description="" />
<keyValuePair key="-append" value="default::[not_specified]" description="" />
<keyValuePair key="-file" value="[specified]" description="" />
<keyValuePair key="-format" value="default::text" description="" />
<keyValuePair key="-hier" value="default::power" description="" />
<keyValuePair key="-l" value="default::[not_specified]" description="" />
<keyValuePair key="-name" value="default::[not_specified]" description="" />
<keyValuePair key="-no_propagation" value="default::[not_specified]" description="" />
<keyValuePair key="-return_string" value="default::[not_specified]" description="" />
<keyValuePair key="-rpx" value="[specified]" description="" />
<keyValuePair key="-verbose" value="default::[not_specified]" description="" />
<keyValuePair key="-vid" value="default::[not_specified]" description="" />
<keyValuePair key="-xpe" value="default::[not_specified]" description="" />
</section>
<section name="usage" level="2" order="2" description="">
<keyValuePair key="airflow" value="250 (LFM)" description="" />
<keyValuePair key="ambient_temp" value="25.0 (C)" description="" />
<keyValuePair key="bi-dir_toggle" value="12.500000" description="" />
<keyValuePair key="bidir_output_enable" value="1.000000" description="" />
<keyValuePair key="board_layers" value="12to15 (12 to 15 Layers)" description="" />
<keyValuePair key="board_selection" value="medium (10&quot;x10&quot;)" description="" />
<keyValuePair key="confidence_level_clock_activity" value="Low" description="" />
<keyValuePair key="confidence_level_design_state" value="High" description="" />
<keyValuePair key="confidence_level_device_models" value="High" description="" />
<keyValuePair key="confidence_level_internal_activity" value="Medium" description="" />
<keyValuePair key="confidence_level_io_activity" value="Low" description="" />
<keyValuePair key="confidence_level_overall" value="Low" description="" />
<keyValuePair key="customer" value="TBD" description="" />
<keyValuePair key="customer_class" value="TBD" description="" />
<keyValuePair key="devstatic" value="0.106823" description="" />
<keyValuePair key="die" value="xc7a35tcsg324-1" description="" />
<keyValuePair key="dsp_output_toggle" value="12.500000" description="" />
<keyValuePair key="dynamic" value="7.487950" description="" />
<keyValuePair key="effective_thetaja" value="4.8" description="" />
<keyValuePair key="enable_probability" value="0.990000" description="" />
<keyValuePair key="family" value="artix7" description="" />
<keyValuePair key="ff_toggle" value="12.500000" description="" />
<keyValuePair key="flow_state" value="routed" description="" />
<keyValuePair key="heatsink" value="medium (Medium Profile)" description="" />
<keyValuePair key="i/o" value="7.107265" description="" />
<keyValuePair key="input_toggle" value="12.500000" description="" />
<keyValuePair key="junction_temp" value="61.3 (C)" description="" />
<keyValuePair key="logic" value="0.133160" description="" />
<keyValuePair key="mgtavcc_dynamic_current" value="0.000000" description="" />
<keyValuePair key="mgtavcc_static_current" value="0.000000" description="" />
<keyValuePair key="mgtavcc_total_current" value="0.000000" description="" />
<keyValuePair key="mgtavcc_voltage" value="1.000000" description="" />
<keyValuePair key="mgtavtt_dynamic_current" value="0.000000" description="" />
<keyValuePair key="mgtavtt_static_current" value="0.000000" description="" />
<keyValuePair key="mgtavtt_total_current" value="0.000000" description="" />
<keyValuePair key="mgtavtt_voltage" value="1.200000" description="" />
<keyValuePair key="netlist_net_matched" value="NA" description="" />
<keyValuePair key="off-chip_power" value="0.000000" description="" />
<keyValuePair key="on-chip_power" value="7.594773" description="" />
<keyValuePair key="output_enable" value="1.000000" description="" />
<keyValuePair key="output_load" value="5.000000" description="" />
<keyValuePair key="output_toggle" value="12.500000" description="" />
<keyValuePair key="package" value="csg324" description="" />
<keyValuePair key="pct_clock_constrained" value="1.000000" description="" />
<keyValuePair key="pct_inputs_defined" value="0" description="" />
<keyValuePair key="platform" value="nt64" description="" />
<keyValuePair key="process" value="typical" description="" />
<keyValuePair key="ram_enable" value="50.000000" description="" />
<keyValuePair key="ram_write" value="50.000000" description="" />
<keyValuePair key="read_saif" value="False" description="" />
<keyValuePair key="set/reset_probability" value="0.000000" description="" />
<keyValuePair key="signal_rate" value="False" description="" />
<keyValuePair key="signals" value="0.247525" description="" />
<keyValuePair key="simulation_file" value="None" description="" />
<keyValuePair key="speedgrade" value="-1" description="" />
<keyValuePair key="static_prob" value="False" description="" />
<keyValuePair key="temp_grade" value="commercial" description="" />
<keyValuePair key="thetajb" value="6.8 (C/W)" description="" />
<keyValuePair key="thetasa" value="4.6 (C/W)" description="" />
<keyValuePair key="toggle_rate" value="False" description="" />
<keyValuePair key="user_board_temp" value="25.0 (C)" description="" />
<keyValuePair key="user_effective_thetaja" value="4.8" description="" />
<keyValuePair key="user_junc_temp" value="61.3 (C)" description="" />
<keyValuePair key="user_thetajb" value="6.8 (C/W)" description="" />
<keyValuePair key="user_thetasa" value="4.6 (C/W)" description="" />
<keyValuePair key="vccadc_dynamic_current" value="0.000000" description="" />
<keyValuePair key="vccadc_static_current" value="0.020000" description="" />
<keyValuePair key="vccadc_total_current" value="0.020000" description="" />
<keyValuePair key="vccadc_voltage" value="1.800000" description="" />
<keyValuePair key="vccaux_dynamic_current" value="0.258388" description="" />
<keyValuePair key="vccaux_io_dynamic_current" value="0.000000" description="" />
<keyValuePair key="vccaux_io_static_current" value="0.000000" description="" />
<keyValuePair key="vccaux_io_total_current" value="0.000000" description="" />
<keyValuePair key="vccaux_io_voltage" value="1.800000" description="" />
<keyValuePair key="vccaux_static_current" value="0.015638" description="" />
<keyValuePair key="vccaux_total_current" value="0.274026" description="" />
<keyValuePair key="vccaux_voltage" value="1.800000" description="" />
<keyValuePair key="vccbram_dynamic_current" value="0.000000" description="" />
<keyValuePair key="vccbram_static_current" value="0.000754" description="" />
<keyValuePair key="vccbram_total_current" value="0.000754" description="" />
<keyValuePair key="vccbram_voltage" value="1.000000" description="" />
<keyValuePair key="vccint_dynamic_current" value="0.436685" description="" />
<keyValuePair key="vccint_static_current" value="0.038622" description="" />
<keyValuePair key="vccint_total_current" value="0.475306" description="" />
<keyValuePair key="vccint_voltage" value="1.000000" description="" />
<keyValuePair key="vcco12_dynamic_current" value="0.000000" description="" />
<keyValuePair key="vcco12_static_current" value="0.000000" description="" />
<keyValuePair key="vcco12_total_current" value="0.000000" description="" />
<keyValuePair key="vcco12_voltage" value="1.200000" description="" />
<keyValuePair key="vcco135_dynamic_current" value="0.000000" description="" />
<keyValuePair key="vcco135_static_current" value="0.000000" description="" />
<keyValuePair key="vcco135_total_current" value="0.000000" description="" />
<keyValuePair key="vcco135_voltage" value="1.350000" description="" />
<keyValuePair key="vcco15_dynamic_current" value="0.000000" description="" />
<keyValuePair key="vcco15_static_current" value="0.000000" description="" />
<keyValuePair key="vcco15_total_current" value="0.000000" description="" />
<keyValuePair key="vcco15_voltage" value="1.500000" description="" />
<keyValuePair key="vcco18_dynamic_current" value="0.000000" description="" />
<keyValuePair key="vcco18_static_current" value="0.000000" description="" />
<keyValuePair key="vcco18_total_current" value="0.000000" description="" />
<keyValuePair key="vcco18_voltage" value="1.800000" description="" />
<keyValuePair key="vcco25_dynamic_current" value="0.000000" description="" />
<keyValuePair key="vcco25_static_current" value="0.000000" description="" />
<keyValuePair key="vcco25_total_current" value="0.000000" description="" />
<keyValuePair key="vcco25_voltage" value="2.500000" description="" />
<keyValuePair key="vcco33_dynamic_current" value="1.995808" description="" />
<keyValuePair key="vcco33_static_current" value="0.001000" description="" />
<keyValuePair key="vcco33_total_current" value="1.996808" description="" />
<keyValuePair key="vcco33_voltage" value="3.300000" description="" />
<keyValuePair key="version" value="2018.1" description="" />
</section>
</section>
<section name="report_utilization" level="1" order="6" description="">
<section name="clocking" level="2" order="1" description="">
<keyValuePair key="bufgctrl_available" value="32" description="" />
<keyValuePair key="bufgctrl_fixed" value="0" description="" />
<keyValuePair key="bufgctrl_used" value="1" description="" />
<keyValuePair key="bufgctrl_util_percentage" value="3.13" description="" />
<keyValuePair key="bufhce_available" value="72" description="" />
<keyValuePair key="bufhce_fixed" value="0" description="" />
<keyValuePair key="bufhce_used" value="0" description="" />
<keyValuePair key="bufhce_util_percentage" value="0.00" description="" />
<keyValuePair key="bufio_available" value="20" description="" />
<keyValuePair key="bufio_fixed" value="0" description="" />
<keyValuePair key="bufio_used" value="0" description="" />
<keyValuePair key="bufio_util_percentage" value="0.00" description="" />
<keyValuePair key="bufmrce_available" value="10" description="" />
<keyValuePair key="bufmrce_fixed" value="0" description="" />
<keyValuePair key="bufmrce_used" value="0" description="" />
<keyValuePair key="bufmrce_util_percentage" value="0.00" description="" />
<keyValuePair key="bufr_available" value="20" description="" />
<keyValuePair key="bufr_fixed" value="0" description="" />
<keyValuePair key="bufr_used" value="0" description="" />
<keyValuePair key="bufr_util_percentage" value="0.00" description="" />
<keyValuePair key="mmcme2_adv_available" value="5" description="" />
<keyValuePair key="mmcme2_adv_fixed" value="0" description="" />
<keyValuePair key="mmcme2_adv_used" value="0" description="" />
<keyValuePair key="mmcme2_adv_util_percentage" value="0.00" description="" />
<keyValuePair key="plle2_adv_available" value="5" description="" />
<keyValuePair key="plle2_adv_fixed" value="0" description="" />
<keyValuePair key="plle2_adv_used" value="0" description="" />
<keyValuePair key="plle2_adv_util_percentage" value="0.00" description="" />
</section>
<section name="dsp" level="2" order="2" description="">
<keyValuePair key="dsps_available" value="90" description="" />
<keyValuePair key="dsps_fixed" value="0" description="" />
<keyValuePair key="dsps_used" value="0" description="" />
<keyValuePair key="dsps_util_percentage" value="0.00" description="" />
</section>
<section name="io_standard" level="2" order="3" description="">
<keyValuePair key="blvds_25" value="0" description="" />
<keyValuePair key="diff_hstl_i" value="0" description="" />
<keyValuePair key="diff_hstl_i_18" value="0" description="" />
<keyValuePair key="diff_hstl_ii" value="0" description="" />
<keyValuePair key="diff_hstl_ii_18" value="0" description="" />
<keyValuePair key="diff_hsul_12" value="0" description="" />
<keyValuePair key="diff_mobile_ddr" value="0" description="" />
<keyValuePair key="diff_sstl135" value="0" description="" />
<keyValuePair key="diff_sstl135_r" value="0" description="" />
<keyValuePair key="diff_sstl15" value="0" description="" />
<keyValuePair key="diff_sstl15_r" value="0" description="" />
<keyValuePair key="diff_sstl18_i" value="0" description="" />
<keyValuePair key="diff_sstl18_ii" value="0" description="" />
<keyValuePair key="hstl_i" value="0" description="" />
<keyValuePair key="hstl_i_18" value="0" description="" />
<keyValuePair key="hstl_ii" value="0" description="" />
<keyValuePair key="hstl_ii_18" value="0" description="" />
<keyValuePair key="hsul_12" value="0" description="" />
<keyValuePair key="lvcmos12" value="0" description="" />
<keyValuePair key="lvcmos15" value="0" description="" />
<keyValuePair key="lvcmos18" value="0" description="" />
<keyValuePair key="lvcmos25" value="0" description="" />
<keyValuePair key="lvcmos33" value="1" description="" />
<keyValuePair key="lvds_25" value="0" description="" />
<keyValuePair key="lvttl" value="0" description="" />
<keyValuePair key="mini_lvds_25" value="0" description="" />
<keyValuePair key="mobile_ddr" value="0" description="" />
<keyValuePair key="pci33_3" value="0" description="" />
<keyValuePair key="ppds_25" value="0" description="" />
<keyValuePair key="rsds_25" value="0" description="" />
<keyValuePair key="sstl135" value="0" description="" />
<keyValuePair key="sstl135_r" value="0" description="" />
<keyValuePair key="sstl15" value="0" description="" />
<keyValuePair key="sstl15_r" value="0" description="" />
<keyValuePair key="sstl18_i" value="0" description="" />
<keyValuePair key="sstl18_ii" value="0" description="" />
<keyValuePair key="tmds_33" value="0" description="" />
</section>
<section name="memory" level="2" order="4" description="">
<keyValuePair key="block_ram_tile_available" value="50" description="" />
<keyValuePair key="block_ram_tile_fixed" value="0" description="" />
<keyValuePair key="block_ram_tile_used" value="0" description="" />
<keyValuePair key="block_ram_tile_util_percentage" value="0.00" description="" />
<keyValuePair key="ramb18_available" value="100" description="" />
<keyValuePair key="ramb18_fixed" value="0" description="" />
<keyValuePair key="ramb18_used" value="0" description="" />
<keyValuePair key="ramb18_util_percentage" value="0.00" description="" />
<keyValuePair key="ramb36_fifo_available" value="50" description="" />
<keyValuePair key="ramb36_fifo_fixed" value="0" description="" />
<keyValuePair key="ramb36_fifo_used" value="0" description="" />
<keyValuePair key="ramb36_fifo_util_percentage" value="0.00" description="" />
</section>
<section name="primitives" level="2" order="5" description="">
<keyValuePair key="bufg_functional_category" value="Clock" description="" />
<keyValuePair key="bufg_used" value="1" description="" />
<keyValuePair key="fdre_functional_category" value="Flop &amp; Latch" description="" />
<keyValuePair key="fdre_used" value="5" description="" />
<keyValuePair key="ibuf_functional_category" value="IO" description="" />
<keyValuePair key="ibuf_used" value="14" description="" />
<keyValuePair key="ldce_functional_category" value="Flop &amp; Latch" description="" />
<keyValuePair key="ldce_used" value="3" description="" />
<keyValuePair key="lut2_functional_category" value="LUT" description="" />
<keyValuePair key="lut2_used" value="4" description="" />
<keyValuePair key="lut3_functional_category" value="LUT" description="" />
<keyValuePair key="lut3_used" value="8" description="" />
<keyValuePair key="lut4_functional_category" value="LUT" description="" />
<keyValuePair key="lut4_used" value="2" description="" />
<keyValuePair key="lut5_functional_category" value="LUT" description="" />
<keyValuePair key="lut5_used" value="11" description="" />
<keyValuePair key="lut6_functional_category" value="LUT" description="" />
<keyValuePair key="lut6_used" value="12" description="" />
<keyValuePair key="obuf_functional_category" value="IO" description="" />
<keyValuePair key="obuf_used" value="16" description="" />
</section>
<section name="slice_logic" level="2" order="6" description="">
<keyValuePair key="f7_muxes_available" value="16300" description="" />
<keyValuePair key="f7_muxes_fixed" value="0" description="" />
<keyValuePair key="f7_muxes_used" value="0" description="" />
<keyValuePair key="f7_muxes_util_percentage" value="0.00" description="" />
<keyValuePair key="f8_muxes_available" value="8150" description="" />
<keyValuePair key="f8_muxes_fixed" value="0" description="" />
<keyValuePair key="f8_muxes_used" value="0" description="" />
<keyValuePair key="f8_muxes_util_percentage" value="0.00" description="" />
<keyValuePair key="fully_used_lut_ff_pairs_fixed" value="0.02" description="" />
<keyValuePair key="fully_used_lut_ff_pairs_used" value="0" description="" />
<keyValuePair key="lut_as_distributed_ram_fixed" value="0" description="" />
<keyValuePair key="lut_as_distributed_ram_used" value="0" description="" />
<keyValuePair key="lut_as_logic_available" value="20800" description="" />
<keyValuePair key="lut_as_logic_available" value="20800" description="" />
<keyValuePair key="lut_as_logic_fixed" value="0" description="" />
<keyValuePair key="lut_as_logic_fixed" value="0" description="" />
<keyValuePair key="lut_as_logic_used" value="32" description="" />
<keyValuePair key="lut_as_logic_used" value="32" description="" />
<keyValuePair key="lut_as_logic_util_percentage" value="0.15" description="" />
<keyValuePair key="lut_as_logic_util_percentage" value="0.15" description="" />
<keyValuePair key="lut_as_memory_available" value="9600" description="" />
<keyValuePair key="lut_as_memory_available" value="9600" description="" />
<keyValuePair key="lut_as_memory_fixed" value="0" description="" />
<keyValuePair key="lut_as_memory_fixed" value="0" description="" />
<keyValuePair key="lut_as_memory_used" value="0" description="" />
<keyValuePair key="lut_as_memory_used" value="0" description="" />
<keyValuePair key="lut_as_memory_util_percentage" value="0.00" description="" />
<keyValuePair key="lut_as_memory_util_percentage" value="0.00" description="" />
<keyValuePair key="lut_as_shift_register_fixed" value="0" description="" />
<keyValuePair key="lut_as_shift_register_used" value="0" description="" />
<keyValuePair key="lut_ff_pairs_with_one_unused_flip_flop_fixed" value="0" description="" />
<keyValuePair key="lut_ff_pairs_with_one_unused_flip_flop_used" value="2" description="" />
<keyValuePair key="lut_ff_pairs_with_one_unused_lut_output_fixed" value="2" description="" />
<keyValuePair key="lut_ff_pairs_with_one_unused_lut_output_used" value="1" description="" />
<keyValuePair key="lut_flip_flop_pairs_available" value="20800" description="" />
<keyValuePair key="lut_flip_flop_pairs_fixed" value="0" description="" />
<keyValuePair key="lut_flip_flop_pairs_used" value="2" description="" />
<keyValuePair key="lut_flip_flop_pairs_util_percentage" value="&lt;0.01" description="" />
<keyValuePair key="register_as_flip_flop_available" value="41600" description="" />
<keyValuePair key="register_as_flip_flop_fixed" value="0" description="" />
<keyValuePair key="register_as_flip_flop_used" value="5" description="" />
<keyValuePair key="register_as_flip_flop_util_percentage" value="0.01" description="" />
<keyValuePair key="register_as_latch_available" value="41600" description="" />
<keyValuePair key="register_as_latch_fixed" value="0" description="" />
<keyValuePair key="register_as_latch_used" value="3" description="" />
<keyValuePair key="register_as_latch_util_percentage" value="&lt;0.01" description="" />
<keyValuePair key="slice_available" value="8150" description="" />
<keyValuePair key="slice_fixed" value="0" description="" />
<keyValuePair key="slice_luts_available" value="20800" description="" />
<keyValuePair key="slice_luts_fixed" value="0" description="" />
<keyValuePair key="slice_luts_used" value="32" description="" />
<keyValuePair key="slice_luts_util_percentage" value="0.15" description="" />
<keyValuePair key="slice_registers_available" value="41600" description="" />
<keyValuePair key="slice_registers_fixed" value="0" description="" />
<keyValuePair key="slice_registers_used" value="8" description="" />
<keyValuePair key="slice_registers_util_percentage" value="0.02" description="" />
<keyValuePair key="slice_used" value="12" description="" />
<keyValuePair key="slice_util_percentage" value="0.15" description="" />
<keyValuePair key="slicel_fixed" value="0" description="" />
<keyValuePair key="slicel_used" value="8" description="" />
<keyValuePair key="slicem_fixed" value="0" description="" />
<keyValuePair key="slicem_used" value="4" description="" />
<keyValuePair key="unique_control_sets_used" value="4" description="" />
<keyValuePair key="using_o5_and_o6_fixed" value="4" description="" />
<keyValuePair key="using_o5_and_o6_used" value="5" description="" />
<keyValuePair key="using_o5_output_only_fixed" value="5" description="" />
<keyValuePair key="using_o5_output_only_used" value="0" description="" />
<keyValuePair key="using_o6_output_only_fixed" value="0" description="" />
<keyValuePair key="using_o6_output_only_used" value="27" description="" />
</section>
<section name="specific_feature" level="2" order="7" description="">
<keyValuePair key="bscane2_available" value="4" description="" />
<keyValuePair key="bscane2_fixed" value="0" description="" />
<keyValuePair key="bscane2_used" value="0" description="" />
<keyValuePair key="bscane2_util_percentage" value="0.00" description="" />
<keyValuePair key="capturee2_available" value="1" description="" />
<keyValuePair key="capturee2_fixed" value="0" description="" />
<keyValuePair key="capturee2_used" value="0" description="" />
<keyValuePair key="capturee2_util_percentage" value="0.00" description="" />
<keyValuePair key="dna_port_available" value="1" description="" />
<keyValuePair key="dna_port_fixed" value="0" description="" />
<keyValuePair key="dna_port_used" value="0" description="" />
<keyValuePair key="dna_port_util_percentage" value="0.00" description="" />
<keyValuePair key="efuse_usr_available" value="1" description="" />
<keyValuePair key="efuse_usr_fixed" value="0" description="" />
<keyValuePair key="efuse_usr_used" value="0" description="" />
<keyValuePair key="efuse_usr_util_percentage" value="0.00" description="" />
<keyValuePair key="frame_ecce2_available" value="1" description="" />
<keyValuePair key="frame_ecce2_fixed" value="0" description="" />
<keyValuePair key="frame_ecce2_used" value="0" description="" />
<keyValuePair key="frame_ecce2_util_percentage" value="0.00" description="" />
<keyValuePair key="icape2_available" value="2" description="" />
<keyValuePair key="icape2_fixed" value="0" description="" />
<keyValuePair key="icape2_used" value="0" description="" />
<keyValuePair key="icape2_util_percentage" value="0.00" description="" />
<keyValuePair key="pcie_2_1_available" value="1" description="" />
<keyValuePair key="pcie_2_1_fixed" value="0" description="" />
<keyValuePair key="pcie_2_1_used" value="0" description="" />
<keyValuePair key="pcie_2_1_util_percentage" value="0.00" description="" />
<keyValuePair key="startupe2_available" value="1" description="" />
<keyValuePair key="startupe2_fixed" value="0" description="" />
<keyValuePair key="startupe2_used" value="0" description="" />
<keyValuePair key="startupe2_util_percentage" value="0.00" description="" />
<keyValuePair key="xadc_available" value="1" description="" />
<keyValuePair key="xadc_fixed" value="0" description="" />
<keyValuePair key="xadc_used" value="0" description="" />
<keyValuePair key="xadc_util_percentage" value="0.00" description="" />
</section>
</section>
<section name="router" level="1" order="7" description="">
<section name="usage" level="2" order="1" description="">
<keyValuePair key="actual_expansions" value="95852" description="" />
<keyValuePair key="bogomips" value="0" description="" />
<keyValuePair key="bram18" value="0" description="" />
<keyValuePair key="bram36" value="0" description="" />
<keyValuePair key="bufg" value="0" description="" />
<keyValuePair key="bufr" value="0" description="" />
<keyValuePair key="ctrls" value="4" description="" />
<keyValuePair key="dsp" value="0" description="" />
<keyValuePair key="effort" value="2" description="" />
<keyValuePair key="estimated_expansions" value="107304" description="" />
<keyValuePair key="ff" value="8" description="" />
<keyValuePair key="global_clocks" value="1" description="" />
<keyValuePair key="high_fanout_nets" value="0" description="" />
<keyValuePair key="iob" value="30" description="" />
<keyValuePair key="lut" value="33" description="" />
<keyValuePair key="movable_instances" value="84" description="" />
<keyValuePair key="nets" value="98" description="" />
<keyValuePair key="pins" value="314" description="" />
<keyValuePair key="pll" value="0" description="" />
<keyValuePair key="router_runtime" value="0.000000" description="" />
<keyValuePair key="router_timing_driven" value="1" description="" />
<keyValuePair key="threads" value="2" description="" />
<keyValuePair key="timing_constraints_exist" value="1" description="" />
</section>
</section>
<section name="synthesis" level="1" order="8" description="">
<section name="command_line_options" level="2" order="1" description="">
<keyValuePair key="-assert" value="default::[not_specified]" description="" />
<keyValuePair key="-bufg" value="default::12" description="" />
<keyValuePair key="-cascade_dsp" value="default::auto" description="" />
<keyValuePair key="-constrset" value="default::[not_specified]" description="" />
<keyValuePair key="-control_set_opt_threshold" value="default::auto" description="" />
<keyValuePair key="-directive" value="default::default" description="" />
<keyValuePair key="-fanout_limit" value="default::10000" description="" />
<keyValuePair key="-flatten_hierarchy" value="default::rebuilt" description="" />
<keyValuePair key="-fsm_extraction" value="default::auto" description="" />
<keyValuePair key="-gated_clock_conversion" value="default::off" description="" />
<keyValuePair key="-generic" value="default::[not_specified]" description="" />
<keyValuePair key="-include_dirs" value="default::[not_specified]" description="" />
<keyValuePair key="-keep_equivalent_registers" value="default::[not_specified]" description="" />
<keyValuePair key="-max_bram" value="default::-1" description="" />
<keyValuePair key="-max_bram_cascade_height" value="default::-1" description="" />
<keyValuePair key="-max_dsp" value="default::-1" description="" />
<keyValuePair key="-max_uram" value="default::-1" description="" />
<keyValuePair key="-max_uram_cascade_height" value="default::-1" description="" />
<keyValuePair key="-mode" value="default::default" description="" />
<keyValuePair key="-name" value="default::[not_specified]" description="" />
<keyValuePair key="-no_lc" value="default::[not_specified]" description="" />
<keyValuePair key="-no_srlextract" value="default::[not_specified]" description="" />
<keyValuePair key="-no_timing_driven" value="default::[not_specified]" description="" />
<keyValuePair key="-part" value="xc7a35tcsg324-1" description="" />
<keyValuePair key="-resource_sharing" value="default::auto" description="" />
<keyValuePair key="-retiming" value="default::[not_specified]" description="" />
<keyValuePair key="-rtl" value="default::[not_specified]" description="" />
<keyValuePair key="-rtl_skip_constraints" value="default::[not_specified]" description="" />
<keyValuePair key="-rtl_skip_ip" value="default::[not_specified]" description="" />
<keyValuePair key="-seu_protect" value="default::none" description="" />
<keyValuePair key="-sfcu" value="default::[not_specified]" description="" />
<keyValuePair key="-shreg_min_size" value="default::3" description="" />
<keyValuePair key="-top" value="calc" description="" />
<keyValuePair key="-verilog_define" value="default::[not_specified]" description="" />
</section>
<section name="usage" level="2" order="2" description="">
<keyValuePair key="elapsed" value="00:00:21s" description="" />
<keyValuePair key="hls_ip" value="0" description="" />
<keyValuePair key="memory_gain" value="486.828MB" description="" />
<keyValuePair key="memory_peak" value="787.938MB" description="" />
</section>
</section>
<section name="unisim_transformation" level="1" order="9" description="">
<section name="post_unisim_transformation" level="2" order="1" description="">
<keyValuePair key="bufg" value="1" description="" />
<keyValuePair key="fdre" value="5" description="" />
<keyValuePair key="gnd" value="4" description="" />
<keyValuePair key="ibuf" value="14" description="" />
<keyValuePair key="ldce" value="3" description="" />
<keyValuePair key="lut2" value="4" description="" />
<keyValuePair key="lut3" value="8" description="" />
<keyValuePair key="lut4" value="2" description="" />
<keyValuePair key="lut5" value="11" description="" />
<keyValuePair key="lut6" value="12" description="" />
<keyValuePair key="obuf" value="16" description="" />
<keyValuePair key="vcc" value="4" description="" />
</section>
<section name="pre_unisim_transformation" level="2" order="2" description="">
<keyValuePair key="bufg" value="1" description="" />
<keyValuePair key="fdre" value="5" description="" />
<keyValuePair key="gnd" value="2" description="" />
<keyValuePair key="ibuf" value="14" description="" />
<keyValuePair key="ldce" value="1" description="" />
<keyValuePair key="ldcp" value="2" description="" />
<keyValuePair key="lut2" value="4" description="" />
<keyValuePair key="lut3" value="4" description="" />
<keyValuePair key="lut4" value="2" description="" />
<keyValuePair key="lut5" value="11" description="" />
<keyValuePair key="lut6" value="12" description="" />
<keyValuePair key="obuf" value="16" description="" />
<keyValuePair key="vcc" value="2" description="" />
</section>
</section>
<section name="vivado_usage" level="1" order="10" description="">
<section name="gui_handlers" level="2" order="1" description="">
<keyValuePair key="basedialog_cancel" value="1" description="" />
<keyValuePair key="basedialog_ok" value="29" description="" />
<keyValuePair key="basedialog_yes" value="2" description="" />
<keyValuePair key="createconstraintsfilepanel_file_name" value="1" description="" />
<keyValuePair key="createsrcfiledialog_file_name" value="5" description="" />
<keyValuePair key="filesetpanel_file_set_panel_tree" value="26" description="" />
<keyValuePair key="flownavigatortreepanel_flow_navigator_tree" value="11" description="" />
<keyValuePair key="fpgachooser_fpga_table" value="1" description="" />
<keyValuePair key="gettingstartedview_create_new_project" value="1" description="" />
<keyValuePair key="hardwaretreepanel_hardware_tree_table" value="8" description="" />
<keyValuePair key="messagewithoptiondialog_dont_show_this_dialog_again" value="1" description="" />
<keyValuePair key="msgtreepanel_message_view_tree" value="1" description="" />
<keyValuePair key="pacommandnames_add_sources" value="3" description="" />
<keyValuePair key="pacommandnames_auto_connect_target" value="4" description="" />
<keyValuePair key="pacommandnames_auto_update_hier" value="3" description="" />
<keyValuePair key="pacommandnames_close_server" value="1" description="" />
<keyValuePair key="pacommandnames_goto_netlist_design" value="2" description="" />
<keyValuePair key="pacommandnames_open_hardware_manager" value="2" description="" />
<keyValuePair key="pacommandnames_open_target" value="1" description="" />
<keyValuePair key="pacommandnames_program_fpga" value="1" description="" />
<keyValuePair key="pacommandnames_run_bitgen" value="2" description="" />
<keyValuePair key="pacommandnames_write_config_memory_file" value="1" description="" />
<keyValuePair key="programdebugtab_open_target" value="4" description="" />
<keyValuePair key="programdebugtab_program_device" value="2" description="" />
<keyValuePair key="programfpgadialog_program" value="3" description="" />
<keyValuePair key="projectnamechooser_project_name" value="1" description="" />
<keyValuePair key="rdicommands_delete" value="1" description="" />
<keyValuePair key="removesourcesdialog_also_delete" value="1" description="" />
<keyValuePair key="saveprojectutils_cancel" value="1" description="" />
<keyValuePair key="signaltreepanel_signal_tree_table" value="32" description="" />
<keyValuePair key="srcchooserpanel_create_file" value="4" description="" />
<keyValuePair key="syntheticagettingstartedview_recent_projects" value="1" description="" />
</section>
<section name="java_command_handlers" level="2" order="2" description="">
<keyValuePair key="addsources" value="4" description="" />
<keyValuePair key="autoconnecttarget" value="4" description="" />
<keyValuePair key="closeserver" value="1" description="" />
<keyValuePair key="editdelete" value="1" description="" />
<keyValuePair key="launchprogramfpga" value="3" description="" />
<keyValuePair key="newproject" value="1" description="" />
<keyValuePair key="openhardwaremanager" value="3" description="" />
<keyValuePair key="opentarget" value="1" description="" />
<keyValuePair key="runbitgen" value="4" description="" />
<keyValuePair key="runimplementation" value="2" description="" />
<keyValuePair key="runsynthesis" value="5" description="" />
<keyValuePair key="savedesign" value="2" description="" />
<keyValuePair key="savefileproxyhandler" value="1" description="" />
<keyValuePair key="showview" value="1" description="" />
<keyValuePair key="viewtasksynthesis" value="2" description="" />
</section>
<section name="other_data" level="2" order="3" description="">
<keyValuePair key="guimode" value="2" description="" />
</section>
<section name="project_data" level="2" order="4" description="">
<keyValuePair key="constraintsetcount" value="1" description="" />
<keyValuePair key="core_container" value="false" description="" />
<keyValuePair key="currentimplrun" value="impl_1" description="" />
<keyValuePair key="currentsynthesisrun" value="synth_1" description="" />
<keyValuePair key="default_library" value="xil_defaultlib" description="" />
<keyValuePair key="designmode" value="RTL" description="" />
<keyValuePair key="export_simulation_activehdl" value="0" description="" />
<keyValuePair key="export_simulation_ies" value="0" description="" />
<keyValuePair key="export_simulation_modelsim" value="0" description="" />
<keyValuePair key="export_simulation_questa" value="0" description="" />
<keyValuePair key="export_simulation_riviera" value="0" description="" />
<keyValuePair key="export_simulation_vcs" value="0" description="" />
<keyValuePair key="export_simulation_xsim" value="0" description="" />
<keyValuePair key="implstrategy" value="Vivado Implementation Defaults" description="" />
<keyValuePair key="launch_simulation_activehdl" value="0" description="" />
<keyValuePair key="launch_simulation_ies" value="0" description="" />
<keyValuePair key="launch_simulation_modelsim" value="0" description="" />
<keyValuePair key="launch_simulation_questa" value="0" description="" />
<keyValuePair key="launch_simulation_riviera" value="0" description="" />
<keyValuePair key="launch_simulation_vcs" value="0" description="" />
<keyValuePair key="launch_simulation_xsim" value="0" description="" />
<keyValuePair key="simulator_language" value="Mixed" description="" />
<keyValuePair key="srcsetcount" value="3" description="" />
<keyValuePair key="synthesisstrategy" value="Vivado Synthesis Defaults" description="" />
<keyValuePair key="target_language" value="Verilog" description="" />
<keyValuePair key="target_simulator" value="XSim" description="" />
<keyValuePair key="totalimplruns" value="1" description="" />
<keyValuePair key="totalsynthesisruns" value="1" description="" />
</section>
</section>
</section>
</webTalkData>

12
Exp4/Exp4.runs/impl_1/vivado.jou Normal file
View File

@@ -0,0 +1,12 @@
#-----------------------------------------------------------
# Vivado v2018.1 (64-bit)
# SW Build 2188600 on Wed Apr 4 18:40:38 MDT 2018
# IP Build 2185939 on Wed Apr 4 20:55:05 MDT 2018
# Start of session at: Thu Nov 7 02:28:43 2024
# Process ID: 25584
# Current directory: F:/Schoolwork/DigitalLogic/Exp4/Exp4.runs/impl_1
# Command line: vivado.exe -log calc.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source calc.tcl -notrace
# Log file: F:/Schoolwork/DigitalLogic/Exp4/Exp4.runs/impl_1/calc.vdi
# Journal file: F:/Schoolwork/DigitalLogic/Exp4/Exp4.runs/impl_1\vivado.jou
#-----------------------------------------------------------
source calc.tcl -notrace

BIN
Exp4/Exp4.runs/impl_1/vivado.pb Normal file
View File

Binary file not shown.

12
Exp4/Exp4.runs/impl_1/vivado_20992.backup.jou Normal file
View File

@@ -0,0 +1,12 @@
#-----------------------------------------------------------
# Vivado v2018.1 (64-bit)
# SW Build 2188600 on Wed Apr 4 18:40:38 MDT 2018
# IP Build 2185939 on Wed Apr 4 20:55:05 MDT 2018
# Start of session at: Thu Nov 7 02:25:03 2024
# Process ID: 20992
# Current directory: F:/Schoolwork/DigitalLogic/Exp4/Exp4.runs/impl_1
# Command line: vivado.exe -log calc.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source calc.tcl -notrace
# Log file: F:/Schoolwork/DigitalLogic/Exp4/Exp4.runs/impl_1/calc.vdi
# Journal file: F:/Schoolwork/DigitalLogic/Exp4/Exp4.runs/impl_1\vivado.jou
#-----------------------------------------------------------
source calc.tcl -notrace

BIN
Exp4/Exp4.runs/impl_1/write_bitstream.pb Normal file
View File

Binary file not shown.

61
Exp4/Exp4.runs/synth_1/.Xil/calc_propImpl.xdc Normal file
View File

@@ -0,0 +1,61 @@
set_property SRC_FILE_INFO {cfile:F:/Schoolwork/DigitalLogic/Exp4/Exp4.srcs/constrs_1/new/calc.xdc rfile:../../../Exp4.srcs/constrs_1/new/calc.xdc id:1} [current_design]
set_property src_info {type:XDC file:1 line:30 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN P5 [get_ports {data1[3]}]
set_property src_info {type:XDC file:1 line:31 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN P4 [get_ports {data1[2]}]
set_property src_info {type:XDC file:1 line:32 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN P3 [get_ports {data1[1]}]
set_property src_info {type:XDC file:1 line:33 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN P2 [get_ports {data1[0]}]
set_property src_info {type:XDC file:1 line:34 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN R2 [get_ports {data2[3]}]
set_property src_info {type:XDC file:1 line:35 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN M4 [get_ports {data2[2]}]
set_property src_info {type:XDC file:1 line:36 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN N4 [get_ports {data2[1]}]
set_property src_info {type:XDC file:1 line:37 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN R1 [get_ports {data2[0]}]
set_property src_info {type:XDC file:1 line:38 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN F6 [get_ports {result[4]}]
set_property src_info {type:XDC file:1 line:39 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN G4 [get_ports {result[3]}]
set_property src_info {type:XDC file:1 line:40 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN G3 [get_ports {result[2]}]
set_property src_info {type:XDC file:1 line:41 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN J4 [get_ports {result[1]}]
set_property src_info {type:XDC file:1 line:42 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN H4 [get_ports {result[0]}]
set_property src_info {type:XDC file:1 line:43 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN D4 [get_ports {seg[6]}]
set_property src_info {type:XDC file:1 line:44 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN E3 [get_ports {seg[5]}]
set_property src_info {type:XDC file:1 line:45 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN D3 [get_ports {seg[4]}]
set_property src_info {type:XDC file:1 line:46 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN F4 [get_ports {seg[3]}]
set_property src_info {type:XDC file:1 line:47 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN F3 [get_ports {seg[2]}]
set_property src_info {type:XDC file:1 line:48 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN E2 [get_ports {seg[1]}]
set_property src_info {type:XDC file:1 line:49 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN D2 [get_ports {seg[0]}]
set_property src_info {type:XDC file:1 line:50 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN G1 [get_ports {seg_cs[3]}]
set_property src_info {type:XDC file:1 line:51 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN F1 [get_ports {seg_cs[2]}]
set_property src_info {type:XDC file:1 line:52 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN E1 [get_ports {seg_cs[1]}]
set_property src_info {type:XDC file:1 line:53 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN G6 [get_ports {seg_cs[0]}]
set_property src_info {type:XDC file:1 line:54 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN U4 [get_ports {type[4]}]
set_property src_info {type:XDC file:1 line:55 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN V1 [get_ports {type[3]}]
set_property src_info {type:XDC file:1 line:56 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN R15 [get_ports {type[2]}]
set_property src_info {type:XDC file:1 line:57 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN R11 [get_ports {type[1]}]
set_property src_info {type:XDC file:1 line:58 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN R17 [get_ports {type[0]}]
set_property src_info {type:XDC file:1 line:60 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN P17 [get_ports clk]

BIN
Exp4/Exp4.runs/synth_1/calc.dcp Normal file
View File

Binary file not shown.

58
Exp4/Exp4.runs/synth_1/calc.tcl Normal file
View File

@@ -0,0 +1,58 @@
#
# Synthesis run script generated by Vivado
#
proc create_report { reportName command } {
set status "."
append status $reportName ".fail"
if { [file exists $status] } {
eval file delete [glob $status]
}
send_msg_id runtcl-4 info "Executing : $command"
set retval [eval catch { $command } msg]
if { $retval != 0 } {
set fp [open $status w]
close $fp
send_msg_id runtcl-5 warning "$msg"
}
}
set_param xicom.use_bs_reader 1
create_project -in_memory -part xc7a35tcsg324-1
set_param project.singleFileAddWarning.threshold 0
set_param project.compositeFile.enableAutoGeneration 0
set_param synth.vivado.isSynthRun true
set_property webtalk.parent_dir F:/Schoolwork/DigitalLogic/Exp4/Exp4.cache/wt [current_project]
set_property parent.project_path F:/Schoolwork/DigitalLogic/Exp4/Exp4.xpr [current_project]
set_property default_lib xil_defaultlib [current_project]
set_property target_language Verilog [current_project]
set_property ip_output_repo f:/Schoolwork/DigitalLogic/Exp4/Exp4.cache/ip [current_project]
set_property ip_cache_permissions {read write} [current_project]
read_verilog -library xil_defaultlib {
F:/Schoolwork/DigitalLogic/Exp4/Exp4.srcs/sources_1/new/SegDisplayCtrl.v
F:/Schoolwork/DigitalLogic/Exp4/Exp4.srcs/sources_1/new/judge.v
F:/Schoolwork/DigitalLogic/Exp4/Exp4.srcs/sources_1/new/calc.v
}
# Mark all dcp files as not used in implementation to prevent them from being
# stitched into the results of this synthesis run. Any black boxes in the
# design are intentionally left as such for best results. Dcp files will be
# stitched into the design at a later time, either when this synthesis run is
# opened, or when it is stitched into a dependent implementation run.
foreach dcp [get_files -quiet -all -filter file_type=="Design\ Checkpoint"] {
set_property used_in_implementation false $dcp
}
read_xdc F:/Schoolwork/DigitalLogic/Exp4/Exp4.srcs/constrs_1/new/calc.xdc
set_property used_in_implementation false [get_files F:/Schoolwork/DigitalLogic/Exp4/Exp4.srcs/constrs_1/new/calc.xdc]
set_param ips.enableIPCacheLiteLoad 0
close [open __synthesis_is_running__ w]
synth_design -top calc -part xc7a35tcsg324-1
# disable binary constraint mode for synth run checkpoints
set_param constraints.enableBinaryConstraints false
write_checkpoint -force -noxdef calc.dcp
create_report "synth_1_synth_report_utilization_0" "report_utilization -file calc_utilization_synth.rpt -pb calc_utilization_synth.pb"
file delete __synthesis_is_running__
close [open __synthesis_is_complete__ w]

306
Exp4/Exp4.runs/synth_1/calc.vds Normal file
View File

@@ -0,0 +1,306 @@
#-----------------------------------------------------------
# Vivado v2018.1 (64-bit)
# SW Build 2188600 on Wed Apr 4 18:40:38 MDT 2018
# IP Build 2185939 on Wed Apr 4 20:55:05 MDT 2018
# Start of session at: Thu Nov 7 02:28:12 2024
# Process ID: 21720
# Current directory: F:/Schoolwork/DigitalLogic/Exp4/Exp4.runs/synth_1
# Command line: vivado.exe -log calc.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source calc.tcl
# Log file: F:/Schoolwork/DigitalLogic/Exp4/Exp4.runs/synth_1/calc.vds
# Journal file: F:/Schoolwork/DigitalLogic/Exp4/Exp4.runs/synth_1\vivado.jou
#-----------------------------------------------------------
source calc.tcl -notrace
Command: synth_design -top calc -part xc7a35tcsg324-1
Starting synth_design
Attempting to get a license for feature 'Synthesis' and/or device 'xc7a35t'
INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7a35t'
INFO: Launching helper process for spawning children vivado processes
INFO: Helper process launched with PID 28152
---------------------------------------------------------------------------------
Starting RTL Elaboration : Time (s): cpu = 00:00:02 ; elapsed = 00:00:03 . Memory (MB): peak = 410.371 ; gain = 97.773
---------------------------------------------------------------------------------
INFO: [Synth 8-6157] synthesizing module 'calc' [F:/Schoolwork/DigitalLogic/Exp4/Exp4.srcs/sources_1/new/calc.v:23]
INFO: [Synth 8-6157] synthesizing module 'judge' [F:/Schoolwork/DigitalLogic/Exp4/Exp4.srcs/sources_1/new/judge.v:23]
INFO: [Synth 8-6155] done synthesizing module 'judge' (1#1) [F:/Schoolwork/DigitalLogic/Exp4/Exp4.srcs/sources_1/new/judge.v:23]
INFO: [Synth 8-6157] synthesizing module 'SegDisplayCtrl' [F:/Schoolwork/DigitalLogic/Exp4/Exp4.srcs/sources_1/new/SegDisplayCtrl.v:23]
INFO: [Synth 8-6155] done synthesizing module 'SegDisplayCtrl' (2#1) [F:/Schoolwork/DigitalLogic/Exp4/Exp4.srcs/sources_1/new/SegDisplayCtrl.v:23]
INFO: [Synth 8-6155] done synthesizing module 'calc' (3#1) [F:/Schoolwork/DigitalLogic/Exp4/Exp4.srcs/sources_1/new/calc.v:23]
WARNING: [Synth 8-3917] design calc has port seg_cs[3] driven by constant 0
WARNING: [Synth 8-3917] design calc has port seg_cs[2] driven by constant 0
---------------------------------------------------------------------------------
Finished RTL Elaboration : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 465.418 ; gain = 152.820
---------------------------------------------------------------------------------
Report Check Netlist:
+------+------------------+-------+---------+-------+------------------+
| |Item |Errors |Warnings |Status |Description |
+------+------------------+-------+---------+-------+------------------+
|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets |
+------+------------------+-------+---------+-------+------------------+
---------------------------------------------------------------------------------
Start Handling Custom Attributes
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Handling Custom Attributes : Time (s): cpu = 00:00:03 ; elapsed = 00:00:04 . Memory (MB): peak = 465.418 ; gain = 152.820
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:03 ; elapsed = 00:00:04 . Memory (MB): peak = 465.418 ; gain = 152.820
---------------------------------------------------------------------------------
INFO: [Device 21-403] Loading part xc7a35tcsg324-1
INFO: [Project 1-570] Preparing netlist for logic optimization
Processing XDC Constraints
Initializing timing engine
Parsing XDC File [F:/Schoolwork/DigitalLogic/Exp4/Exp4.srcs/constrs_1/new/calc.xdc]
Finished Parsing XDC File [F:/Schoolwork/DigitalLogic/Exp4/Exp4.srcs/constrs_1/new/calc.xdc]
INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [F:/Schoolwork/DigitalLogic/Exp4/Exp4.srcs/constrs_1/new/calc.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/calc_propImpl.xdc].
Resolution: To avoid this warning, move constraints listed in [.Xil/calc_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
Completed Processing XDC Constraints
INFO: [Project 1-111] Unisim Transformation Summary:
No Unisim elements were transformed.
Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 770.922 ; gain = 0.000
---------------------------------------------------------------------------------
Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 770.922 ; gain = 458.324
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Loading Part and Timing Information
---------------------------------------------------------------------------------
Loading part: xc7a35tcsg324-1
---------------------------------------------------------------------------------
Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 770.922 ; gain = 458.324
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Applying 'set_property' XDC Constraints
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 770.922 ; gain = 458.324
---------------------------------------------------------------------------------
INFO: [Synth 8-5587] ROM size for "seg" is below threshold of ROM address width. It will be mapped to LUTs
WARNING: [Synth 8-327] inferring latch for variable 'result_reg' [F:/Schoolwork/DigitalLogic/Exp4/Exp4.srcs/sources_1/new/judge.v:29]
---------------------------------------------------------------------------------
Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 770.922 ; gain = 458.324
---------------------------------------------------------------------------------
Report RTL Partitions:
+-+--------------+------------+----------+
| |RTL Partition |Replication |Instances |
+-+--------------+------------+----------+
+-+--------------+------------+----------+
---------------------------------------------------------------------------------
Start RTL Component Statistics
---------------------------------------------------------------------------------
Detailed RTL Component Info :
+---Adders :
2 Input 5 Bit Adders := 1
+---XORs :
2 Input 5 Bit XORs := 1
+---Registers :
5 Bit Registers := 1
+---Muxes :
6 Input 7 Bit Muxes := 1
3 Input 5 Bit Muxes := 1
---------------------------------------------------------------------------------
Finished RTL Component Statistics
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start RTL Hierarchical Component Statistics
---------------------------------------------------------------------------------
Hierarchical RTL Component report
Module calc
Detailed RTL Component Info :
+---Adders :
2 Input 5 Bit Adders := 1
+---XORs :
2 Input 5 Bit XORs := 1
+---Registers :
5 Bit Registers := 1
Module judge
Detailed RTL Component Info :
+---Muxes :
3 Input 5 Bit Muxes := 1
Module SegDisplayCtrl
Detailed RTL Component Info :
+---Muxes :
6 Input 7 Bit Muxes := 1
---------------------------------------------------------------------------------
Finished RTL Hierarchical Component Statistics
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Part Resource Summary
---------------------------------------------------------------------------------
Part Resources:
DSPs: 90 (col length:60)
BRAMs: 100 (col length: RAMB18 60 RAMB36 30)
---------------------------------------------------------------------------------
Finished Part Resource Summary
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Cross Boundary and Area Optimization
---------------------------------------------------------------------------------
Warning: Parallel synthesis criteria is not met
WARNING: [Synth 8-3917] design calc has port seg_cs[3] driven by constant 0
WARNING: [Synth 8-3917] design calc has port seg_cs[2] driven by constant 0
WARNING: [Synth 8-3917] design calc has port seg_cs[1] driven by constant 0
INFO: [Synth 8-3886] merging instance 'run/result_reg[0]' (LDC) to 'run/result_reg[4]'
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\run/result_reg[4] )
WARNING: [Synth 8-3332] Sequential element (run/result_reg[4]) is unused and will be removed from module calc.
---------------------------------------------------------------------------------
Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:10 ; elapsed = 00:00:12 . Memory (MB): peak = 770.922 ; gain = 458.324
---------------------------------------------------------------------------------
Report RTL Partitions:
+-+--------------+------------+----------+
| |RTL Partition |Replication |Instances |
+-+--------------+------------+----------+
+-+--------------+------------+----------+
---------------------------------------------------------------------------------
Start Applying XDC Timing Constraints
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:15 ; elapsed = 00:00:18 . Memory (MB): peak = 786.383 ; gain = 473.785
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Timing Optimization
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Timing Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:18 . Memory (MB): peak = 786.383 ; gain = 473.785
---------------------------------------------------------------------------------
Report RTL Partitions:
+-+--------------+------------+----------+
| |RTL Partition |Replication |Instances |
+-+--------------+------------+----------+
+-+--------------+------------+----------+
---------------------------------------------------------------------------------
Start Technology Mapping
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Technology Mapping : Time (s): cpu = 00:00:15 ; elapsed = 00:00:18 . Memory (MB): peak = 786.754 ; gain = 474.156
---------------------------------------------------------------------------------
Report RTL Partitions:
+-+--------------+------------+----------+
| |RTL Partition |Replication |Instances |
+-+--------------+------------+----------+
+-+--------------+------------+----------+
---------------------------------------------------------------------------------
Start IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Flattening Before IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Flattening Before IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Final Netlist Cleanup
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Final Netlist Cleanup
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished IO Insertion : Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 787.883 ; gain = 475.285
---------------------------------------------------------------------------------
Report Check Netlist:
+------+------------------+-------+---------+-------+------------------+
| |Item |Errors |Warnings |Status |Description |
+------+------------------+-------+---------+-------+------------------+
|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets |
+------+------------------+-------+---------+-------+------------------+
---------------------------------------------------------------------------------
Start Renaming Generated Instances
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Instances : Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 787.883 ; gain = 475.285
---------------------------------------------------------------------------------
Report RTL Partitions:
+-+--------------+------------+----------+
| |RTL Partition |Replication |Instances |
+-+--------------+------------+----------+
+-+--------------+------------+----------+
---------------------------------------------------------------------------------
Start Rebuilding User Hierarchy
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 787.883 ; gain = 475.285
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Ports
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Ports : Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 787.883 ; gain = 475.285
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Handling Custom Attributes
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Handling Custom Attributes : Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 787.883 ; gain = 475.285
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Nets
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Nets : Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 787.883 ; gain = 475.285
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Writing Synthesis Report
---------------------------------------------------------------------------------
Report BlackBoxes:
+-+--------------+----------+
| |BlackBox name |Instances |
+-+--------------+----------+
+-+--------------+----------+
Report Cell Usage:
+------+-----+------+
| |Cell |Count |
+------+-----+------+
|1 |BUFG | 1|
|2 |LUT2 | 4|
|3 |LUT3 | 4|
|4 |LUT4 | 2|
|5 |LUT5 | 11|
|6 |LUT6 | 12|
|7 |FDRE | 5|
|8 |LDC | 1|
|9 |LDCP | 2|
|10 |IBUF | 14|
|11 |OBUF | 16|
+------+-----+------+
Report Instance Areas:
+------+---------+-------+------+
| |Instance |Module |Cells |
+------+---------+-------+------+
|1 |top | | 72|
|2 | run |judge | 18|
+------+---------+-------+------+
---------------------------------------------------------------------------------
Finished Writing Synthesis Report : Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 787.883 ; gain = 475.285
---------------------------------------------------------------------------------
Synthesis finished with 0 errors, 0 critical warnings and 5 warnings.
Synthesis Optimization Runtime : Time (s): cpu = 00:00:10 ; elapsed = 00:00:14 . Memory (MB): peak = 787.938 ; gain = 169.836
Synthesis Optimization Complete : Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 787.938 ; gain = 475.340
INFO: [Project 1-571] Translating synthesized netlist
INFO: [Netlist 29-17] Analyzing 17 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-570] Preparing netlist for logic optimization
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
INFO: [Project 1-111] Unisim Transformation Summary:
A total of 3 instances were transformed.
LDC => LDCE: 1 instances
LDCP => LDCP (GND, LUT3, LUT3, LDCE, VCC): 2 instances
INFO: [Common 17-83] Releasing license: Synthesis
21 Infos, 7 Warnings, 0 Critical Warnings and 0 Errors encountered.
synth_design completed successfully
synth_design: Time (s): cpu = 00:00:17 ; elapsed = 00:00:21 . Memory (MB): peak = 804.738 ; gain = 504.793
INFO: [Common 17-1381] The checkpoint 'F:/Schoolwork/DigitalLogic/Exp4/Exp4.runs/synth_1/calc.dcp' has been generated.
INFO: [runtcl-4] Executing : report_utilization -file calc_utilization_synth.rpt -pb calc_utilization_synth.pb
report_utilization: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.010 . Memory (MB): peak = 804.738 ; gain = 0.000
INFO: [Common 17-206] Exiting Vivado at Thu Nov 7 02:28:37 2024...

BIN
Exp4/Exp4.runs/synth_1/calc_utilization_synth.pb Normal file
View File

Binary file not shown.

177
Exp4/Exp4.runs/synth_1/calc_utilization_synth.rpt Normal file
View File

@@ -0,0 +1,177 @@
Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
---------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2018.1 (win64) Build 2188600 Wed Apr 4 18:40:38 MDT 2018
| Date : Thu Nov 7 02:28:37 2024
| Host : W10-20240912132 running 64-bit major release (build 9200)
| Command : report_utilization -file calc_utilization_synth.rpt -pb calc_utilization_synth.pb
| Design : calc
| Device : 7a35tcsg324-1
| Design State : Synthesized
---------------------------------------------------------------------------------------------------
Utilization Design Information
Table of Contents
-----------------
1. Slice Logic
1.1 Summary of Registers by Type
2. Memory
3. DSP
4. IO and GT Specific
5. Clocking
6. Specific Feature
7. Primitives
8. Black Boxes
9. Instantiated Netlists
1. Slice Logic
--------------
+-------------------------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+-------------------------+------+-------+-----------+-------+
| Slice LUTs* | 33 | 0 | 20800 | 0.16 |
| LUT as Logic | 33 | 0 | 20800 | 0.16 |
| LUT as Memory | 0 | 0 | 9600 | 0.00 |
| Slice Registers | 8 | 0 | 41600 | 0.02 |
| Register as Flip Flop | 5 | 0 | 41600 | 0.01 |
| Register as Latch | 3 | 0 | 41600 | <0.01 |
| F7 Muxes | 0 | 0 | 16300 | 0.00 |
| F8 Muxes | 0 | 0 | 8150 | 0.00 |
+-------------------------+------+-------+-----------+-------+
* Warning! The Final LUT count, after physical optimizations and full implementation, is typically lower. Run opt_design after synthesis, if not already completed, for a more realistic count.
1.1 Summary of Registers by Type
--------------------------------
+-------+--------------+-------------+--------------+
| Total | Clock Enable | Synchronous | Asynchronous |
+-------+--------------+-------------+--------------+
| 2 | _ | - | - |
| 0 | _ | - | Set |
| 0 | _ | - | Reset |
| 0 | _ | Set | - |
| 0 | _ | Reset | - |
| 0 | Yes | - | - |
| 0 | Yes | - | Set |
| 1 | Yes | - | Reset |
| 0 | Yes | Set | - |
| 5 | Yes | Reset | - |
+-------+--------------+-------------+--------------+
2. Memory
---------
+----------------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+----------------+------+-------+-----------+-------+
| Block RAM Tile | 0 | 0 | 50 | 0.00 |
| RAMB36/FIFO* | 0 | 0 | 50 | 0.00 |
| RAMB18 | 0 | 0 | 100 | 0.00 |
+----------------+------+-------+-----------+-------+
* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1
3. DSP
------
+-----------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+-----------+------+-------+-----------+-------+
| DSPs | 0 | 0 | 90 | 0.00 |
+-----------+------+-------+-----------+-------+
4. IO and GT Specific
---------------------
+-----------------------------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+-----------------------------+------+-------+-----------+-------+
| Bonded IOB | 30 | 0 | 210 | 14.29 |
| Bonded IPADs | 0 | 0 | 2 | 0.00 |
| PHY_CONTROL | 0 | 0 | 5 | 0.00 |
| PHASER_REF | 0 | 0 | 5 | 0.00 |
| OUT_FIFO | 0 | 0 | 20 | 0.00 |
| IN_FIFO | 0 | 0 | 20 | 0.00 |
| IDELAYCTRL | 0 | 0 | 5 | 0.00 |
| IBUFDS | 0 | 0 | 202 | 0.00 |
| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 20 | 0.00 |
| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 20 | 0.00 |
| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 250 | 0.00 |
| ILOGIC | 0 | 0 | 210 | 0.00 |
| OLOGIC | 0 | 0 | 210 | 0.00 |
+-----------------------------+------+-------+-----------+-------+
5. Clocking
-----------
+------------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+------------+------+-------+-----------+-------+
| BUFGCTRL | 1 | 0 | 32 | 3.13 |
| BUFIO | 0 | 0 | 20 | 0.00 |
| MMCME2_ADV | 0 | 0 | 5 | 0.00 |
| PLLE2_ADV | 0 | 0 | 5 | 0.00 |
| BUFMRCE | 0 | 0 | 10 | 0.00 |
| BUFHCE | 0 | 0 | 72 | 0.00 |
| BUFR | 0 | 0 | 20 | 0.00 |
+------------+------+-------+-----------+-------+
6. Specific Feature
-------------------
+-------------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+-------------+------+-------+-----------+-------+
| BSCANE2 | 0 | 0 | 4 | 0.00 |
| CAPTUREE2 | 0 | 0 | 1 | 0.00 |
| DNA_PORT | 0 | 0 | 1 | 0.00 |
| EFUSE_USR | 0 | 0 | 1 | 0.00 |
| FRAME_ECCE2 | 0 | 0 | 1 | 0.00 |
| ICAPE2 | 0 | 0 | 2 | 0.00 |
| PCIE_2_1 | 0 | 0 | 1 | 0.00 |
| STARTUPE2 | 0 | 0 | 1 | 0.00 |
| XADC | 0 | 0 | 1 | 0.00 |
+-------------+------+-------+-----------+-------+
7. Primitives
-------------
+----------+------+---------------------+
| Ref Name | Used | Functional Category |
+----------+------+---------------------+
| OBUF | 16 | IO |
| IBUF | 14 | IO |
| LUT6 | 12 | LUT |
| LUT5 | 11 | LUT |
| LUT3 | 8 | LUT |
| FDRE | 5 | Flop & Latch |
| LUT2 | 4 | LUT |
| LDCE | 3 | Flop & Latch |
| LUT4 | 2 | LUT |
| BUFG | 1 | Clock |
+----------+------+---------------------+
8. Black Boxes
--------------
+----------+------+
| Ref Name | Used |
+----------+------+
9. Instantiated Netlists
------------------------
+----------+------+
| Ref Name | Used |
+----------+------+

55
Exp4/Exp4.runs/synth_1/gen_run.xml Normal file
View File

@@ -0,0 +1,55 @@
<?xml version="1.0" encoding="UTF-8"?>
<GenRun Id="synth_1" LaunchPart="xc7a35tcsg324-1" LaunchTime="1730917691">
<File Type="PA-TCL" Name="calc.tcl"/>
<File Type="REPORTS-TCL" Name="calc_reports.tcl"/>
<File Type="RDS-RDS" Name="calc.vds"/>
<File Type="RDS-UTIL" Name="calc_utilization_synth.rpt"/>
<File Type="RDS-UTIL-PB" Name="calc_utilization_synth.pb"/>
<File Type="RDS-DCP" Name="calc.dcp"/>
<FileSet Name="sources" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1">
<Filter Type="Srcs"/>
<File Path="$PSRCDIR/sources_1/new/SegDisplayCtrl.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/new/judge.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/new/calc.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<Config>
<Option Name="DesignMode" Val="RTL"/>
<Option Name="TopModule" Val="calc"/>
<Option Name="TopAutoSet" Val="TRUE"/>
</Config>
</FileSet>
<FileSet Name="constrs_in" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1">
<Filter Type="Constrs"/>
<File Path="$PSRCDIR/constrs_1/new/calc.xdc">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
</FileInfo>
</File>
<Config>
<Option Name="TargetConstrsFile" Val="$PSRCDIR/constrs_1/new/calc.xdc"/>
<Option Name="ConstrsType" Val="XDC"/>
</Config>
</FileSet>
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2018"/>
<Step Id="synth_design"/>
</Strategy>
</GenRun>

9
Exp4/Exp4.runs/synth_1/htr.txt Normal file
View File

@@ -0,0 +1,9 @@
REM
REM Vivado(TM)
REM htr.txt: a Vivado-generated description of how-to-repeat the
REM the basic steps of a run. Note that runme.bat/sh needs
REM to be invoked for Vivado to track run status.
REM Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
REM
vivado -log calc.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source calc.tcl

12
Exp4/Exp4.runs/synth_1/vivado.jou Normal file
View File

@@ -0,0 +1,12 @@
#-----------------------------------------------------------
# Vivado v2018.1 (64-bit)
# SW Build 2188600 on Wed Apr 4 18:40:38 MDT 2018
# IP Build 2185939 on Wed Apr 4 20:55:05 MDT 2018
# Start of session at: Thu Nov 7 02:28:12 2024
# Process ID: 21720
# Current directory: F:/Schoolwork/DigitalLogic/Exp4/Exp4.runs/synth_1
# Command line: vivado.exe -log calc.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source calc.tcl
# Log file: F:/Schoolwork/DigitalLogic/Exp4/Exp4.runs/synth_1/calc.vds
# Journal file: F:/Schoolwork/DigitalLogic/Exp4/Exp4.runs/synth_1\vivado.jou
#-----------------------------------------------------------
source calc.tcl -notrace

BIN
Exp4/Exp4.runs/synth_1/vivado.pb Normal file
View File

Binary file not shown.

11
Exp4/Exp4.sim/sim_1/behav/xsim/calc_tb.tcl Normal file
View File

@@ -0,0 +1,11 @@
set curr_wave [current_wave_config]
if { [string length $curr_wave] == 0 } {
if { [llength [get_objects]] > 0} {
add_wave /
set_property needs_save false [current_wave_config]
} else {
send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
}
}
run 1000ns

12
Exp4/Exp4.sim/sim_1/behav/xsim/calc_tb_vlog.prj Normal file
View File

@@ -0,0 +1,12 @@
# compile verilog/system verilog design source files
verilog xil_defaultlib \
"../../../../Exp4.srcs/sources_1/new/SegDisplayCtrl.v" \
"../../../../Exp4.srcs/sources_1/new/calc.v" \
"../../../../Exp4.srcs/sources_1/new/judge.v" \
"../../../../Exp4.srcs/sim_1/new/calc_tb.v" \
# compile glbl module
verilog xil_defaultlib "glbl.v"
# Do not sort compile order
nosort

71
Exp4/Exp4.sim/sim_1/behav/xsim/glbl.v Normal file
View File

@@ -0,0 +1,71 @@
// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (strong1, weak0) GSR = GSR_int;
assign (strong1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif

12
Exp4/Exp4.sim/sim_1/behav/xsim/webtalk.jou Normal file
View File

@@ -0,0 +1,12 @@
#-----------------------------------------------------------
# Webtalk v2018.1 (64-bit)
# SW Build 2188600 on Wed Apr 4 18:40:38 MDT 2018
# IP Build 2185939 on Wed Apr 4 20:55:05 MDT 2018
# Start of session at: Wed Nov 13 22:33:02 2024
# Process ID: 36096
# Current directory: F:/Schoolwork/DigitalLogic/Exp4/Exp4.sim/sim_1/behav/xsim
# Command line: wbtcv.exe -mode batch -source F:/Schoolwork/DigitalLogic/Exp4/Exp4.sim/sim_1/behav/xsim/xsim.dir/calc_tb_behav/webtalk/xsim_webtalk.tcl -notrace
# Log file: F:/Schoolwork/DigitalLogic/Exp4/Exp4.sim/sim_1/behav/xsim/webtalk.log
# Journal file: F:/Schoolwork/DigitalLogic/Exp4/Exp4.sim/sim_1/behav/xsim\webtalk.jou
#-----------------------------------------------------------
source F:/Schoolwork/DigitalLogic/Exp4/Exp4.sim/sim_1/behav/xsim/xsim.dir/calc_tb_behav/webtalk/xsim_webtalk.tcl -notrace

12
Exp4/Exp4.sim/sim_1/behav/xsim/webtalk_35820.backup.jou Normal file
View File

@@ -0,0 +1,12 @@
#-----------------------------------------------------------
# Webtalk v2018.1 (64-bit)
# SW Build 2188600 on Wed Apr 4 18:40:38 MDT 2018
# IP Build 2185939 on Wed Apr 4 20:55:05 MDT 2018
# Start of session at: Wed Nov 13 22:26:32 2024
# Process ID: 35820
# Current directory: F:/Schoolwork/DigitalLogic/Exp4/Exp4.sim/sim_1/behav/xsim
# Command line: wbtcv.exe -mode batch -source F:/Schoolwork/DigitalLogic/Exp4/Exp4.sim/sim_1/behav/xsim/xsim.dir/calc_tb_behav/webtalk/xsim_webtalk.tcl -notrace
# Log file: F:/Schoolwork/DigitalLogic/Exp4/Exp4.sim/sim_1/behav/xsim/webtalk.log
# Journal file: F:/Schoolwork/DigitalLogic/Exp4/Exp4.sim/sim_1/behav/xsim\webtalk.jou
#-----------------------------------------------------------
source F:/Schoolwork/DigitalLogic/Exp4/Exp4.sim/sim_1/behav/xsim/xsim.dir/calc_tb_behav/webtalk/xsim_webtalk.tcl -notrace

BIN
Exp4/Exp4.sim/sim_1/behav/xsim/xelab.pb Normal file
View File

Binary file not shown.

1
Exp4/Exp4.sim/sim_1/behav/xsim/xsim.dir/calc_tb_behav/Compile_Options.txt Normal file
View File

@@ -0,0 +1 @@
-wto "56490f59f5644a478a040843011181be" --incr --debug "typical" --relax --mt "2" -L "xil_defaultlib" -L "unisims_ver" -L "unimacro_ver" -L "secureip" --snapshot "calc_tb_behav" "xil_defaultlib.calc_tb" "xil_defaultlib.glbl" -log "elaborate.log"

1
Exp4/Exp4.sim/sim_1/behav/xsim/xsim.dir/calc_tb_behav/TempBreakPointFile.txt Normal file
View File

@@ -0,0 +1 @@
Breakpoint File Version 1.0

119
Exp4/Exp4.sim/sim_1/behav/xsim/xsim.dir/calc_tb_behav/obj/xsim_1.c Normal file
View File

@@ -0,0 +1,119 @@
/**********************************************************************/
/* ____ ____ */
/* / /\/ / */
/* /___/ \ / */
/* \ \ \/ */
/* \ \ Copyright (c) 2003-2013 Xilinx, Inc. */
/* / / All Right Reserved. */
/* /---/ /\ */
/* \ \ / \ */
/* \___\/\___\ */
/**********************************************************************/
#include "iki.h"
#include <string.h>
#include <math.h>
#ifdef __GNUC__
#include <stdlib.h>
#else
#include <malloc.h>
#define alloca _alloca
#endif
/**********************************************************************/
/* ____ ____ */
/* / /\/ / */
/* /___/ \ / */
/* \ \ \/ */
/* \ \ Copyright (c) 2003-2013 Xilinx, Inc. */
/* / / All Right Reserved. */
/* /---/ /\ */
/* \ \ / \ */
/* \___\/\___\ */
/**********************************************************************/
#include "iki.h"
#include <string.h>
#include <math.h>
#ifdef __GNUC__
#include <stdlib.h>
#else
#include <malloc.h>
#define alloca _alloca
#endif
typedef void (*funcp)(char *, char *);
extern int main(int, char**);
extern void execute_10(char*, char *);
extern void execute_11(char*, char *);
extern void execute_19(char*, char *);
extern void execute_20(char*, char *);
extern void execute_21(char*, char *);
extern void execute_22(char*, char *);
extern void execute_23(char*, char *);
extern void execute_24(char*, char *);
extern void execute_5(char*, char *);
extern void execute_6(char*, char *);
extern void execute_9(char*, char *);
extern void execute_16(char*, char *);
extern void execute_17(char*, char *);
extern void execute_18(char*, char *);
extern void execute_4(char*, char *);
extern void execute_8(char*, char *);
extern void execute_13(char*, char *);
extern void execute_14(char*, char *);
extern void execute_15(char*, char *);
extern void execute_25(char*, char *);
extern void execute_26(char*, char *);
extern void execute_27(char*, char *);
extern void execute_28(char*, char *);
extern void execute_29(char*, char *);
extern void vlog_transfunc_eventcallback(char*, char*, unsigned, unsigned, unsigned, char *);
funcp funcTab[25] = {(funcp)execute_10, (funcp)execute_11, (funcp)execute_19, (funcp)execute_20, (funcp)execute_21, (funcp)execute_22, (funcp)execute_23, (funcp)execute_24, (funcp)execute_5, (funcp)execute_6, (funcp)execute_9, (funcp)execute_16, (funcp)execute_17, (funcp)execute_18, (funcp)execute_4, (funcp)execute_8, (funcp)execute_13, (funcp)execute_14, (funcp)execute_15, (funcp)execute_25, (funcp)execute_26, (funcp)execute_27, (funcp)execute_28, (funcp)execute_29, (funcp)vlog_transfunc_eventcallback};
const int NumRelocateId= 25;
void relocate(char *dp)
{
iki_relocate(dp, "xsim.dir/calc_tb_behav/xsim.reloc", (void **)funcTab, 25);
/*Populate the transaction function pointer field in the whole net structure */
}
void sensitize(char *dp)
{
iki_sensitize(dp, "xsim.dir/calc_tb_behav/xsim.reloc");
}
void simulate(char *dp)
{
iki_schedule_processes_at_time_zero(dp, "xsim.dir/calc_tb_behav/xsim.reloc");
// Initialize Verilog nets in mixed simulation, for the cases when the value at time 0 should be propagated from the mixed language Vhdl net
iki_execute_processes();
// Schedule resolution functions for the multiply driven Verilog nets that have strength
// Schedule transaction functions for the singly driven Verilog nets that have strength
}
#include "iki_bridge.h"
void relocate(char *);
void sensitize(char *);
void simulate(char *);
extern SYSTEMCLIB_IMP_DLLSPEC void local_register_implicit_channel(int, char*);
extern void implicit_HDL_SCinstatiate();
extern int xsim_argc_copy ;
extern char** xsim_argv_copy ;
int main(int argc, char **argv)
{
iki_heap_initialize("ms", "isimmm", 0, 2147483648) ;
iki_set_sv_type_file_path_name("xsim.dir/calc_tb_behav/xsim.svtype");
iki_set_crvs_dump_file_path_name("xsim.dir/calc_tb_behav/xsim.crvsdump");
void* design_handle = iki_create_design("xsim.dir/calc_tb_behav/xsim.mem", (void *)relocate, (void *)sensitize, (void *)simulate, 0, isimBridge_getWdbWriter(), 0, argc, argv);
iki_set_rc_trial_count(100);
(void) design_handle;
return iki_simulate_design();
}

BIN
Exp4/Exp4.sim/sim_1/behav/xsim/xsim.dir/calc_tb_behav/xsim.mem Normal file
View File

Binary file not shown.

BIN
Exp4/Exp4.sim/sim_1/behav/xsim/xvlog.pb Normal file
View File

Binary file not shown.

61
Exp4/Exp4.srcs/constrs_1/new/calc.xdc Normal file
View File

@@ -0,0 +1,61 @@
set_property IOSTANDARD LVCMOS33 [get_ports {data1[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {data1[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {data1[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {data1[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {data2[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {data2[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {data2[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {data2[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {result[4]}]
set_property IOSTANDARD LVCMOS33 [get_ports {result[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {result[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {result[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {result[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {seg[6]}]
set_property IOSTANDARD LVCMOS33 [get_ports {seg[5]}]
set_property IOSTANDARD LVCMOS33 [get_ports {seg[4]}]
set_property IOSTANDARD LVCMOS33 [get_ports {seg[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {seg[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {seg[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {seg[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {seg_cs[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {seg_cs[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {seg_cs[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {seg_cs[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {type[4]}]
set_property IOSTANDARD LVCMOS33 [get_ports {type[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {type[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {type[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {type[0]}]
set_property PACKAGE_PIN P5 [get_ports {data1[3]}]
set_property PACKAGE_PIN P4 [get_ports {data1[2]}]
set_property PACKAGE_PIN P3 [get_ports {data1[1]}]
set_property PACKAGE_PIN P2 [get_ports {data1[0]}]
set_property PACKAGE_PIN R2 [get_ports {data2[3]}]
set_property PACKAGE_PIN M4 [get_ports {data2[2]}]
set_property PACKAGE_PIN N4 [get_ports {data2[1]}]
set_property PACKAGE_PIN R1 [get_ports {data2[0]}]
set_property PACKAGE_PIN F6 [get_ports {result[4]}]
set_property PACKAGE_PIN G4 [get_ports {result[3]}]
set_property PACKAGE_PIN G3 [get_ports {result[2]}]
set_property PACKAGE_PIN J4 [get_ports {result[1]}]
set_property PACKAGE_PIN H4 [get_ports {result[0]}]
set_property PACKAGE_PIN D4 [get_ports {seg[6]}]
set_property PACKAGE_PIN E3 [get_ports {seg[5]}]
set_property PACKAGE_PIN D3 [get_ports {seg[4]}]
set_property PACKAGE_PIN F4 [get_ports {seg[3]}]
set_property PACKAGE_PIN F3 [get_ports {seg[2]}]
set_property PACKAGE_PIN E2 [get_ports {seg[1]}]
set_property PACKAGE_PIN D2 [get_ports {seg[0]}]
set_property PACKAGE_PIN G1 [get_ports {seg_cs[3]}]
set_property PACKAGE_PIN F1 [get_ports {seg_cs[2]}]
set_property PACKAGE_PIN E1 [get_ports {seg_cs[1]}]
set_property PACKAGE_PIN G6 [get_ports {seg_cs[0]}]
set_property PACKAGE_PIN U4 [get_ports {type[4]}]
set_property PACKAGE_PIN V1 [get_ports {type[3]}]
set_property PACKAGE_PIN R15 [get_ports {type[2]}]
set_property PACKAGE_PIN R11 [get_ports {type[1]}]
set_property PACKAGE_PIN R17 [get_ports {type[0]}]
set_property PACKAGE_PIN P17 [get_ports clk]
set_property IOSTANDARD LVCMOS33 [get_ports clk]

60
Exp4/Exp4.srcs/sim_1/new/calc_tb.v Normal file
View File

@@ -0,0 +1,60 @@
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2024/11/13 22:21:16
// Design Name:
// Module Name: calc_tb
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module calc_tb();
reg [3:0] data1;
reg [3:0] data2;
reg [4:0] type;
reg clk;
wire [4:0] result;
wire [6:0] seg;
wire [3:0] seg_cs;
calc uut (
.data1(data1),
.data2(data2),
.type(type),
.clk(clk),
.result(result),
.seg(seg),
.seg_cs(seg_cs)
);
initial begin
clk = 0;
forever #5 clk = ~clk; // Clock signal
end
initial begin
data1 = 4'b0011;
data2 = 4'b0101;
type = 5'b10000; #10; // Plus
type = 5'b01000; #10; // AND
type = 5'b00100; #10; // OR
type = 5'b00010; #10; // XOR
type = 5'b00001; #10; // Judge 1 <
data1 = 4'b0101;
data2 = 4'b0011;
type = 5'b00001; #10; // Judge 2 >
data1 = 4'b0101;
data2 = 4'b0101;
type = 5'b00001; #10; // Judge 3 =
$stop;
end
endmodule

37
Exp4/Exp4.srcs/sources_1/new/SegDisplayCtrl.v Normal file
View File

@@ -0,0 +1,37 @@
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2024/10/31 11:26:14
// Design Name:
// Module Name: SegDisplayCtrl
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module SegDisplayCtrl(
input wire [4:0] type,
output reg [6:0] seg
);
always @(*) begin
case (type)
5'b10000: seg = 7'b1110111; // a
5'b01000: seg = 7'b0011111; // b
5'b00100: seg = 7'b1001110; // c
5'b00010: seg = 7'b0111101; // d
5'b00001: seg = 7'b1001111; // e
default: seg = 7'b0000000;
endcase
end
endmodule

51
Exp4/Exp4.srcs/sources_1/new/calc.v Normal file
View File

@@ -0,0 +1,51 @@
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2024/10/31 10:43:01
// Design Name:
// Module Name: calc
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module calc(
input [3:0] data1,
input [3:0] data2,
input [4:0] type,
input clk,
output reg [4:0] result,
output wire [6:0] seg,
output reg [3:0] seg_cs
);
reg [4:0] stored_type = 5'b00000;
wire [4:0] judge_result;
wire [4:0] operation_result;
judge run (.data1(data1), .data2(data2), .result(judge_result));
always @(posedge clk) begin
if (type != 5'b00000) stored_type <= type;
end
always @(*) begin
case (stored_type)
5'b10000: result = data1 + data2;
5'b01000: result = data1 & data2;
5'b00100: result = data1 | data2;
5'b00010: result = data1 ^ data2;
5'b00001: result = judge_result;
default: result = 5'b00000;
endcase
seg_cs = (stored_type != 5'b00000) ? 4'b0001 : 4'b0000;
end
SegDisplayCtrl unit (.type(stored_type), .seg(seg));
endmodule

33
Exp4/Exp4.srcs/sources_1/new/judge.v Normal file
View File

@@ -0,0 +1,33 @@
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2024/10/31 11:22:30
// Design Name:
// Module Name: judge
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module judge(
input [3:0] data1,
input [3:0] data2,
output reg [4:0] result
);
always @(*) begin
if (data1 > data2) result = 4'b1000;
else if (data1 < data2) result = 4'b0100;
else if (data1 == data2) result = 4'b0010;
end
endmodule

165
Exp4/Exp4.xpr Normal file
View File

@@ -0,0 +1,165 @@
<?xml version="1.0" encoding="UTF-8"?>
<!-- Product Version: Vivado v2018.1 (64-bit) -->
<!-- -->
<!-- Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. -->
<Project Version="7" Minor="36" Path="F:/Schoolwork/DigitalLogic/Exp4/Exp4.xpr">
<DefaultLaunch Dir="$PRUNDIR"/>
<Configuration>
<Option Name="Id" Val="56490f59f5644a478a040843011181be"/>
<Option Name="Part" Val="xc7a35tcsg324-1"/>
<Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
<Option Name="CompiledLibDirXSim" Val=""/>
<Option Name="CompiledLibDirModelSim" Val="$PCACHEDIR/compile_simlib/modelsim"/>
<Option Name="CompiledLibDirQuesta" Val="$PCACHEDIR/compile_simlib/questa"/>
<Option Name="CompiledLibDirIES" Val="$PCACHEDIR/compile_simlib/ies"/>
<Option Name="CompiledLibDirXcelium" Val="$PCACHEDIR/compile_simlib/xcelium"/>
<Option Name="CompiledLibDirVCS" Val="$PCACHEDIR/compile_simlib/vcs"/>
<Option Name="CompiledLibDirRiviera" Val="$PCACHEDIR/compile_simlib/riviera"/>
<Option Name="CompiledLibDirActivehdl" Val="$PCACHEDIR/compile_simlib/activehdl"/>
<Option Name="BoardPart" Val=""/>
<Option Name="ActiveSimSet" Val="sim_1"/>
<Option Name="DefaultLib" Val="xil_defaultlib"/>
<Option Name="ProjectType" Val="Default"/>
<Option Name="IPOutputRepo" Val="$PCACHEDIR/ip"/>
<Option Name="IPCachePermission" Val="read"/>
<Option Name="IPCachePermission" Val="write"/>
<Option Name="EnableCoreContainer" Val="FALSE"/>
<Option Name="CreateRefXciForCoreContainers" Val="FALSE"/>
<Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
<Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
<Option Name="EnableBDX" Val="FALSE"/>
<Option Name="DSAVendor" Val="xilinx"/>
<Option Name="DSANumComputeUnits" Val="60"/>
<Option Name="WTXSimLaunchSim" Val="1"/>
<Option Name="WTModelSimLaunchSim" Val="0"/>
<Option Name="WTQuestaLaunchSim" Val="0"/>
<Option Name="WTIesLaunchSim" Val="0"/>
<Option Name="WTVcsLaunchSim" Val="0"/>
<Option Name="WTRivieraLaunchSim" Val="0"/>
<Option Name="WTActivehdlLaunchSim" Val="0"/>
<Option Name="WTXSimExportSim" Val="0"/>
<Option Name="WTModelSimExportSim" Val="0"/>
<Option Name="WTQuestaExportSim" Val="0"/>
<Option Name="WTIesExportSim" Val="0"/>
<Option Name="WTVcsExportSim" Val="0"/>
<Option Name="WTRivieraExportSim" Val="0"/>
<Option Name="WTActivehdlExportSim" Val="0"/>
<Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
<Option Name="XSimRadix" Val="hex"/>
<Option Name="XSimTimeUnit" Val="ns"/>
<Option Name="XSimArrayDisplayLimit" Val="1024"/>
<Option Name="XSimTraceLimit" Val="65536"/>
<Option Name="SimTypes" Val="rtl"/>
</Configuration>
<FileSets Version="1" Minor="31">
<FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1">
<Filter Type="Srcs"/>
<File Path="$PSRCDIR/sources_1/new/SegDisplayCtrl.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/new/judge.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/new/calc.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<Config>
<Option Name="DesignMode" Val="RTL"/>
<Option Name="TopModule" Val="calc"/>
<Option Name="TopAutoSet" Val="TRUE"/>
</Config>
</FileSet>
<FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1">
<Filter Type="Constrs"/>
<File Path="$PSRCDIR/constrs_1/new/calc.xdc">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
</FileInfo>
</File>
<Config>
<Option Name="TargetConstrsFile" Val="$PSRCDIR/constrs_1/new/calc.xdc"/>
<Option Name="ConstrsType" Val="XDC"/>
</Config>
</FileSet>
<FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1">
<Filter Type="Srcs"/>
<File Path="$PSRCDIR/sim_1/new/calc_tb.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<Config>
<Option Name="DesignMode" Val="RTL"/>
<Option Name="TopModule" Val="calc_tb"/>
<Option Name="TopLib" Val="xil_defaultlib"/>
<Option Name="TopAutoSet" Val="TRUE"/>
<Option Name="TransportPathDelay" Val="0"/>
<Option Name="TransportIntDelay" Val="0"/>
<Option Name="SrcSet" Val="sources_1"/>
</Config>
</FileSet>
</FileSets>
<Simulators>
<Simulator Name="XSim">
<Option Name="Description" Val="Vivado Simulator"/>
<Option Name="CompiledLib" Val="0"/>
</Simulator>
<Simulator Name="ModelSim">
<Option Name="Description" Val="ModelSim Simulator"/>
</Simulator>
<Simulator Name="Questa">
<Option Name="Description" Val="Questa Advanced Simulator"/>
</Simulator>
<Simulator Name="Riviera">
<Option Name="Description" Val="Riviera-PRO Simulator"/>
</Simulator>
<Simulator Name="ActiveHDL">
<Option Name="Description" Val="Active-HDL Simulator"/>
</Simulator>
</Simulators>
<Runs Version="1" Minor="10">
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a35tcsg324-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2018"/>
<Step Id="synth_design"/>
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2018"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
</Run>
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcsg324-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1" IncludeInArchive="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2018"/>
<Step Id="init_design"/>
<Step Id="opt_design"/>
<Step Id="power_opt_design"/>
<Step Id="place_design"/>
<Step Id="post_place_power_opt_design"/>
<Step Id="phys_opt_design"/>
<Step Id="route_design"/>
<Step Id="post_route_phys_opt_design"/>
<Step Id="write_bitstream"/>
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2018"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
</Run>
</Runs>
<Board/>
</Project>

14
Exp4/vivado.jou Normal file
View File

@@ -0,0 +1,14 @@
#-----------------------------------------------------------
# Vivado v2018.1 (64-bit)
# SW Build 2188600 on Wed Apr 4 18:40:38 MDT 2018
# IP Build 2185939 on Wed Apr 4 20:55:05 MDT 2018
# Start of session at: Mon Dec 2 10:27:41 2024
# Process ID: 18304
# Current directory: F:/Schoolwork/DigitalLogic/Exp4
# Command line: vivado.exe -gui_launcher_event rodinguilauncherevent11156 F:\Schoolwork\DigitalLogic\Exp4\Exp4.xpr
# Log file: F:/Schoolwork/DigitalLogic/Exp4/vivado.log
# Journal file: F:/Schoolwork/DigitalLogic/Exp4\vivado.jou
#-----------------------------------------------------------
start_gui
open_project F:/Schoolwork/DigitalLogic/Exp4/Exp4.xpr
update_compile_order -fileset sources_1

14
Exp4/vivado_19868.backup.jou Normal file
View File

@@ -0,0 +1,14 @@
#-----------------------------------------------------------
# Vivado v2018.1 (64-bit)
# SW Build 2188600 on Wed Apr 4 18:40:38 MDT 2018
# IP Build 2185939 on Wed Apr 4 20:55:05 MDT 2018
# Start of session at: Sun Dec 1 21:44:01 2024
# Process ID: 19868
# Current directory: F:/Schoolwork/DigitalLogic/Exp4
# Command line: vivado.exe -gui_launcher_event rodinguilauncherevent8772 F:\Schoolwork\DigitalLogic\Exp4\Exp4.xpr
# Log file: F:/Schoolwork/DigitalLogic/Exp4/vivado.log
# Journal file: F:/Schoolwork/DigitalLogic/Exp4\vivado.jou
#-----------------------------------------------------------
start_gui
open_project F:/Schoolwork/DigitalLogic/Exp4/Exp4.xpr
update_compile_order -fileset sources_1

44
Exp4/vivado_26344.backup.jou Normal file
View File

@@ -0,0 +1,44 @@
#-----------------------------------------------------------
# Vivado v2018.1 (64-bit)
# SW Build 2188600 on Wed Apr 4 18:40:38 MDT 2018
# IP Build 2185939 on Wed Apr 4 20:55:05 MDT 2018
# Start of session at: Wed Nov 13 21:13:18 2024
# Process ID: 26344
# Current directory: F:/Schoolwork/DigitalLogic/Exp4
# Command line: vivado.exe -gui_launcher_event rodinguilauncherevent29944 F:\Schoolwork\DigitalLogic\Exp4\Exp4.xpr
# Log file: F:/Schoolwork/DigitalLogic/Exp4/vivado.log
# Journal file: F:/Schoolwork/DigitalLogic/Exp4\vivado.jou
#-----------------------------------------------------------
start_gui
open_project F:/Schoolwork/DigitalLogic/Exp4/Exp4.xpr
update_compile_order -fileset sources_1
open_hw
connect_hw_server
refresh_hw_server {localhost:3121}
open_hw_target {localhost:3121/xilinx_tcf/Xilinx/1234-tulA}
set_property PROGRAM.FILE {F:/Schoolwork/DigitalLogic/Exp4/Exp4.runs/impl_1/calc.bit} [get_hw_devices xc7a35t_0]
current_hw_device [get_hw_devices xc7a35t_0]
refresh_hw_device -update_hw_probes false [lindex [get_hw_devices xc7a35t_0] 0]
set_property PROBES.FILE {} [get_hw_devices xc7a35t_0]
set_property FULL_PROBES.FILE {} [get_hw_devices xc7a35t_0]
set_property PROGRAM.FILE {F:/Schoolwork/DigitalLogic/Exp4/Exp4.runs/impl_1/calc.bit} [get_hw_devices xc7a35t_0]
program_hw_devices [get_hw_devices xc7a35t_0]
refresh_hw_device [lindex [get_hw_devices xc7a35t_0] 0]
close_hw
file mkdir F:/Schoolwork/DigitalLogic/Exp4/Exp4.srcs/sim_1/new
set_property SOURCE_SET sources_1 [get_filesets sim_1]
close [ open F:/Schoolwork/DigitalLogic/Exp4/Exp4.srcs/sim_1/new/calc_tb.v w ]
add_files -fileset sim_1 F:/Schoolwork/DigitalLogic/Exp4/Exp4.srcs/sim_1/new/calc_tb.v
update_compile_order -fileset sim_1
update_compile_order -fileset sim_1
launch_simulation
source calc_tb.tcl
synth_design -rtl -name rtl_1
close_sim
open_hw
connect_hw_server
open_hw_target
set_property PROGRAM.FILE {F:/Schoolwork/DigitalLogic/Exp4/Exp4.runs/impl_1/calc.bit} [get_hw_devices xc7a35t_0]
current_hw_device [get_hw_devices xc7a35t_0]
refresh_hw_device -update_hw_probes false [lindex [get_hw_devices xc7a35t_0] 0]
close_hw_target {localhost:3121/xilinx_tcf/Xilinx/1234-tulA}