Initial commit

Exp5-1/Exp5-1.srcs/sim_1/new/DFlipFlop_tb.v

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+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date: 2024/11/24 20:30:43
+// Design Name: 
+// Module Name: DFlipFlop_tb
+// Project Name: 
+// Target Devices: 
+// Tool Versions: 
+// Description: 
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module DFlipFlop_tb;
+    reg D, clk;
+    wire Q;
+DFlipFlop uut (
+    .D(D),
+    .clk(clk),
+    .Q(Q)
+);
+initial begin
+    clk = 0;
+    forever #10 clk = ~clk;
+end
+initial begin
+    D = 0; #15;
+    D = 1; #20;
+    D = 0; #20;
+    $stop;
+end
+endmodule

Exp5-1/Exp5-1.srcs/sources_1/new/DFlipFlop.v

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+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date: 2024/11/24 20:29:26
+// Design Name: 
+// Module Name: DFlipFlop
+// Project Name: 
+// Target Devices: 
+// Tool Versions: 
+// Description: 
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module DFlipFlop (
+    input wire D,
+    input wire clk,
+    output reg Q
+);
+always @(posedge clk) begin
+    Q <= D;
+end
+endmodule