launchcore/DigitalLogic
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

Initial commit

Browse Source
This commit is contained in:
綾瀬桃桃
2025-11-06 10:08:01 +08:00
commit 0bded5b86e
1033 changed files with 55966 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

45
Exp5-3/Exp5-3.cache/wt/webtalk_pa.xml Normal file
View File

@@ -0,0 +1,45 @@
<?xml version="1.0" encoding="UTF-8" ?>
<document>
<!--The data in this file is primarily intended for consumption by Xilinx tools.
The structure and the elements are likely to change over the next few releases.
This means code written to parse this file will need to be revisited each subsequent release.-->
<application name="pa" timeStamp="Mon Dec 2 10:47:20 2024">
<section name="Project Information" visible="false">
<property name="ProjectID" value="420678297f754bc69b1b150e9ad76a63" type="ProjectID"/>
<property name="ProjectIteration" value="1" type="ProjectIteration"/>
</section>
<section name="PlanAhead Usage" visible="true">
<item name="Project Data">
<property name="SrcSetCount" value="1" type="SrcSetCount"/>
<property name="ConstraintSetCount" value="1" type="ConstraintSetCount"/>
<property name="DesignMode" value="RTL" type="DesignMode"/>
<property name="SynthesisStrategy" value="Vivado Synthesis Defaults" type="SynthesisStrategy"/>
<property name="ImplStrategy" value="Vivado Implementation Defaults" type="ImplStrategy"/>
</item>
<item name="Java Command Handlers">
<property name="AddSources" value="2" type="JavaHandler"/>
<property name="NewProject" value="1" type="JavaHandler"/>
<property name="SimulationRun" value="1" type="JavaHandler"/>
</item>
<item name="Gui Handlers">
<property name="AddSrcWizard_SPECIFY_SIMULATION_SPECIFIC_HDL_FILES" value="1" type="GuiHandlerData"/>
<property name="BaseDialog_OK" value="4" type="GuiHandlerData"/>
<property name="CreateSrcFileDialog_FILE_NAME" value="2" type="GuiHandlerData"/>
<property name="FPGAChooser_FPGA_TABLE" value="1" type="GuiHandlerData"/>
<property name="FileSetPanel_FILE_SET_PANEL_TREE" value="7" type="GuiHandlerData"/>
<property name="FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE" value="3" type="GuiHandlerData"/>
<property name="GettingStartedView_CREATE_NEW_PROJECT" value="1" type="GuiHandlerData"/>
<property name="GraphicalView_ZOOM_FIT" value="1" type="GuiHandlerData"/>
<property name="PACommandNames_SIMULATION_RUN_BEHAVIORAL" value="1" type="GuiHandlerData"/>
<property name="ProjectNameChooser_PROJECT_NAME" value="1" type="GuiHandlerData"/>
<property name="SrcChooserPanel_CREATE_FILE" value="2" type="GuiHandlerData"/>
<property name="WaveformNameTree_WAVEFORM_NAME_TREE" value="2" type="GuiHandlerData"/>
</item>
<item name="Other">
<property name="GuiMode" value="32" type="GuiMode"/>
<property name="BatchMode" value="0" type="BatchMode"/>
<property name="TclMode" value="18" type="TclMode"/>
</item>
</section>
</application>
</document>

1
Exp5-3/Exp5-3.ip_user_files/README.txt Normal file
View File

@@ -0,0 +1 @@
The files in this directory structure are automatically generated and managed by Vivado. Editing these files is not recommended.

11
Exp5-3/Exp5-3.sim/sim_1/behav/xsim/Register32_tb.tcl Normal file
View File

@@ -0,0 +1,11 @@
set curr_wave [current_wave_config]
if { [string length $curr_wave] == 0 } {
if { [llength [get_objects]] > 0} {
add_wave /
set_property needs_save false [current_wave_config]
} else {
send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
}
}
run 1000ns

10
Exp5-3/Exp5-3.sim/sim_1/behav/xsim/Register32_tb_vlog.prj Normal file
View File

@@ -0,0 +1,10 @@
# compile verilog/system verilog design source files
verilog xil_defaultlib \
"../../../../Exp5-3.srcs/sources_1/new/Register32.v" \
"../../../../Exp5-3.srcs/sim_1/new/Register32_tb.v" \
# compile glbl module
verilog xil_defaultlib "glbl.v"
# Do not sort compile order
nosort

71
Exp5-3/Exp5-3.sim/sim_1/behav/xsim/glbl.v Normal file
View File

@@ -0,0 +1,71 @@
// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (strong1, weak0) GSR = GSR_int;
assign (strong1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif

12
Exp5-3/Exp5-3.sim/sim_1/behav/xsim/webtalk.jou Normal file
View File

@@ -0,0 +1,12 @@
#-----------------------------------------------------------
# Webtalk v2018.1 (64-bit)
# SW Build 2188600 on Wed Apr 4 18:40:38 MDT 2018
# IP Build 2185939 on Wed Apr 4 20:55:05 MDT 2018
# Start of session at: Wed Nov 27 15:40:18 2024
# Process ID: 33904
# Current directory: F:/Schoolwork/DigitalLogic/Exp5-3/Exp5-3.sim/sim_1/behav/xsim
# Command line: wbtcv.exe -mode batch -source F:/Schoolwork/DigitalLogic/Exp5-3/Exp5-3.sim/sim_1/behav/xsim/xsim.dir/Register32_tb_behav/webtalk/xsim_webtalk.tcl -notrace
# Log file: F:/Schoolwork/DigitalLogic/Exp5-3/Exp5-3.sim/sim_1/behav/xsim/webtalk.log
# Journal file: F:/Schoolwork/DigitalLogic/Exp5-3/Exp5-3.sim/sim_1/behav/xsim\webtalk.jou
#-----------------------------------------------------------
source F:/Schoolwork/DigitalLogic/Exp5-3/Exp5-3.sim/sim_1/behav/xsim/xsim.dir/Register32_tb_behav/webtalk/xsim_webtalk.tcl -notrace

12
Exp5-3/Exp5-3.sim/sim_1/behav/xsim/webtalk_34348.backup.jou Normal file
View File

@@ -0,0 +1,12 @@
#-----------------------------------------------------------
# Webtalk v2018.1 (64-bit)
# SW Build 2188600 on Wed Apr 4 18:40:38 MDT 2018
# IP Build 2185939 on Wed Apr 4 20:55:05 MDT 2018
# Start of session at: Wed Nov 27 04:06:33 2024
# Process ID: 34348
# Current directory: F:/Schoolwork/DigitalLogic/Exp5-3/Exp5-3.sim/sim_1/behav/xsim
# Command line: wbtcv.exe -mode batch -source F:/Schoolwork/DigitalLogic/Exp5-3/Exp5-3.sim/sim_1/behav/xsim/xsim.dir/Register32_tb_behav/webtalk/xsim_webtalk.tcl -notrace
# Log file: F:/Schoolwork/DigitalLogic/Exp5-3/Exp5-3.sim/sim_1/behav/xsim/webtalk.log
# Journal file: F:/Schoolwork/DigitalLogic/Exp5-3/Exp5-3.sim/sim_1/behav/xsim\webtalk.jou
#-----------------------------------------------------------
source F:/Schoolwork/DigitalLogic/Exp5-3/Exp5-3.sim/sim_1/behav/xsim/xsim.dir/Register32_tb_behav/webtalk/xsim_webtalk.tcl -notrace

BIN
Exp5-3/Exp5-3.sim/sim_1/behav/xsim/xelab.pb Normal file
View File

Binary file not shown.

1
Exp5-3/Exp5-3.sim/sim_1/behav/xsim/xsim.dir/Register32_tb_behav/Compile_Options.txt Normal file
View File

@@ -0,0 +1 @@
-wto "3466f69b37c149a9988e8ad9bd948ef1" --incr --debug "typical" --relax --mt "2" -L "xil_defaultlib" -L "unisims_ver" -L "unimacro_ver" -L "secureip" --snapshot "Register32_tb_behav" "xil_defaultlib.Register32_tb" "xil_defaultlib.glbl" -log "elaborate.log"

1
Exp5-3/Exp5-3.sim/sim_1/behav/xsim/xsim.dir/Register32_tb_behav/TempBreakPointFile.txt Normal file
View File

@@ -0,0 +1 @@
Breakpoint File Version 1.0

111
Exp5-3/Exp5-3.sim/sim_1/behav/xsim/xsim.dir/Register32_tb_behav/obj/xsim_1.c Normal file
View File

@@ -0,0 +1,111 @@
/**********************************************************************/
/* ____ ____ */
/* / /\/ / */
/* /___/ \ / */
/* \ \ \/ */
/* \ \ Copyright (c) 2003-2013 Xilinx, Inc. */
/* / / All Right Reserved. */
/* /---/ /\ */
/* \ \ / \ */
/* \___\/\___\ */
/**********************************************************************/
#include "iki.h"
#include <string.h>
#include <math.h>
#ifdef __GNUC__
#include <stdlib.h>
#else
#include <malloc.h>
#define alloca _alloca
#endif
/**********************************************************************/
/* ____ ____ */
/* / /\/ / */
/* /___/ \ / */
/* \ \ \/ */
/* \ \ Copyright (c) 2003-2013 Xilinx, Inc. */
/* / / All Right Reserved. */
/* /---/ /\ */
/* \ \ / \ */
/* \___\/\___\ */
/**********************************************************************/
#include "iki.h"
#include <string.h>
#include <math.h>
#ifdef __GNUC__
#include <stdlib.h>
#else
#include <malloc.h>
#define alloca _alloca
#endif
typedef void (*funcp)(char *, char *);
extern int main(int, char**);
extern void execute_4(char*, char *);
extern void execute_5(char*, char *);
extern void execute_10(char*, char *);
extern void execute_11(char*, char *);
extern void execute_12(char*, char *);
extern void execute_13(char*, char *);
extern void execute_14(char*, char *);
extern void execute_3(char*, char *);
extern void execute_7(char*, char *);
extern void execute_8(char*, char *);
extern void execute_9(char*, char *);
extern void execute_15(char*, char *);
extern void execute_16(char*, char *);
extern void execute_17(char*, char *);
extern void execute_18(char*, char *);
extern void execute_19(char*, char *);
extern void vlog_transfunc_eventcallback(char*, char*, unsigned, unsigned, unsigned, char *);
funcp funcTab[17] = {(funcp)execute_4, (funcp)execute_5, (funcp)execute_10, (funcp)execute_11, (funcp)execute_12, (funcp)execute_13, (funcp)execute_14, (funcp)execute_3, (funcp)execute_7, (funcp)execute_8, (funcp)execute_9, (funcp)execute_15, (funcp)execute_16, (funcp)execute_17, (funcp)execute_18, (funcp)execute_19, (funcp)vlog_transfunc_eventcallback};
const int NumRelocateId= 17;
void relocate(char *dp)
{
iki_relocate(dp, "xsim.dir/Register32_tb_behav/xsim.reloc", (void **)funcTab, 17);
/*Populate the transaction function pointer field in the whole net structure */
}
void sensitize(char *dp)
{
iki_sensitize(dp, "xsim.dir/Register32_tb_behav/xsim.reloc");
}
void simulate(char *dp)
{
iki_schedule_processes_at_time_zero(dp, "xsim.dir/Register32_tb_behav/xsim.reloc");
// Initialize Verilog nets in mixed simulation, for the cases when the value at time 0 should be propagated from the mixed language Vhdl net
iki_execute_processes();
// Schedule resolution functions for the multiply driven Verilog nets that have strength
// Schedule transaction functions for the singly driven Verilog nets that have strength
}
#include "iki_bridge.h"
void relocate(char *);
void sensitize(char *);
void simulate(char *);
extern SYSTEMCLIB_IMP_DLLSPEC void local_register_implicit_channel(int, char*);
extern void implicit_HDL_SCinstatiate();
extern int xsim_argc_copy ;
extern char** xsim_argv_copy ;
int main(int argc, char **argv)
{
iki_heap_initialize("ms", "isimmm", 0, 2147483648) ;
iki_set_sv_type_file_path_name("xsim.dir/Register32_tb_behav/xsim.svtype");
iki_set_crvs_dump_file_path_name("xsim.dir/Register32_tb_behav/xsim.crvsdump");
void* design_handle = iki_create_design("xsim.dir/Register32_tb_behav/xsim.mem", (void *)relocate, (void *)sensitize, (void *)simulate, 0, isimBridge_getWdbWriter(), 0, argc, argv);
iki_set_rc_trial_count(100);
(void) design_handle;
return iki_simulate_design();
}

BIN
Exp5-3/Exp5-3.sim/sim_1/behav/xsim/xsim.dir/Register32_tb_behav/xsim.mem Normal file
View File

Binary file not shown.

BIN
Exp5-3/Exp5-3.sim/sim_1/behav/xsim/xvlog.pb Normal file
View File

Binary file not shown.

51
Exp5-3/Exp5-3.srcs/sim_1/new/Register32_tb.v Normal file
View File

@@ -0,0 +1,51 @@
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2024/11/27 04:03:49
// Design Name:
// Module Name: Register32_tb
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Register32_tb;
reg [31:0] D;
reg clk, rst, set;
wire [31:0] Q;
Register32 uut (
.D(D),
.clk(clk),
.rst(rst),
.set(set),
.Q(Q)
);
initial begin
clk = 0;
forever #10 clk = ~clk;
end
initial begin
D = 32'b0; rst = 0; set = 0; #15;
// Reset test
rst = 1; #20;
rst = 0; #20;
// Set test
set = 1; #20;
set = 0; #20;
// Data input test
D = 32'hA5A5A5A5; #30;
D = 32'h5A5A5A5A; #30;
$stop;
end
endmodule

39
Exp5-3/Exp5-3.srcs/sources_1/new/Register32.v Normal file
View File

@@ -0,0 +1,39 @@
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2024/11/24 23:42:48
// Design Name:
// Module Name: Register32
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Register32 (
input wire [31:0] D,
input wire clk,
input wire rst,
input wire set,
output reg [31:0] Q
);
always @(posedge clk or posedge rst or posedge set) begin
if (rst)
Q <= 32'h00000000; // Reset clear
else if (set)
Q <= 32'hFFFFFFFF; // Set all 1
else
Q <= D;
end
endmodule

145
Exp5-3/Exp5-3.xpr Normal file
View File

@@ -0,0 +1,145 @@
<?xml version="1.0" encoding="UTF-8"?>
<!-- Product Version: Vivado v2018.1 (64-bit) -->
<!-- -->
<!-- Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. -->
<Project Version="7" Minor="36" Path="F:/Schoolwork/DigitalLogic/Exp5-3/Exp5-3.xpr">
<DefaultLaunch Dir="$PRUNDIR"/>
<Configuration>
<Option Name="Id" Val="3466f69b37c149a9988e8ad9bd948ef1"/>
<Option Name="Part" Val="xc7a35tcsg324-1"/>
<Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
<Option Name="CompiledLibDirXSim" Val=""/>
<Option Name="CompiledLibDirModelSim" Val="$PCACHEDIR/compile_simlib/modelsim"/>
<Option Name="CompiledLibDirQuesta" Val="$PCACHEDIR/compile_simlib/questa"/>
<Option Name="CompiledLibDirIES" Val="$PCACHEDIR/compile_simlib/ies"/>
<Option Name="CompiledLibDirXcelium" Val="$PCACHEDIR/compile_simlib/xcelium"/>
<Option Name="CompiledLibDirVCS" Val="$PCACHEDIR/compile_simlib/vcs"/>
<Option Name="CompiledLibDirRiviera" Val="$PCACHEDIR/compile_simlib/riviera"/>
<Option Name="CompiledLibDirActivehdl" Val="$PCACHEDIR/compile_simlib/activehdl"/>
<Option Name="BoardPart" Val=""/>
<Option Name="ActiveSimSet" Val="sim_1"/>
<Option Name="DefaultLib" Val="xil_defaultlib"/>
<Option Name="ProjectType" Val="Default"/>
<Option Name="IPOutputRepo" Val="$PCACHEDIR/ip"/>
<Option Name="IPCachePermission" Val="read"/>
<Option Name="IPCachePermission" Val="write"/>
<Option Name="EnableCoreContainer" Val="FALSE"/>
<Option Name="CreateRefXciForCoreContainers" Val="FALSE"/>
<Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
<Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
<Option Name="EnableBDX" Val="FALSE"/>
<Option Name="DSAVendor" Val="xilinx"/>
<Option Name="DSANumComputeUnits" Val="60"/>
<Option Name="WTXSimLaunchSim" Val="1"/>
<Option Name="WTModelSimLaunchSim" Val="0"/>
<Option Name="WTQuestaLaunchSim" Val="0"/>
<Option Name="WTIesLaunchSim" Val="0"/>
<Option Name="WTVcsLaunchSim" Val="0"/>
<Option Name="WTRivieraLaunchSim" Val="0"/>
<Option Name="WTActivehdlLaunchSim" Val="0"/>
<Option Name="WTXSimExportSim" Val="0"/>
<Option Name="WTModelSimExportSim" Val="0"/>
<Option Name="WTQuestaExportSim" Val="0"/>
<Option Name="WTIesExportSim" Val="0"/>
<Option Name="WTVcsExportSim" Val="0"/>
<Option Name="WTRivieraExportSim" Val="0"/>
<Option Name="WTActivehdlExportSim" Val="0"/>
<Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
<Option Name="XSimRadix" Val="hex"/>
<Option Name="XSimTimeUnit" Val="ns"/>
<Option Name="XSimArrayDisplayLimit" Val="1024"/>
<Option Name="XSimTraceLimit" Val="65536"/>
<Option Name="SimTypes" Val="rtl"/>
</Configuration>
<FileSets Version="1" Minor="31">
<FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1">
<Filter Type="Srcs"/>
<File Path="$PSRCDIR/sources_1/new/Register32.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<Config>
<Option Name="DesignMode" Val="RTL"/>
<Option Name="TopModule" Val="Register32"/>
<Option Name="TopAutoSet" Val="TRUE"/>
</Config>
</FileSet>
<FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1">
<Filter Type="Constrs"/>
<Config>
<Option Name="ConstrsType" Val="XDC"/>
</Config>
</FileSet>
<FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1">
<File Path="$PSRCDIR/sim_1/new/Register32_tb.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<Config>
<Option Name="DesignMode" Val="RTL"/>
<Option Name="TopModule" Val="Register32_tb"/>
<Option Name="TopLib" Val="xil_defaultlib"/>
<Option Name="TopAutoSet" Val="TRUE"/>
<Option Name="TransportPathDelay" Val="0"/>
<Option Name="TransportIntDelay" Val="0"/>
<Option Name="SrcSet" Val="sources_1"/>
</Config>
</FileSet>
</FileSets>
<Simulators>
<Simulator Name="XSim">
<Option Name="Description" Val="Vivado Simulator"/>
<Option Name="CompiledLib" Val="0"/>
</Simulator>
<Simulator Name="ModelSim">
<Option Name="Description" Val="ModelSim Simulator"/>
</Simulator>
<Simulator Name="Questa">
<Option Name="Description" Val="Questa Advanced Simulator"/>
</Simulator>
<Simulator Name="Riviera">
<Option Name="Description" Val="Riviera-PRO Simulator"/>
</Simulator>
<Simulator Name="ActiveHDL">
<Option Name="Description" Val="Active-HDL Simulator"/>
</Simulator>
</Simulators>
<Runs Version="1" Minor="10">
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a35tcsg324-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2018">
<Desc>Vivado Synthesis Defaults</Desc>
</StratHandle>
<Step Id="synth_design"/>
</Strategy>
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2018"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
</Run>
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcsg324-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2018">
<Desc>Default settings for Implementation.</Desc>
</StratHandle>
<Step Id="init_design"/>
<Step Id="opt_design"/>
<Step Id="power_opt_design"/>
<Step Id="place_design"/>
<Step Id="post_place_power_opt_design"/>
<Step Id="phys_opt_design"/>
<Step Id="route_design"/>
<Step Id="post_route_phys_opt_design"/>
<Step Id="write_bitstream"/>
</Strategy>
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2018"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
</Run>
</Runs>
<Board/>
</Project>

14
Exp5-3/vivado.jou Normal file
View File

@@ -0,0 +1,14 @@
#-----------------------------------------------------------
# Vivado v2018.1 (64-bit)
# SW Build 2188600 on Wed Apr 4 18:40:38 MDT 2018
# IP Build 2185939 on Wed Apr 4 20:55:05 MDT 2018
# Start of session at: Mon Dec 2 10:28:58 2024
# Process ID: 2072
# Current directory: F:/Schoolwork/DigitalLogic/Exp5-3
# Command line: vivado.exe -gui_launcher_event rodinguilauncherevent20832 F:\Schoolwork\DigitalLogic\Exp5-3\Exp5-3.xpr
# Log file: F:/Schoolwork/DigitalLogic/Exp5-3/vivado.log
# Journal file: F:/Schoolwork/DigitalLogic/Exp5-3\vivado.jou
#-----------------------------------------------------------
start_gui
open_project F:/Schoolwork/DigitalLogic/Exp5-3/Exp5-3.xpr
update_compile_order -fileset sources_1