Initial commit

Exp5-3/Exp5-3.srcs/sim_1/new/Register32_tb.v

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+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date: 2024/11/27 04:03:49
+// Design Name: 
+// Module Name: Register32_tb
+// Project Name: 
+// Target Devices: 
+// Tool Versions: 
+// Description: 
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module Register32_tb;
+reg [31:0] D;
+reg clk, rst, set;
+wire [31:0] Q;
+Register32 uut (
+    .D(D),
+    .clk(clk),
+    .rst(rst),
+    .set(set),
+    .Q(Q)
+);
+initial begin
+    clk = 0;
+    forever #10 clk = ~clk;
+end
+initial begin
+    D = 32'b0; rst = 0; set = 0; #15;
+    // Reset test
+    rst = 1; #20;
+    rst = 0; #20;
+    // Set test
+    set = 1; #20;
+    set = 0; #20;
+    // Data input test
+    D = 32'hA5A5A5A5; #30;
+    D = 32'h5A5A5A5A; #30;
+    $stop;
+end
+endmodule

Exp5-3/Exp5-3.srcs/sources_1/new/Register32.v

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+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date: 2024/11/24 23:42:48
+// Design Name: 
+// Module Name: Register32
+// Project Name: 
+// Target Devices: 
+// Tool Versions: 
+// Description: 
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module Register32 (
+    input wire [31:0] D,
+    input wire clk,
+    input wire rst,
+    input wire set,
+    output reg [31:0] Q
+);
+always @(posedge clk or posedge rst or posedge set) begin
+    if (rst)
+        Q <= 32'h00000000; // Reset clear
+    else if (set)
+        Q <= 32'hFFFFFFFF; // Set all 1
+    else
+        Q <= D;
+end
+endmodule
+