Initial commit

Exp1-2-1/Exp1-2-1.srcs/constrs_1/new/mux21.xdc

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+set_property PACKAGE_PIN P5 [get_ports a]
+set_property PACKAGE_PIN P4 [get_ports b]
+set_property PACKAGE_PIN P3 [get_ports c]
+set_property PACKAGE_PIN G4 [get_ports y]
+set_property IOSTANDARD LVCMOS33 [get_ports a]
+set_property IOSTANDARD LVCMOS33 [get_ports b]
+set_property IOSTANDARD LVCMOS33 [get_ports c]
+set_property IOSTANDARD LVCMOS33 [get_ports y]

Exp1-2-1/Exp1-2-1.srcs/sim_1/new/sim4mux21.v

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+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date: 2024/09/24 15:10:13
+// Design Name: 
+// Module Name: sim4mux21
+// Project Name: 
+// Target Devices: 
+// Tool Versions: 
+// Description: 
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module sim4mux21();
+reg a, b, c;
+wire y;
+mux21 uut(.a(a), .b(b), .c(c), .y(y));
+    always begin
+    a = 0; b = 0; c = 0; #100;
+    a = 0; b = 0; c = 1; #100;
+    a = 0; b = 1; c = 0; #100;
+    a = 0; b = 1; c = 1; #100;
+    a = 1; b = 0; c = 0; #100;
+    a = 1; b = 0; c = 1; #100;
+    a = 1; b = 1; c = 0; #100;
+    a = 1; b = 1; c = 1; #100;
+    end
+endmodule

Exp1-2-1/Exp1-2-1.srcs/sources_1/new/mux21.v

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+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date: 2024/09/24 15:07:05
+// Design Name: 
+// Module Name: mux21
+// Project Name: 
+// Target Devices: 
+// Tool Versions: 
+// Description: 
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module mux21(a, b, c, y);
+input a, b, c;
+output y;
+assign y = c ? b : a;
+endmodule