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2025-11-06 09:35:54 +08:00
commit 07678f510c
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31
Experiments/Shared/ALU.v Normal file
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module ALU(
input [31:0] a,
input [31:0] b,
input [2:0] AluCtrl,
output reg [31:0] AddResult,
output reg Zero
);
parameter ADD = 3'b000;
parameter SUB = 3'b001;
parameter AND = 3'b010;
parameter OR = 3'b011;
parameter NOR = 3'b100;
parameter SLT = 3'b101;
parameter SLTU = 3'b110;
parameter PASSB= 3'b111;
always @(*) begin
case (AluCtrl)
ADD: AddResult = a + b;
SUB: AddResult = a - b;
AND: AddResult = a & b;
OR: AddResult = a | b;
NOR: AddResult = ~(a | b);
SLT: AddResult = ($signed(a) < $signed(b)) ? 32'd1 : 32'd0;
SLTU: AddResult = (a < b) ? 32'd1 : 32'd0;
PASSB:AddResult = b;
default: AddResult = 32'hxxxxxxxx;
endcase
Zero = (AddResult == 32'd0);
end
endmodule

43
Experiments/Shared/Controller.v Normal file
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module Controller(
input [31:15] Opcode_in,
output reg RegWr,
output reg MemToReg,
output reg MemWrEn,
output reg ALUBSrc,
output reg srcReg,
output reg [1:0] ExtOp,
output reg [2:0] AluCtrl
);
parameter OP_RTYPE = 3'b000, OP_LU12I = 3'b001, OP_LOAD = 3'b010, OP_STORE = 3'b011;
parameter FUNC_ADD = 7'b0000010, FUNC_SLT = 7'b0000100, FUNC_SLTU= 7'b0000101;
wire [2:0] main_op = Opcode_in[31:29];
wire [6:0] func_op = Opcode_in[21:15];
always @(*) begin
RegWr=0; MemToReg=0; MemWrEn=0; ALUBSrc=0; srcReg=0; ExtOp=2'bxx; AluCtrl=3'bxxx;
case(main_op)
OP_RTYPE: begin
RegWr=1; ALUBSrc=0;
case(func_op)
FUNC_ADD: AluCtrl = 3'b000;
FUNC_SLT: AluCtrl = 3'b101;
FUNC_SLTU: AluCtrl = 3'b110;
default: ;
endcase
end
OP_LU12I: begin
RegWr=1; ALUBSrc=1; ExtOp=2'b10; AluCtrl=3'b111;
end
OP_LOAD: begin
RegWr=1; MemToReg=1; ALUBSrc=1; ExtOp=2'b00; AluCtrl=3'b000;
end
OP_STORE: begin
MemWrEn=1; ALUBSrc=1; srcReg=1; ExtOp=2'b00; AluCtrl=3'b000;
end
default: ;
endcase
end
endmodule

12
Experiments/Shared/DR.v Normal file
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module DR(
input clk,
input WE,
input [31:0] DataIn,
output reg [31:0] DataOut
);
always @(posedge clk) begin
if (WE) begin
DataOut <= DataIn;
end
end
endmodule

17
Experiments/Shared/DataRAM.v Normal file
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module DataRAM(
input clk,
input MemWrEn,
input [31:0] addr,
input [31:0] data_in,
output [31:0] data_out
);
reg [31:0] ram[0:1023];
wire [9:0] word_addr = addr[11:2];
always @(posedge clk) begin
if (MemWrEn) begin
ram[word_addr] <= data_in;
end
end
assign data_out = ram[word_addr];
endmodule

24
Experiments/Shared/Datapath.v Normal file
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module Datapath(
input clk,
input [31:0] Instr,
input RegWr,
input MemToReg,
input MemWrEn,
input ALUBSrc,
input srcReg,
input [1:0] ExtOp,
input [2:0] AluCtrl,
output Zero
);
wire [31:0] busA_out, busB_out, ext_out, alu_in_b, alu_result, ram_data_out, reg_write_data;
wire [4:0] rj = Instr[9:5];
wire [4:0] rk_or_rd_store = Instr[14:10];
wire [4:0] rd_write = Instr[4:0];
Registers u_Registers(.clk(clk), .RegWr(RegWr), .Ra(rj), .Rb(srcReg ? Instr[4:0] : rk_or_rd_store), .Rw(rd_write), .busW(reg_write_data), .busA(busA_out), .busB(busB_out));
Ext u_Ext(.DataIn(Instr), .ExtOp(ExtOp), .DataOut(ext_out));
assign alu_in_b = ALUBSrc ? ext_out : busB_out;
ALU u_ALU(.a(busA_out), .b(alu_in_b), .AluCtrl(AluCtrl), .AddResult(alu_result), .Zero(Zero));
DataRAM u_DataRAM(.clk(clk), .MemWrEn(MemWrEn), .addr(alu_result), .data_in(busB_out), .data_out(ram_data_out));
assign reg_write_data = MemToReg ? ram_data_out : alu_result;
endmodule

23
Experiments/Shared/Ext.v Normal file
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module Ext(
input [31:0] DataIn,
input [1:0] ExtOp,
output [31:0] DataOut
);
wire [31:0] imm12, imm16, imm20, imm26;
assign imm12 = {{20{DataIn[21]}}, DataIn[21:10]};
assign imm16 = {{14{DataIn[25]}}, DataIn[25:10], 2'b0};
assign imm20 = {DataIn[24:5], 12'b0};
assign imm26 = {{4{DataIn[9]}}, DataIn[9:0], DataIn[25:10], 2'b0};
reg [31:0] temp_DataOut;
always @(*) begin
case (ExtOp)
2'b00: temp_DataOut = imm12;
2'b01: temp_DataOut = imm16;
2'b10: temp_DataOut = imm20;
2'b11: temp_DataOut = imm26;
default: temp_DataOut = 32'hxxxxxxxx;
endcase
end
assign DataOut = temp_DataOut;
endmodule

14
Experiments/Shared/LA32R_CPU.v Normal file
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module LA32R_CPU(
input clk,
input [31:0] Instr
);
wire RegWr, MemToReg, MemWrEn, ALUBSrc, srcReg;
wire [1:0] ExtOp;
wire [2:0] AluCtrl;
wire Zero;
Controller u_Controller(.Opcode_in(Instr[31:15]), .RegWr(RegWr), .MemToReg(MemToReg), .MemWrEn(MemWrEn),
.ALUBSrc(ALUBSrc), .srcReg(srcReg), .ExtOp(ExtOp), .AluCtrl(AluCtrl));
Datapath u_Datapath(.clk(clk), .Instr(Instr), .RegWr(RegWr), .MemToReg(MemToReg), .MemWrEn(MemWrEn),
.ALUBSrc(ALUBSrc), .srcReg(srcReg), .ExtOp(ExtOp), .AluCtrl(AluCtrl), .Zero(Zero));
endmodule

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Experiments/Shared/PC.v Normal file
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module PC(
input clk,
input rst,
input pc_inc,
input [31:0] offset,
output reg [31:0] PCdata
);
always @(posedge clk or posedge rst) begin
if (rst) begin
PCdata <= 32'd0;
end else begin
if (pc_inc) begin
PCdata <= PCdata + 4;
end else begin
PCdata <= PCdata + offset;
end
end
end
endmodule

25
Experiments/Shared/Registers.v Normal file
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module Registers(
input clk,
input RegWr,
input [4:0] Ra, Rb, Rw,
input [31:0] busW,
output [31:0] busA,
output [31:0] busB
);
reg [31:0] regs[0:31];
integer i;
initial begin
for (i = 0; i < 32; i = i + 1) begin
regs[i] = 32'd0;
end
end
always @(posedge clk) begin
if (RegWr && (Rw != 5'd0)) begin
regs[Rw] <= busW;
end
end
assign busA = (Ra == 5'd0) ? 32'd0 : regs[Ra];
assign busB = (Rb == 5'd0) ? 32'd0 : regs[Rb];
endmodule