Initial commit
This commit is contained in:
133
.gitignore
vendored
Normal file
133
.gitignore
vendored
Normal file
@@ -0,0 +1,133 @@
|
||||
### MicrosoftOffice ###
|
||||
*.tmp
|
||||
|
||||
# Word temporary
|
||||
~$*.doc*
|
||||
|
||||
# Word Auto Backup File
|
||||
Backup of *.doc*
|
||||
|
||||
# Excel temporary
|
||||
~$*.xls*
|
||||
|
||||
# Excel Backup File
|
||||
*.xlk
|
||||
|
||||
# PowerPoint temporary
|
||||
~$*.ppt*
|
||||
|
||||
# Visio autosave temporary files
|
||||
*.~vsd*
|
||||
|
||||
### VisualStudioCode ###
|
||||
.vscode/*
|
||||
!.vscode/settings.json
|
||||
!.vscode/tasks.json
|
||||
!.vscode/launch.json
|
||||
!.vscode/extensions.json
|
||||
!.vscode/*.code-snippets
|
||||
|
||||
# Local History for Visual Studio Code
|
||||
.history/
|
||||
|
||||
# Built Visual Studio Code Extensions
|
||||
*.vsix
|
||||
|
||||
### VisualStudioCode Patch ###
|
||||
# Ignore all local history of files
|
||||
.history
|
||||
.ionide
|
||||
|
||||
### Vivado ###
|
||||
#########################################################################################################
|
||||
## This is an example .gitignore file for Vivado, please treat it as an example as
|
||||
## it might not be complete. In addition, XAPP 1165 should be followed.
|
||||
#########
|
||||
#Exclude all
|
||||
Exp**/*
|
||||
!*/
|
||||
!.gitignore
|
||||
!Exp**.docx
|
||||
###########################################################################
|
||||
## VIVADO
|
||||
#Source files:
|
||||
#Do NOT ignore VHDL, Verilog, block diagrams or EDIF files.
|
||||
!*.vhd
|
||||
!*.v
|
||||
!*.sv
|
||||
!*.bd
|
||||
!*.edif
|
||||
#IP files
|
||||
#.xci: synthesis and implemented not possible - you need to return back to the previous version to generate output products
|
||||
#.xci + .dcp: implementation possible but not re-synthesis
|
||||
#*.xci(www.spiritconsortium.org)
|
||||
!*.xci
|
||||
#.xcix: Core container file
|
||||
#.xcix: https://www.xilinx.com/support/documentation/sw_manuals/xilinx2016_2/ug896-vivado-ip.pdf (Page 41)
|
||||
!*.xcix
|
||||
#*.dcp(checkpoint files)
|
||||
!*.dcp
|
||||
!*.vds
|
||||
!*.pb
|
||||
#All bd comments and layout coordinates are stored within .ui
|
||||
!*.ui
|
||||
!*.ooc
|
||||
#System Generator
|
||||
!*.mdl
|
||||
!*.slx
|
||||
!*.bxml
|
||||
#Simulation logic analyzer
|
||||
!*.wcfg
|
||||
!*.coe
|
||||
#MIG
|
||||
!*.prj
|
||||
!*.mem
|
||||
#Project files
|
||||
#XPR + *.XML ? XPR (Files are merged into a single XPR file for 2014.1 version)
|
||||
#Do NOT ignore *.xpr files
|
||||
!*.xpr
|
||||
#Include *.xml files for 2013.4 or earlier version
|
||||
!*.xml
|
||||
#Constraint files
|
||||
#Do NOT ignore *.xdc files
|
||||
!*.xdc
|
||||
#TCL - files
|
||||
!*.tcl
|
||||
#Journal - files
|
||||
!*.jou
|
||||
#Reports
|
||||
!*.rpt
|
||||
!*.txt
|
||||
!*.vdi
|
||||
#C-files
|
||||
!*.c
|
||||
!*.h
|
||||
!*.elf
|
||||
!*.bmm
|
||||
!*.xmp
|
||||
|
||||
### Windows ###
|
||||
# Windows thumbnail cache files
|
||||
Thumbs.db
|
||||
Thumbs.db:encryptable
|
||||
ehthumbs.db
|
||||
ehthumbs_vista.db
|
||||
|
||||
# Dump file
|
||||
*.stackdump
|
||||
|
||||
# Folder config file
|
||||
[Dd]esktop.ini
|
||||
|
||||
# Recycle Bin used on file shares
|
||||
$RECYCLE.BIN/
|
||||
|
||||
# Windows Installer files
|
||||
*.cab
|
||||
*.msi
|
||||
*.msix
|
||||
*.msm
|
||||
*.msp
|
||||
|
||||
# Windows shortcuts
|
||||
*.lnk
|
||||
BIN
2025-计算机组成原理实验讲义LA32R.docx
Normal file
BIN
2025-计算机组成原理实验讲义LA32R.docx
Normal file
Binary file not shown.
44
Exp1/Exp1.cache/wt/webtalk_pa.xml
Normal file
44
Exp1/Exp1.cache/wt/webtalk_pa.xml
Normal file
@@ -0,0 +1,44 @@
|
||||
<?xml version="1.0" encoding="UTF-8" ?>
|
||||
<document>
|
||||
<!--The data in this file is primarily intended for consumption by Xilinx tools.
|
||||
The structure and the elements are likely to change over the next few releases.
|
||||
This means code written to parse this file will need to be revisited each subsequent release.-->
|
||||
<application name="pa" timeStamp="Tue Jul 1 23:58:17 2025">
|
||||
<section name="Project Information" visible="false">
|
||||
<property name="ProjectID" value="ee2af576d9d24774bc966985fcb46077" type="ProjectID"/>
|
||||
<property name="ProjectIteration" value="1" type="ProjectIteration"/>
|
||||
</section>
|
||||
<section name="PlanAhead Usage" visible="true">
|
||||
<item name="Project Data">
|
||||
<property name="SrcSetCount" value="1" type="SrcSetCount"/>
|
||||
<property name="ConstraintSetCount" value="1" type="ConstraintSetCount"/>
|
||||
<property name="DesignMode" value="RTL" type="DesignMode"/>
|
||||
<property name="SynthesisStrategy" value="Vivado Synthesis Defaults" type="SynthesisStrategy"/>
|
||||
<property name="ImplStrategy" value="Vivado Implementation Defaults" type="ImplStrategy"/>
|
||||
</item>
|
||||
<item name="Java Command Handlers">
|
||||
<property name="AddSources" value="1" type="JavaHandler"/>
|
||||
<property name="CloseProject" value="1" type="JavaHandler"/>
|
||||
<property name="NewProject" value="1" type="JavaHandler"/>
|
||||
<property name="OpenProject" value="1" type="JavaHandler"/>
|
||||
</item>
|
||||
<item name="Gui Handlers">
|
||||
<property name="BaseDialog_OK" value="1" type="GuiHandlerData"/>
|
||||
<property name="FPGAChooser_FPGA_TABLE" value="1" type="GuiHandlerData"/>
|
||||
<property name="FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE" value="1" type="GuiHandlerData"/>
|
||||
<property name="GettingStartedView_CREATE_NEW_PROJECT" value="1" type="GuiHandlerData"/>
|
||||
<property name="MainMenuMgr_FILE" value="4" type="GuiHandlerData"/>
|
||||
<property name="MainMenuMgr_FLOW" value="2" type="GuiHandlerData"/>
|
||||
<property name="MainMenuMgr_PROJECT" value="4" type="GuiHandlerData"/>
|
||||
<property name="PACommandNames_CLOSE_PROJECT" value="1" type="GuiHandlerData"/>
|
||||
<property name="PACommandNames_OPEN_PROJECT" value="1" type="GuiHandlerData"/>
|
||||
<property name="ProjectNameChooser_PROJECT_NAME" value="1" type="GuiHandlerData"/>
|
||||
</item>
|
||||
<item name="Other">
|
||||
<property name="GuiMode" value="12" type="GuiMode"/>
|
||||
<property name="BatchMode" value="0" type="BatchMode"/>
|
||||
<property name="TclMode" value="8" type="TclMode"/>
|
||||
</item>
|
||||
</section>
|
||||
</application>
|
||||
</document>
|
||||
128
Exp1/Exp1.xpr
Normal file
128
Exp1/Exp1.xpr
Normal file
@@ -0,0 +1,128 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<!-- Product Version: Vivado v2018.1 (64-bit) -->
|
||||
<!-- -->
|
||||
<!-- Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. -->
|
||||
|
||||
<Project Version="7" Minor="36" Path="D:/Schoolwork/ComputerComposition/Exp1/Exp1.xpr">
|
||||
<DefaultLaunch Dir="$PRUNDIR"/>
|
||||
<Configuration>
|
||||
<Option Name="Id" Val="92df7af7179e4393a9b6b717f49919e8"/>
|
||||
<Option Name="Part" Val="xc7a35tcsg324-1"/>
|
||||
<Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
|
||||
<Option Name="CompiledLibDirXSim" Val=""/>
|
||||
<Option Name="CompiledLibDirModelSim" Val="$PCACHEDIR/compile_simlib/modelsim"/>
|
||||
<Option Name="CompiledLibDirQuesta" Val="$PCACHEDIR/compile_simlib/questa"/>
|
||||
<Option Name="CompiledLibDirIES" Val="$PCACHEDIR/compile_simlib/ies"/>
|
||||
<Option Name="CompiledLibDirXcelium" Val="$PCACHEDIR/compile_simlib/xcelium"/>
|
||||
<Option Name="CompiledLibDirVCS" Val="$PCACHEDIR/compile_simlib/vcs"/>
|
||||
<Option Name="CompiledLibDirRiviera" Val="$PCACHEDIR/compile_simlib/riviera"/>
|
||||
<Option Name="CompiledLibDirActivehdl" Val="$PCACHEDIR/compile_simlib/activehdl"/>
|
||||
<Option Name="BoardPart" Val=""/>
|
||||
<Option Name="ActiveSimSet" Val="sim_1"/>
|
||||
<Option Name="DefaultLib" Val="xil_defaultlib"/>
|
||||
<Option Name="ProjectType" Val="Default"/>
|
||||
<Option Name="IPOutputRepo" Val="$PCACHEDIR/ip"/>
|
||||
<Option Name="IPCachePermission" Val="read"/>
|
||||
<Option Name="IPCachePermission" Val="write"/>
|
||||
<Option Name="EnableCoreContainer" Val="FALSE"/>
|
||||
<Option Name="CreateRefXciForCoreContainers" Val="FALSE"/>
|
||||
<Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
|
||||
<Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
|
||||
<Option Name="EnableBDX" Val="FALSE"/>
|
||||
<Option Name="DSAVendor" Val="xilinx"/>
|
||||
<Option Name="DSANumComputeUnits" Val="60"/>
|
||||
<Option Name="WTXSimLaunchSim" Val="0"/>
|
||||
<Option Name="WTModelSimLaunchSim" Val="0"/>
|
||||
<Option Name="WTQuestaLaunchSim" Val="0"/>
|
||||
<Option Name="WTIesLaunchSim" Val="0"/>
|
||||
<Option Name="WTVcsLaunchSim" Val="0"/>
|
||||
<Option Name="WTRivieraLaunchSim" Val="0"/>
|
||||
<Option Name="WTActivehdlLaunchSim" Val="0"/>
|
||||
<Option Name="WTXSimExportSim" Val="0"/>
|
||||
<Option Name="WTModelSimExportSim" Val="0"/>
|
||||
<Option Name="WTQuestaExportSim" Val="0"/>
|
||||
<Option Name="WTIesExportSim" Val="0"/>
|
||||
<Option Name="WTVcsExportSim" Val="0"/>
|
||||
<Option Name="WTRivieraExportSim" Val="0"/>
|
||||
<Option Name="WTActivehdlExportSim" Val="0"/>
|
||||
<Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
|
||||
<Option Name="XSimRadix" Val="hex"/>
|
||||
<Option Name="XSimTimeUnit" Val="ns"/>
|
||||
<Option Name="XSimArrayDisplayLimit" Val="1024"/>
|
||||
<Option Name="XSimTraceLimit" Val="65536"/>
|
||||
<Option Name="SimTypes" Val="rtl"/>
|
||||
</Configuration>
|
||||
<FileSets Version="1" Minor="31">
|
||||
<FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1">
|
||||
<Filter Type="Srcs"/>
|
||||
<Config>
|
||||
<Option Name="DesignMode" Val="RTL"/>
|
||||
<Option Name="TopAutoSet" Val="TRUE"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1">
|
||||
<Filter Type="Constrs"/>
|
||||
<Config>
|
||||
<Option Name="ConstrsType" Val="XDC"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1">
|
||||
<Config>
|
||||
<Option Name="DesignMode" Val="RTL"/>
|
||||
<Option Name="TopAutoSet" Val="TRUE"/>
|
||||
<Option Name="TransportPathDelay" Val="0"/>
|
||||
<Option Name="TransportIntDelay" Val="0"/>
|
||||
<Option Name="SrcSet" Val="sources_1"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
</FileSets>
|
||||
<Simulators>
|
||||
<Simulator Name="XSim">
|
||||
<Option Name="Description" Val="Vivado Simulator"/>
|
||||
<Option Name="CompiledLib" Val="0"/>
|
||||
</Simulator>
|
||||
<Simulator Name="ModelSim">
|
||||
<Option Name="Description" Val="ModelSim Simulator"/>
|
||||
</Simulator>
|
||||
<Simulator Name="Questa">
|
||||
<Option Name="Description" Val="Questa Advanced Simulator"/>
|
||||
</Simulator>
|
||||
<Simulator Name="Riviera">
|
||||
<Option Name="Description" Val="Riviera-PRO Simulator"/>
|
||||
</Simulator>
|
||||
<Simulator Name="ActiveHDL">
|
||||
<Option Name="Description" Val="Active-HDL Simulator"/>
|
||||
</Simulator>
|
||||
</Simulators>
|
||||
<Runs Version="1" Minor="10">
|
||||
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a35tcsg324-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2018">
|
||||
<Desc>Vivado Synthesis Defaults</Desc>
|
||||
</StratHandle>
|
||||
<Step Id="synth_design"/>
|
||||
</Strategy>
|
||||
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2018"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
</Run>
|
||||
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcsg324-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2018">
|
||||
<Desc>Default settings for Implementation.</Desc>
|
||||
</StratHandle>
|
||||
<Step Id="init_design"/>
|
||||
<Step Id="opt_design"/>
|
||||
<Step Id="power_opt_design"/>
|
||||
<Step Id="place_design"/>
|
||||
<Step Id="post_place_power_opt_design"/>
|
||||
<Step Id="phys_opt_design"/>
|
||||
<Step Id="route_design"/>
|
||||
<Step Id="post_route_phys_opt_design"/>
|
||||
<Step Id="write_bitstream"/>
|
||||
</Strategy>
|
||||
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2018"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
</Run>
|
||||
</Runs>
|
||||
<Board/>
|
||||
</Project>
|
||||
BIN
Exp1Report.docx
Normal file
BIN
Exp1Report.docx
Normal file
Binary file not shown.
30
Exp2/Exp2.cache/wt/webtalk_pa.xml
Normal file
30
Exp2/Exp2.cache/wt/webtalk_pa.xml
Normal file
@@ -0,0 +1,30 @@
|
||||
<?xml version="1.0" encoding="UTF-8" ?>
|
||||
<document>
|
||||
<!--The data in this file is primarily intended for consumption by Xilinx tools.
|
||||
The structure and the elements are likely to change over the next few releases.
|
||||
This means code written to parse this file will need to be revisited each subsequent release.-->
|
||||
<application name="pa" timeStamp="Mon Jun 9 00:51:56 2025">
|
||||
<section name="Project Information" visible="false">
|
||||
<property name="ProjectID" value="a73c9123352543f9bfb3406843b0bfb0" type="ProjectID"/>
|
||||
<property name="ProjectIteration" value="1" type="ProjectIteration"/>
|
||||
</section>
|
||||
<section name="PlanAhead Usage" visible="true">
|
||||
<item name="Project Data">
|
||||
<property name="SrcSetCount" value="1" type="SrcSetCount"/>
|
||||
<property name="ConstraintSetCount" value="1" type="ConstraintSetCount"/>
|
||||
<property name="DesignMode" value="RTL" type="DesignMode"/>
|
||||
<property name="SynthesisStrategy" value="Vivado Synthesis Defaults" type="SynthesisStrategy"/>
|
||||
<property name="ImplStrategy" value="Vivado Implementation Defaults" type="ImplStrategy"/>
|
||||
</item>
|
||||
<item name="Gui Handlers">
|
||||
<property name="FileSetPanel_FILE_SET_PANEL_TREE" value="4" type="GuiHandlerData"/>
|
||||
<property name="SyntheticaGettingStartedView_RECENT_PROJECTS" value="1" type="GuiHandlerData"/>
|
||||
</item>
|
||||
<item name="Other">
|
||||
<property name="GuiMode" value="3" type="GuiMode"/>
|
||||
<property name="BatchMode" value="0" type="BatchMode"/>
|
||||
<property name="TclMode" value="0" type="TclMode"/>
|
||||
</item>
|
||||
</section>
|
||||
</application>
|
||||
</document>
|
||||
34
Exp2/Exp2.srcs/sources_1/new/DR.v
Normal file
34
Exp2/Exp2.srcs/sources_1/new/DR.v
Normal file
@@ -0,0 +1,34 @@
|
||||
`timescale 1ns / 1ps
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company:
|
||||
// Engineer:
|
||||
//
|
||||
// Create Date: 2025/05/30 19:43:40
|
||||
// Design Name:
|
||||
// Module Name: DR
|
||||
// Project Name:
|
||||
// Target Devices:
|
||||
// Tool Versions:
|
||||
// Description:
|
||||
//
|
||||
// Dependencies:
|
||||
//
|
||||
// Revision:
|
||||
// Revision 0.01 - File Created
|
||||
// Additional Comments:
|
||||
//
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
module DR (
|
||||
input wire [31:0] Datain,
|
||||
input wire clk,
|
||||
input wire WE,
|
||||
output reg [31:0] DataOut
|
||||
);
|
||||
always @(posedge clk) begin
|
||||
if (WE) begin
|
||||
DataOut <= Datain;
|
||||
end
|
||||
end
|
||||
endmodule
|
||||
43
Exp2/Exp2.srcs/sources_1/new/PC.v
Normal file
43
Exp2/Exp2.srcs/sources_1/new/PC.v
Normal file
@@ -0,0 +1,43 @@
|
||||
`timescale 1ns / 1ps
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company:
|
||||
// Engineer:
|
||||
//
|
||||
// Create Date: 2025/05/30 20:48:55
|
||||
// Design Name:
|
||||
// Module Name: PC
|
||||
// Project Name:
|
||||
// Target Devices:
|
||||
// Tool Versions:
|
||||
// Description:
|
||||
//
|
||||
// Dependencies:
|
||||
//
|
||||
// Revision:
|
||||
// Revision 0.01 - File Created
|
||||
// Additional Comments:
|
||||
//
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
module PC (
|
||||
input wire rst,
|
||||
input wire clk,
|
||||
input wire [31:0] offset,
|
||||
input wire pc_inc,
|
||||
output reg [31:0] PCdata
|
||||
);
|
||||
always @(posedge clk or posedge rst) begin
|
||||
if (rst) begin
|
||||
PCdata <= 32'h00000000;
|
||||
end
|
||||
else begin
|
||||
if (pc_inc) begin
|
||||
PCdata <= PCdata + 1;
|
||||
end
|
||||
else begin
|
||||
PCdata <= PCdata + offset;
|
||||
end
|
||||
end
|
||||
end
|
||||
endmodule
|
||||
37
Exp2/Exp2.srcs/sources_1/new/RAM.v
Normal file
37
Exp2/Exp2.srcs/sources_1/new/RAM.v
Normal file
@@ -0,0 +1,37 @@
|
||||
`timescale 1ns / 1ps
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company:
|
||||
// Engineer:
|
||||
//
|
||||
// Create Date: 2025/05/30 20:50:37
|
||||
// Design Name:
|
||||
// Module Name: RAM
|
||||
// Project Name:
|
||||
// Target Devices:
|
||||
// Tool Versions:
|
||||
// Description:
|
||||
//
|
||||
// Dependencies:
|
||||
//
|
||||
// Revision:
|
||||
// Revision 0.01 - File Created
|
||||
// Additional Comments:
|
||||
//
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
module RAM (
|
||||
input wire clk,
|
||||
input wire MemWrEn,
|
||||
input wire [31:0] addr,
|
||||
input wire [31:0] data_in,
|
||||
output wire [31:0] data_out
|
||||
);
|
||||
reg [31:0] memory_array [2^32-1:0];
|
||||
always @(posedge clk) begin
|
||||
if (MemWrEn) begin
|
||||
memory_array[addr] <= data_in;
|
||||
end
|
||||
end
|
||||
assign data_out = memory_array[addr];
|
||||
endmodule
|
||||
41
Exp2/Exp2.srcs/sources_1/new/Registers.v
Normal file
41
Exp2/Exp2.srcs/sources_1/new/Registers.v
Normal file
@@ -0,0 +1,41 @@
|
||||
`timescale 1ns / 1ps
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company:
|
||||
// Engineer:
|
||||
//
|
||||
// Create Date: 2025/05/30 20:49:51
|
||||
// Design Name:
|
||||
// Module Name: Registers
|
||||
// Project Name:
|
||||
// Target Devices:
|
||||
// Tool Versions:
|
||||
// Description:
|
||||
//
|
||||
// Dependencies:
|
||||
//
|
||||
// Revision:
|
||||
// Revision 0.01 - File Created
|
||||
// Additional Comments:
|
||||
//
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
module Registers (
|
||||
input wire clk,
|
||||
input wire RegWr,
|
||||
input wire [4:0] Ra,
|
||||
input wire [4:0] Rb,
|
||||
input wire [4:0] Rw,
|
||||
input wire [31:0] busW,
|
||||
output wire [31:0] busA,
|
||||
output wire [31:0] busB
|
||||
);
|
||||
reg [31:0] register_file [31:0];
|
||||
always @(posedge clk) begin
|
||||
if (RegWr && (Rw != 5'b00000)) begin
|
||||
register_file[Rw] <= busW;
|
||||
end
|
||||
end
|
||||
assign busA = (Ra == 5'b00000) ? 32'h00000000 : register_file[Ra];
|
||||
assign busB = (Rb == 5'b00000) ? 32'h00000000 : register_file[Rb];
|
||||
endmodule
|
||||
162
Exp2/Exp2.xpr
Normal file
162
Exp2/Exp2.xpr
Normal file
@@ -0,0 +1,162 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<!-- Product Version: Vivado v2018.1 (64-bit) -->
|
||||
<!-- -->
|
||||
<!-- Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. -->
|
||||
|
||||
<Project Version="7" Minor="36" Path="D:/Schoolwork/ComputerComposition/Exp2/Exp2.xpr">
|
||||
<DefaultLaunch Dir="$PRUNDIR"/>
|
||||
<Configuration>
|
||||
<Option Name="Id" Val="f4d37796f83345268710a003d248692f"/>
|
||||
<Option Name="Part" Val="xc7a35tcsg324-1"/>
|
||||
<Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
|
||||
<Option Name="CompiledLibDirXSim" Val=""/>
|
||||
<Option Name="CompiledLibDirModelSim" Val="$PCACHEDIR/compile_simlib/modelsim"/>
|
||||
<Option Name="CompiledLibDirQuesta" Val="$PCACHEDIR/compile_simlib/questa"/>
|
||||
<Option Name="CompiledLibDirIES" Val="$PCACHEDIR/compile_simlib/ies"/>
|
||||
<Option Name="CompiledLibDirXcelium" Val="$PCACHEDIR/compile_simlib/xcelium"/>
|
||||
<Option Name="CompiledLibDirVCS" Val="$PCACHEDIR/compile_simlib/vcs"/>
|
||||
<Option Name="CompiledLibDirRiviera" Val="$PCACHEDIR/compile_simlib/riviera"/>
|
||||
<Option Name="CompiledLibDirActivehdl" Val="$PCACHEDIR/compile_simlib/activehdl"/>
|
||||
<Option Name="BoardPart" Val=""/>
|
||||
<Option Name="ActiveSimSet" Val="sim_1"/>
|
||||
<Option Name="DefaultLib" Val="xil_defaultlib"/>
|
||||
<Option Name="ProjectType" Val="Default"/>
|
||||
<Option Name="IPOutputRepo" Val="$PCACHEDIR/ip"/>
|
||||
<Option Name="IPCachePermission" Val="read"/>
|
||||
<Option Name="IPCachePermission" Val="write"/>
|
||||
<Option Name="EnableCoreContainer" Val="FALSE"/>
|
||||
<Option Name="CreateRefXciForCoreContainers" Val="FALSE"/>
|
||||
<Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
|
||||
<Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
|
||||
<Option Name="EnableBDX" Val="FALSE"/>
|
||||
<Option Name="DSAVendor" Val="xilinx"/>
|
||||
<Option Name="DSANumComputeUnits" Val="60"/>
|
||||
<Option Name="WTXSimLaunchSim" Val="0"/>
|
||||
<Option Name="WTModelSimLaunchSim" Val="0"/>
|
||||
<Option Name="WTQuestaLaunchSim" Val="0"/>
|
||||
<Option Name="WTIesLaunchSim" Val="0"/>
|
||||
<Option Name="WTVcsLaunchSim" Val="0"/>
|
||||
<Option Name="WTRivieraLaunchSim" Val="0"/>
|
||||
<Option Name="WTActivehdlLaunchSim" Val="0"/>
|
||||
<Option Name="WTXSimExportSim" Val="0"/>
|
||||
<Option Name="WTModelSimExportSim" Val="0"/>
|
||||
<Option Name="WTQuestaExportSim" Val="0"/>
|
||||
<Option Name="WTIesExportSim" Val="0"/>
|
||||
<Option Name="WTVcsExportSim" Val="0"/>
|
||||
<Option Name="WTRivieraExportSim" Val="0"/>
|
||||
<Option Name="WTActivehdlExportSim" Val="0"/>
|
||||
<Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
|
||||
<Option Name="XSimRadix" Val="hex"/>
|
||||
<Option Name="XSimTimeUnit" Val="ns"/>
|
||||
<Option Name="XSimArrayDisplayLimit" Val="1024"/>
|
||||
<Option Name="XSimTraceLimit" Val="65536"/>
|
||||
<Option Name="SimTypes" Val="rtl"/>
|
||||
</Configuration>
|
||||
<FileSets Version="1" Minor="31">
|
||||
<FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1">
|
||||
<Filter Type="Srcs"/>
|
||||
<File Path="$PSRCDIR/sources_1/new/DR.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PSRCDIR/sources_1/new/PC.v">
|
||||
<FileInfo>
|
||||
<Attr Name="AutoDisabled" Val="1"/>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PSRCDIR/sources_1/new/Registers.v">
|
||||
<FileInfo>
|
||||
<Attr Name="AutoDisabled" Val="1"/>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PSRCDIR/sources_1/new/RAM.v">
|
||||
<FileInfo>
|
||||
<Attr Name="AutoDisabled" Val="1"/>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<Config>
|
||||
<Option Name="DesignMode" Val="RTL"/>
|
||||
<Option Name="TopModule" Val="DR"/>
|
||||
<Option Name="TopAutoSet" Val="TRUE"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1">
|
||||
<Filter Type="Constrs"/>
|
||||
<Config>
|
||||
<Option Name="ConstrsType" Val="XDC"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1">
|
||||
<Config>
|
||||
<Option Name="DesignMode" Val="RTL"/>
|
||||
<Option Name="TopModule" Val="DR"/>
|
||||
<Option Name="TopLib" Val="xil_defaultlib"/>
|
||||
<Option Name="TopAutoSet" Val="TRUE"/>
|
||||
<Option Name="TransportPathDelay" Val="0"/>
|
||||
<Option Name="TransportIntDelay" Val="0"/>
|
||||
<Option Name="SrcSet" Val="sources_1"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
</FileSets>
|
||||
<Simulators>
|
||||
<Simulator Name="XSim">
|
||||
<Option Name="Description" Val="Vivado Simulator"/>
|
||||
<Option Name="CompiledLib" Val="0"/>
|
||||
</Simulator>
|
||||
<Simulator Name="ModelSim">
|
||||
<Option Name="Description" Val="ModelSim Simulator"/>
|
||||
</Simulator>
|
||||
<Simulator Name="Questa">
|
||||
<Option Name="Description" Val="Questa Advanced Simulator"/>
|
||||
</Simulator>
|
||||
<Simulator Name="Riviera">
|
||||
<Option Name="Description" Val="Riviera-PRO Simulator"/>
|
||||
</Simulator>
|
||||
<Simulator Name="ActiveHDL">
|
||||
<Option Name="Description" Val="Active-HDL Simulator"/>
|
||||
</Simulator>
|
||||
</Simulators>
|
||||
<Runs Version="1" Minor="10">
|
||||
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a35tcsg324-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2018">
|
||||
<Desc>Vivado Synthesis Defaults</Desc>
|
||||
</StratHandle>
|
||||
<Step Id="synth_design"/>
|
||||
</Strategy>
|
||||
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2018"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
</Run>
|
||||
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcsg324-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2018">
|
||||
<Desc>Default settings for Implementation.</Desc>
|
||||
</StratHandle>
|
||||
<Step Id="init_design"/>
|
||||
<Step Id="opt_design"/>
|
||||
<Step Id="power_opt_design"/>
|
||||
<Step Id="place_design"/>
|
||||
<Step Id="post_place_power_opt_design"/>
|
||||
<Step Id="phys_opt_design"/>
|
||||
<Step Id="route_design"/>
|
||||
<Step Id="post_route_phys_opt_design"/>
|
||||
<Step Id="write_bitstream"/>
|
||||
</Strategy>
|
||||
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2018"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
</Run>
|
||||
</Runs>
|
||||
<Board/>
|
||||
</Project>
|
||||
BIN
Exp2Report.docx
Normal file
BIN
Exp2Report.docx
Normal file
Binary file not shown.
57
Exp3/Exp3.cache/wt/webtalk_pa.xml
Normal file
57
Exp3/Exp3.cache/wt/webtalk_pa.xml
Normal file
@@ -0,0 +1,57 @@
|
||||
<?xml version="1.0" encoding="UTF-8" ?>
|
||||
<document>
|
||||
<!--The data in this file is primarily intended for consumption by Xilinx tools.
|
||||
The structure and the elements are likely to change over the next few releases.
|
||||
This means code written to parse this file will need to be revisited each subsequent release.-->
|
||||
<application name="pa" timeStamp="Fri Jun 13 18:58:17 2025">
|
||||
<section name="Project Information" visible="false">
|
||||
<property name="ProjectID" value="63b83e631b0241febe9a3ce66a721511" type="ProjectID"/>
|
||||
<property name="ProjectIteration" value="1" type="ProjectIteration"/>
|
||||
</section>
|
||||
<section name="PlanAhead Usage" visible="true">
|
||||
<item name="Project Data">
|
||||
<property name="SrcSetCount" value="1" type="SrcSetCount"/>
|
||||
<property name="ConstraintSetCount" value="1" type="ConstraintSetCount"/>
|
||||
<property name="DesignMode" value="RTL" type="DesignMode"/>
|
||||
<property name="SynthesisStrategy" value="Vivado Synthesis Defaults" type="SynthesisStrategy"/>
|
||||
<property name="ImplStrategy" value="Vivado Implementation Defaults" type="ImplStrategy"/>
|
||||
</item>
|
||||
<item name="Java Command Handlers">
|
||||
<property name="AddSources" value="2" type="JavaHandler"/>
|
||||
<property name="NewProject" value="1" type="JavaHandler"/>
|
||||
<property name="ToolsSettings" value="3" type="JavaHandler"/>
|
||||
</item>
|
||||
<item name="Gui Handlers">
|
||||
<property name="AbstractFileView_RELOAD" value="1" type="GuiHandlerData"/>
|
||||
<property name="BaseDialog_APPLY" value="5" type="GuiHandlerData"/>
|
||||
<property name="BaseDialog_CANCEL" value="1" type="GuiHandlerData"/>
|
||||
<property name="BaseDialog_OK" value="12" type="GuiHandlerData"/>
|
||||
<property name="ConfirmSaveTextEditsDialog_CANCEL" value="1" type="GuiHandlerData"/>
|
||||
<property name="CreateSrcFileDialog_FILE_NAME" value="7" type="GuiHandlerData"/>
|
||||
<property name="FPGAChooser_FPGA_TABLE" value="1" type="GuiHandlerData"/>
|
||||
<property name="FileSetPanel_FILE_SET_PANEL_TREE" value="19" type="GuiHandlerData"/>
|
||||
<property name="GettingStartedView_CREATE_NEW_PROJECT" value="1" type="GuiHandlerData"/>
|
||||
<property name="MainMenuMgr_FLOW" value="2" type="GuiHandlerData"/>
|
||||
<property name="MainMenuMgr_REPORTS" value="12" type="GuiHandlerData"/>
|
||||
<property name="MainMenuMgr_TOOLS" value="12" type="GuiHandlerData"/>
|
||||
<property name="MainMenuMgr_WINDOW" value="2" type="GuiHandlerData"/>
|
||||
<property name="PACommandNames_ADD_SOURCES" value="2" type="GuiHandlerData"/>
|
||||
<property name="PAViews_CODE" value="2" type="GuiHandlerData"/>
|
||||
<property name="ProjectNameChooser_PROJECT_NAME" value="1" type="GuiHandlerData"/>
|
||||
<property name="RDICommands_COPY" value="1" type="GuiHandlerData"/>
|
||||
<property name="RDICommands_CUSTOM_COMMANDS" value="2" type="GuiHandlerData"/>
|
||||
<property name="RDICommands_SETTINGS" value="3" type="GuiHandlerData"/>
|
||||
<property name="SettingsDialog_OPTIONS_TREE" value="17" type="GuiHandlerData"/>
|
||||
<property name="SettingsEditorPage_USE_THIS_DROP_DOWN_LIST_BOX_TO_SELECT" value="2" type="GuiHandlerData"/>
|
||||
<property name="SrcChooserPanel_CREATE_FILE" value="6" type="GuiHandlerData"/>
|
||||
<property name="SrcFilePropPanels_LIBRARY" value="1" type="GuiHandlerData"/>
|
||||
<property name="SyntheticaGettingStartedView_RECENT_PROJECTS" value="1" type="GuiHandlerData"/>
|
||||
</item>
|
||||
<item name="Other">
|
||||
<property name="GuiMode" value="5" type="GuiMode"/>
|
||||
<property name="BatchMode" value="0" type="BatchMode"/>
|
||||
<property name="TclMode" value="1" type="TclMode"/>
|
||||
</item>
|
||||
</section>
|
||||
</application>
|
||||
</document>
|
||||
0
Exp3/Exp3.srcs/sources_1/new/ALU.v
Normal file
0
Exp3/Exp3.srcs/sources_1/new/ALU.v
Normal file
0
Exp3/Exp3.srcs/sources_1/new/DataRAM.v
Normal file
0
Exp3/Exp3.srcs/sources_1/new/DataRAM.v
Normal file
76
Exp3/Exp3.srcs/sources_1/new/Datapath.v
Normal file
76
Exp3/Exp3.srcs/sources_1/new/Datapath.v
Normal file
@@ -0,0 +1,76 @@
|
||||
`timescale 1ns / 1ps
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company:
|
||||
// Engineer:
|
||||
//
|
||||
// Create Date: 2025/06/06 15:26:45
|
||||
// Design Name:
|
||||
// Module Name: Datapath
|
||||
// Project Name:
|
||||
// Target Devices:
|
||||
// Tool Versions:
|
||||
// Description:
|
||||
//
|
||||
// Dependencies:
|
||||
//
|
||||
// Revision:
|
||||
// Revision 0.01 - File Created
|
||||
// Additional Comments:
|
||||
//
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
module DataPath (
|
||||
input wire clk,
|
||||
input wire rst,
|
||||
input wire [31:0] Instr,
|
||||
input wire srcReg,
|
||||
input wire ALUBsrc,
|
||||
input wire MemToReg,
|
||||
input wire RegWr,
|
||||
input wire MemWrEn,
|
||||
input wire [2:0] ALUop,
|
||||
input wire [1:0] Extop
|
||||
);
|
||||
wire [4:0] rd = Instr[4:0];
|
||||
wire [4:0] rj = Instr[9:5];
|
||||
wire [4:0] rk = Instr[14:10];
|
||||
wire [31:0] immExt;
|
||||
Ext u_ext (
|
||||
.DataIn (Instr),
|
||||
.Extop (Extop),
|
||||
.DataOut(immExt)
|
||||
);
|
||||
wire [4:0] Rb_sel = srcReg ? rd : rk;
|
||||
wire [31:0] busA, busB_reg;
|
||||
wire [31:0] WriteData;
|
||||
Registers u_regs (
|
||||
.clk (clk),
|
||||
.RegWr(RegWr),
|
||||
.Ra (rj),
|
||||
.Rb (Rb_sel),
|
||||
.Rw (rd),
|
||||
.busW (WriteData),
|
||||
.busA (busA),
|
||||
.busB (busB_reg)
|
||||
);
|
||||
wire [31:0] aluB = ALUBsrc ? immExt : busB_reg;
|
||||
wire [31:0] aluResult;
|
||||
wire aluZero;
|
||||
ALU u_alu (
|
||||
.a (busA),
|
||||
.b (aluB),
|
||||
.op (ALUop),
|
||||
.result (aluResult),
|
||||
.Zero (aluZero)
|
||||
);
|
||||
wire [31:0] ramDataOut;
|
||||
DataRAM u_dram (
|
||||
.clk (clk),
|
||||
.MemWrEn (MemWrEn),
|
||||
.addr (aluResult),
|
||||
.data_in (busB_reg),
|
||||
.data_out(ramDataOut)
|
||||
);
|
||||
assign WriteData = MemToReg ? ramDataOut : aluResult;
|
||||
endmodule
|
||||
0
Exp3/Exp3.srcs/sources_1/new/Ext.v
Normal file
0
Exp3/Exp3.srcs/sources_1/new/Ext.v
Normal file
26
Exp3/Exp3.srcs/sources_1/new/Mux.v
Normal file
26
Exp3/Exp3.srcs/sources_1/new/Mux.v
Normal file
@@ -0,0 +1,26 @@
|
||||
`timescale 1ns / 1ps
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company:
|
||||
// Engineer:
|
||||
//
|
||||
// Create Date: 2025/06/06 15:29:28
|
||||
// Design Name:
|
||||
// Module Name: Mux
|
||||
// Project Name:
|
||||
// Target Devices:
|
||||
// Tool Versions:
|
||||
// Description:
|
||||
//
|
||||
// Dependencies:
|
||||
//
|
||||
// Revision:
|
||||
// Revision 0.01 - File Created
|
||||
// Additional Comments:
|
||||
//
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
module Mux(
|
||||
|
||||
);
|
||||
endmodule
|
||||
0
Exp3/Exp3.srcs/sources_1/new/Registers.v
Normal file
0
Exp3/Exp3.srcs/sources_1/new/Registers.v
Normal file
179
Exp3/Exp3.xpr
Normal file
179
Exp3/Exp3.xpr
Normal file
@@ -0,0 +1,179 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<!-- Product Version: Vivado v2018.1 (64-bit) -->
|
||||
<!-- -->
|
||||
<!-- Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. -->
|
||||
|
||||
<Project Version="7" Minor="36" Path="D:/Schoolwork/ComputerComposition/Exp3/Exp3.xpr">
|
||||
<DefaultLaunch Dir="$PRUNDIR"/>
|
||||
<Configuration>
|
||||
<Option Name="Id" Val="fd2f5e9babf446cd859e616a9aaddfec"/>
|
||||
<Option Name="Part" Val="xc7a35tcsg324-1"/>
|
||||
<Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
|
||||
<Option Name="CompiledLibDirXSim" Val=""/>
|
||||
<Option Name="CompiledLibDirModelSim" Val="$PCACHEDIR/compile_simlib/modelsim"/>
|
||||
<Option Name="CompiledLibDirQuesta" Val="$PCACHEDIR/compile_simlib/questa"/>
|
||||
<Option Name="CompiledLibDirIES" Val="$PCACHEDIR/compile_simlib/ies"/>
|
||||
<Option Name="CompiledLibDirXcelium" Val="$PCACHEDIR/compile_simlib/xcelium"/>
|
||||
<Option Name="CompiledLibDirVCS" Val="$PCACHEDIR/compile_simlib/vcs"/>
|
||||
<Option Name="CompiledLibDirRiviera" Val="$PCACHEDIR/compile_simlib/riviera"/>
|
||||
<Option Name="CompiledLibDirActivehdl" Val="$PCACHEDIR/compile_simlib/activehdl"/>
|
||||
<Option Name="BoardPart" Val=""/>
|
||||
<Option Name="ActiveSimSet" Val="sim_1"/>
|
||||
<Option Name="DefaultLib" Val="xil_defaultlib"/>
|
||||
<Option Name="ProjectType" Val="Default"/>
|
||||
<Option Name="IPOutputRepo" Val="$PCACHEDIR/ip"/>
|
||||
<Option Name="IPCachePermission" Val="read"/>
|
||||
<Option Name="IPCachePermission" Val="write"/>
|
||||
<Option Name="EnableCoreContainer" Val="FALSE"/>
|
||||
<Option Name="CreateRefXciForCoreContainers" Val="FALSE"/>
|
||||
<Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
|
||||
<Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
|
||||
<Option Name="EnableBDX" Val="FALSE"/>
|
||||
<Option Name="DSAVendor" Val="xilinx"/>
|
||||
<Option Name="DSANumComputeUnits" Val="60"/>
|
||||
<Option Name="WTXSimLaunchSim" Val="0"/>
|
||||
<Option Name="WTModelSimLaunchSim" Val="0"/>
|
||||
<Option Name="WTQuestaLaunchSim" Val="0"/>
|
||||
<Option Name="WTIesLaunchSim" Val="0"/>
|
||||
<Option Name="WTVcsLaunchSim" Val="0"/>
|
||||
<Option Name="WTRivieraLaunchSim" Val="0"/>
|
||||
<Option Name="WTActivehdlLaunchSim" Val="0"/>
|
||||
<Option Name="WTXSimExportSim" Val="0"/>
|
||||
<Option Name="WTModelSimExportSim" Val="0"/>
|
||||
<Option Name="WTQuestaExportSim" Val="0"/>
|
||||
<Option Name="WTIesExportSim" Val="0"/>
|
||||
<Option Name="WTVcsExportSim" Val="0"/>
|
||||
<Option Name="WTRivieraExportSim" Val="0"/>
|
||||
<Option Name="WTActivehdlExportSim" Val="0"/>
|
||||
<Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
|
||||
<Option Name="XSimRadix" Val="hex"/>
|
||||
<Option Name="XSimTimeUnit" Val="ns"/>
|
||||
<Option Name="XSimArrayDisplayLimit" Val="1024"/>
|
||||
<Option Name="XSimTraceLimit" Val="65536"/>
|
||||
<Option Name="SimTypes" Val="rtl"/>
|
||||
</Configuration>
|
||||
<FileSets Version="1" Minor="31">
|
||||
<FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1">
|
||||
<Filter Type="Srcs"/>
|
||||
<File Path="$PSRCDIR/sources_1/new/Datapath.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PSRCDIR/sources_1/new/Mux.v">
|
||||
<FileInfo>
|
||||
<Attr Name="AutoDisabled" Val="1"/>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PSRCDIR/sources_1/new/Registers.v">
|
||||
<FileInfo>
|
||||
<Attr Name="AutoDisabled" Val="1"/>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PSRCDIR/sources_1/new/ALU.v">
|
||||
<FileInfo>
|
||||
<Attr Name="AutoDisabled" Val="1"/>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PSRCDIR/sources_1/new/DataRAM.v">
|
||||
<FileInfo>
|
||||
<Attr Name="AutoDisabled" Val="1"/>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PSRCDIR/sources_1/new/Ext.v">
|
||||
<FileInfo>
|
||||
<Attr Name="AutoDisabled" Val="1"/>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<Config>
|
||||
<Option Name="DesignMode" Val="RTL"/>
|
||||
<Option Name="TopModule" Val="DataPath"/>
|
||||
<Option Name="TopAutoSet" Val="TRUE"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1">
|
||||
<Filter Type="Constrs"/>
|
||||
<Config>
|
||||
<Option Name="ConstrsType" Val="XDC"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1">
|
||||
<Filter Type="Srcs"/>
|
||||
<Config>
|
||||
<Option Name="DesignMode" Val="RTL"/>
|
||||
<Option Name="TopModule" Val="DataPath"/>
|
||||
<Option Name="TopLib" Val="xil_defaultlib"/>
|
||||
<Option Name="TopAutoSet" Val="TRUE"/>
|
||||
<Option Name="TransportPathDelay" Val="0"/>
|
||||
<Option Name="TransportIntDelay" Val="0"/>
|
||||
<Option Name="SrcSet" Val="sources_1"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
</FileSets>
|
||||
<Simulators>
|
||||
<Simulator Name="XSim">
|
||||
<Option Name="Description" Val="Vivado Simulator"/>
|
||||
<Option Name="CompiledLib" Val="0"/>
|
||||
</Simulator>
|
||||
<Simulator Name="ModelSim">
|
||||
<Option Name="Description" Val="ModelSim Simulator"/>
|
||||
</Simulator>
|
||||
<Simulator Name="Questa">
|
||||
<Option Name="Description" Val="Questa Advanced Simulator"/>
|
||||
</Simulator>
|
||||
<Simulator Name="Riviera">
|
||||
<Option Name="Description" Val="Riviera-PRO Simulator"/>
|
||||
</Simulator>
|
||||
<Simulator Name="ActiveHDL">
|
||||
<Option Name="Description" Val="Active-HDL Simulator"/>
|
||||
</Simulator>
|
||||
</Simulators>
|
||||
<Runs Version="1" Minor="10">
|
||||
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a35tcsg324-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2018">
|
||||
<Desc>Vivado Synthesis Defaults</Desc>
|
||||
</StratHandle>
|
||||
<Step Id="synth_design"/>
|
||||
</Strategy>
|
||||
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2018"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
</Run>
|
||||
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcsg324-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2018">
|
||||
<Desc>Default settings for Implementation.</Desc>
|
||||
</StratHandle>
|
||||
<Step Id="init_design"/>
|
||||
<Step Id="opt_design"/>
|
||||
<Step Id="power_opt_design"/>
|
||||
<Step Id="place_design"/>
|
||||
<Step Id="post_place_power_opt_design"/>
|
||||
<Step Id="phys_opt_design"/>
|
||||
<Step Id="route_design"/>
|
||||
<Step Id="post_route_phys_opt_design"/>
|
||||
<Step Id="write_bitstream"/>
|
||||
</Strategy>
|
||||
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2018"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
</Run>
|
||||
</Runs>
|
||||
<Board/>
|
||||
</Project>
|
||||
BIN
Exp3Report.docx
Normal file
BIN
Exp3Report.docx
Normal file
Binary file not shown.
40
Exp4/Exp4.cache/wt/webtalk_pa.xml
Normal file
40
Exp4/Exp4.cache/wt/webtalk_pa.xml
Normal file
@@ -0,0 +1,40 @@
|
||||
<?xml version="1.0" encoding="UTF-8" ?>
|
||||
<document>
|
||||
<!--The data in this file is primarily intended for consumption by Xilinx tools.
|
||||
The structure and the elements are likely to change over the next few releases.
|
||||
This means code written to parse this file will need to be revisited each subsequent release.-->
|
||||
<application name="pa" timeStamp="Fri Jun 13 18:58:21 2025">
|
||||
<section name="Project Information" visible="false">
|
||||
<property name="ProjectID" value="8cf578bb90b940d8a64446f0d623b5fb" type="ProjectID"/>
|
||||
<property name="ProjectIteration" value="1" type="ProjectIteration"/>
|
||||
</section>
|
||||
<section name="PlanAhead Usage" visible="true">
|
||||
<item name="Project Data">
|
||||
<property name="SrcSetCount" value="1" type="SrcSetCount"/>
|
||||
<property name="ConstraintSetCount" value="1" type="ConstraintSetCount"/>
|
||||
<property name="DesignMode" value="RTL" type="DesignMode"/>
|
||||
<property name="SynthesisStrategy" value="Vivado Synthesis Defaults" type="SynthesisStrategy"/>
|
||||
<property name="ImplStrategy" value="Vivado Implementation Defaults" type="ImplStrategy"/>
|
||||
</item>
|
||||
<item name="Java Command Handlers">
|
||||
<property name="AddSources" value="1" type="JavaHandler"/>
|
||||
<property name="NewProject" value="1" type="JavaHandler"/>
|
||||
</item>
|
||||
<item name="Gui Handlers">
|
||||
<property name="BaseDialog_OK" value="2" type="GuiHandlerData"/>
|
||||
<property name="CreateSrcFileDialog_FILE_NAME" value="1" type="GuiHandlerData"/>
|
||||
<property name="FPGAChooser_FPGA_TABLE" value="3" type="GuiHandlerData"/>
|
||||
<property name="FileSetPanel_FILE_SET_PANEL_TREE" value="3" type="GuiHandlerData"/>
|
||||
<property name="FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE" value="1" type="GuiHandlerData"/>
|
||||
<property name="GettingStartedView_CREATE_NEW_PROJECT" value="1" type="GuiHandlerData"/>
|
||||
<property name="ProjectNameChooser_PROJECT_NAME" value="1" type="GuiHandlerData"/>
|
||||
<property name="SrcChooserPanel_CREATE_FILE" value="1" type="GuiHandlerData"/>
|
||||
</item>
|
||||
<item name="Other">
|
||||
<property name="GuiMode" value="4" type="GuiMode"/>
|
||||
<property name="BatchMode" value="0" type="BatchMode"/>
|
||||
<property name="TclMode" value="1" type="TclMode"/>
|
||||
</item>
|
||||
</section>
|
||||
</application>
|
||||
</document>
|
||||
107
Exp4/Exp4.srcs/sources_1/new/Controller.v
Normal file
107
Exp4/Exp4.srcs/sources_1/new/Controller.v
Normal file
@@ -0,0 +1,107 @@
|
||||
`timescale 1ns / 1ps
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company:
|
||||
// Engineer:
|
||||
//
|
||||
// Create Date: 2025/06/13 14:23:19
|
||||
// Design Name:
|
||||
// Module Name: Controller
|
||||
// Project Name:
|
||||
// Target Devices:
|
||||
// Tool Versions:
|
||||
// Description:
|
||||
//
|
||||
// Dependencies:
|
||||
//
|
||||
// Revision:
|
||||
// Revision 0.01 - File Created
|
||||
// Additional Comments:
|
||||
//
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
module Controller (
|
||||
input [31:15] Instr,
|
||||
output reg RegWr,
|
||||
output reg ALUBsrc,
|
||||
output reg MemToReg,
|
||||
output reg MemWrEn,
|
||||
output reg srcReg,
|
||||
output reg [2:0] AluCtrl,
|
||||
output reg [1:0] ExtOp
|
||||
);
|
||||
localparam ADD_W = 17'b00000010001000000;
|
||||
localparam SLT_W = 17'b00000010010000000;
|
||||
localparam SLTU_W = 17'b00000010011000000;
|
||||
localparam LU12I_W = 7'b0001010;
|
||||
localparam LD_W = 7'b0010100;
|
||||
localparam ST_W = 7'b0010101;
|
||||
localparam ALU_ADD = 3'b000;
|
||||
localparam ALU_SLT = 3'b101;
|
||||
localparam ALU_SLTU = 3'b110;
|
||||
localparam EXT_SIGN_12 = 2'b00;
|
||||
localparam EXT_ZERO_20 = 2'b10;
|
||||
always @(*) begin
|
||||
RegWr = 1'b0;
|
||||
ALUBsrc = 1'b0;
|
||||
MemToReg = 1'b0;
|
||||
MemWrEn = 1'b0;
|
||||
srcReg = 1'b0;
|
||||
AluCtrl = 3'bxxx;
|
||||
ExtOp = 2'bxx;
|
||||
if (Instr == ADD_W) begin
|
||||
RegWr = 1'b1;
|
||||
ALUBsrc = 1'b0;
|
||||
MemToReg = 1'b0;
|
||||
MemWrEn = 1'b0;
|
||||
srcReg = 1'b0;
|
||||
AluCtrl = ALU_ADD;
|
||||
ExtOp = 2'bxx;
|
||||
end
|
||||
else if (Instr == SLT_W) begin
|
||||
RegWr = 1'b1;
|
||||
ALUBsrc = 1'b0;
|
||||
MemToReg = 1'b0;
|
||||
MemWrEn = 1'b0;
|
||||
srcReg = 1'b0;
|
||||
AluCtrl = ALU_SLT;
|
||||
ExtOp = 2'bxx;
|
||||
end
|
||||
else if (Instr == SLTU_W) begin
|
||||
RegWr = 1'b1;
|
||||
ALUBsrc = 1'b0;
|
||||
MemToReg = 1'b0;
|
||||
MemWrEn = 1'b0;
|
||||
srcReg = 1'b0;
|
||||
AluCtrl = ALU_SLTU;
|
||||
ExtOp = 2'bxx;
|
||||
end
|
||||
else if (Instr[31:25] == LU12I_W) begin
|
||||
RegWr = 1'b1;
|
||||
ALUBsrc = 1'b1;
|
||||
MemToReg = 1'b0;
|
||||
MemWrEn = 1'b0;
|
||||
srcReg = 1'b0;
|
||||
AluCtrl = ALU_ADD;
|
||||
ExtOp = EXT_ZERO_20;
|
||||
end
|
||||
else if (Instr[31:25] == LD_W) begin
|
||||
RegWr = 1'b1;
|
||||
ALUBsrc = 1'b1;
|
||||
MemToReg = 1'b1;
|
||||
MemWrEn = 1'b0;
|
||||
srcReg = 1'b0;
|
||||
AluCtrl = ALU_ADD;
|
||||
ExtOp = EXT_SIGN_12;
|
||||
end
|
||||
else if (Instr[31:25] == ST_W) begin
|
||||
RegWr = 1'b0;
|
||||
ALUBsrc = 1'b1;
|
||||
MemToReg = 1'bx;
|
||||
MemWrEn = 1'b1;
|
||||
srcReg = 1'b1;
|
||||
AluCtrl = ALU_ADD;
|
||||
ExtOp = EXT_SIGN_12;
|
||||
end
|
||||
end
|
||||
endmodule
|
||||
138
Exp4/Exp4.xpr
Normal file
138
Exp4/Exp4.xpr
Normal file
@@ -0,0 +1,138 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<!-- Product Version: Vivado v2018.1 (64-bit) -->
|
||||
<!-- -->
|
||||
<!-- Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. -->
|
||||
|
||||
<Project Version="7" Minor="36" Path="D:/Schoolwork/ComputerComposition/Exp4/Exp4.xpr">
|
||||
<DefaultLaunch Dir="$PRUNDIR"/>
|
||||
<Configuration>
|
||||
<Option Name="Id" Val="7ebecf71bb874ff395b204b0a04ff716"/>
|
||||
<Option Name="Part" Val="xc7a35tcsg324-1"/>
|
||||
<Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
|
||||
<Option Name="CompiledLibDirXSim" Val=""/>
|
||||
<Option Name="CompiledLibDirModelSim" Val="$PCACHEDIR/compile_simlib/modelsim"/>
|
||||
<Option Name="CompiledLibDirQuesta" Val="$PCACHEDIR/compile_simlib/questa"/>
|
||||
<Option Name="CompiledLibDirIES" Val="$PCACHEDIR/compile_simlib/ies"/>
|
||||
<Option Name="CompiledLibDirXcelium" Val="$PCACHEDIR/compile_simlib/xcelium"/>
|
||||
<Option Name="CompiledLibDirVCS" Val="$PCACHEDIR/compile_simlib/vcs"/>
|
||||
<Option Name="CompiledLibDirRiviera" Val="$PCACHEDIR/compile_simlib/riviera"/>
|
||||
<Option Name="CompiledLibDirActivehdl" Val="$PCACHEDIR/compile_simlib/activehdl"/>
|
||||
<Option Name="BoardPart" Val=""/>
|
||||
<Option Name="ActiveSimSet" Val="sim_1"/>
|
||||
<Option Name="DefaultLib" Val="xil_defaultlib"/>
|
||||
<Option Name="ProjectType" Val="Default"/>
|
||||
<Option Name="IPOutputRepo" Val="$PCACHEDIR/ip"/>
|
||||
<Option Name="IPCachePermission" Val="read"/>
|
||||
<Option Name="IPCachePermission" Val="write"/>
|
||||
<Option Name="EnableCoreContainer" Val="FALSE"/>
|
||||
<Option Name="CreateRefXciForCoreContainers" Val="FALSE"/>
|
||||
<Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
|
||||
<Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
|
||||
<Option Name="EnableBDX" Val="FALSE"/>
|
||||
<Option Name="DSAVendor" Val="xilinx"/>
|
||||
<Option Name="DSANumComputeUnits" Val="60"/>
|
||||
<Option Name="WTXSimLaunchSim" Val="0"/>
|
||||
<Option Name="WTModelSimLaunchSim" Val="0"/>
|
||||
<Option Name="WTQuestaLaunchSim" Val="0"/>
|
||||
<Option Name="WTIesLaunchSim" Val="0"/>
|
||||
<Option Name="WTVcsLaunchSim" Val="0"/>
|
||||
<Option Name="WTRivieraLaunchSim" Val="0"/>
|
||||
<Option Name="WTActivehdlLaunchSim" Val="0"/>
|
||||
<Option Name="WTXSimExportSim" Val="0"/>
|
||||
<Option Name="WTModelSimExportSim" Val="0"/>
|
||||
<Option Name="WTQuestaExportSim" Val="0"/>
|
||||
<Option Name="WTIesExportSim" Val="0"/>
|
||||
<Option Name="WTVcsExportSim" Val="0"/>
|
||||
<Option Name="WTRivieraExportSim" Val="0"/>
|
||||
<Option Name="WTActivehdlExportSim" Val="0"/>
|
||||
<Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
|
||||
<Option Name="XSimRadix" Val="hex"/>
|
||||
<Option Name="XSimTimeUnit" Val="ns"/>
|
||||
<Option Name="XSimArrayDisplayLimit" Val="1024"/>
|
||||
<Option Name="XSimTraceLimit" Val="65536"/>
|
||||
<Option Name="SimTypes" Val="rtl"/>
|
||||
</Configuration>
|
||||
<FileSets Version="1" Minor="31">
|
||||
<FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1">
|
||||
<Filter Type="Srcs"/>
|
||||
<File Path="$PSRCDIR/sources_1/new/Controller.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<Config>
|
||||
<Option Name="DesignMode" Val="RTL"/>
|
||||
<Option Name="TopModule" Val="Controller"/>
|
||||
<Option Name="TopAutoSet" Val="TRUE"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1">
|
||||
<Filter Type="Constrs"/>
|
||||
<Config>
|
||||
<Option Name="ConstrsType" Val="XDC"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1">
|
||||
<Config>
|
||||
<Option Name="DesignMode" Val="RTL"/>
|
||||
<Option Name="TopModule" Val="Controller"/>
|
||||
<Option Name="TopLib" Val="xil_defaultlib"/>
|
||||
<Option Name="TopAutoSet" Val="TRUE"/>
|
||||
<Option Name="TransportPathDelay" Val="0"/>
|
||||
<Option Name="TransportIntDelay" Val="0"/>
|
||||
<Option Name="SrcSet" Val="sources_1"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
</FileSets>
|
||||
<Simulators>
|
||||
<Simulator Name="XSim">
|
||||
<Option Name="Description" Val="Vivado Simulator"/>
|
||||
<Option Name="CompiledLib" Val="0"/>
|
||||
</Simulator>
|
||||
<Simulator Name="ModelSim">
|
||||
<Option Name="Description" Val="ModelSim Simulator"/>
|
||||
</Simulator>
|
||||
<Simulator Name="Questa">
|
||||
<Option Name="Description" Val="Questa Advanced Simulator"/>
|
||||
</Simulator>
|
||||
<Simulator Name="Riviera">
|
||||
<Option Name="Description" Val="Riviera-PRO Simulator"/>
|
||||
</Simulator>
|
||||
<Simulator Name="ActiveHDL">
|
||||
<Option Name="Description" Val="Active-HDL Simulator"/>
|
||||
</Simulator>
|
||||
</Simulators>
|
||||
<Runs Version="1" Minor="10">
|
||||
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a35tcsg324-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2018">
|
||||
<Desc>Vivado Synthesis Defaults</Desc>
|
||||
</StratHandle>
|
||||
<Step Id="synth_design"/>
|
||||
</Strategy>
|
||||
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2018"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
</Run>
|
||||
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcsg324-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2018">
|
||||
<Desc>Default settings for Implementation.</Desc>
|
||||
</StratHandle>
|
||||
<Step Id="init_design"/>
|
||||
<Step Id="opt_design"/>
|
||||
<Step Id="power_opt_design"/>
|
||||
<Step Id="place_design"/>
|
||||
<Step Id="post_place_power_opt_design"/>
|
||||
<Step Id="phys_opt_design"/>
|
||||
<Step Id="route_design"/>
|
||||
<Step Id="post_route_phys_opt_design"/>
|
||||
<Step Id="write_bitstream"/>
|
||||
</Strategy>
|
||||
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2018"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
</Run>
|
||||
</Runs>
|
||||
<Board/>
|
||||
</Project>
|
||||
BIN
Exp4Report.docx
Normal file
BIN
Exp4Report.docx
Normal file
Binary file not shown.
1
Experiments/Exp1/Exp1.ip_user_files/README.txt
Normal file
1
Experiments/Exp1/Exp1.ip_user_files/README.txt
Normal file
@@ -0,0 +1 @@
|
||||
The files in this directory structure are automatically generated and managed by Vivado. Editing these files is not recommended.
|
||||
71
Experiments/Exp1/Exp1.sim/sim_1/behav/xsim/glbl.v
Normal file
71
Experiments/Exp1/Exp1.sim/sim_1/behav/xsim/glbl.v
Normal file
@@ -0,0 +1,71 @@
|
||||
// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
|
||||
`ifndef GLBL
|
||||
`define GLBL
|
||||
`timescale 1 ps / 1 ps
|
||||
|
||||
module glbl ();
|
||||
|
||||
parameter ROC_WIDTH = 100000;
|
||||
parameter TOC_WIDTH = 0;
|
||||
|
||||
//-------- STARTUP Globals --------------
|
||||
wire GSR;
|
||||
wire GTS;
|
||||
wire GWE;
|
||||
wire PRLD;
|
||||
tri1 p_up_tmp;
|
||||
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
|
||||
|
||||
wire PROGB_GLBL;
|
||||
wire CCLKO_GLBL;
|
||||
wire FCSBO_GLBL;
|
||||
wire [3:0] DO_GLBL;
|
||||
wire [3:0] DI_GLBL;
|
||||
|
||||
reg GSR_int;
|
||||
reg GTS_int;
|
||||
reg PRLD_int;
|
||||
|
||||
//-------- JTAG Globals --------------
|
||||
wire JTAG_TDO_GLBL;
|
||||
wire JTAG_TCK_GLBL;
|
||||
wire JTAG_TDI_GLBL;
|
||||
wire JTAG_TMS_GLBL;
|
||||
wire JTAG_TRST_GLBL;
|
||||
|
||||
reg JTAG_CAPTURE_GLBL;
|
||||
reg JTAG_RESET_GLBL;
|
||||
reg JTAG_SHIFT_GLBL;
|
||||
reg JTAG_UPDATE_GLBL;
|
||||
reg JTAG_RUNTEST_GLBL;
|
||||
|
||||
reg JTAG_SEL1_GLBL = 0;
|
||||
reg JTAG_SEL2_GLBL = 0 ;
|
||||
reg JTAG_SEL3_GLBL = 0;
|
||||
reg JTAG_SEL4_GLBL = 0;
|
||||
|
||||
reg JTAG_USER_TDO1_GLBL = 1'bz;
|
||||
reg JTAG_USER_TDO2_GLBL = 1'bz;
|
||||
reg JTAG_USER_TDO3_GLBL = 1'bz;
|
||||
reg JTAG_USER_TDO4_GLBL = 1'bz;
|
||||
|
||||
assign (strong1, weak0) GSR = GSR_int;
|
||||
assign (strong1, weak0) GTS = GTS_int;
|
||||
assign (weak1, weak0) PRLD = PRLD_int;
|
||||
|
||||
initial begin
|
||||
GSR_int = 1'b1;
|
||||
PRLD_int = 1'b1;
|
||||
#(ROC_WIDTH)
|
||||
GSR_int = 1'b0;
|
||||
PRLD_int = 1'b0;
|
||||
end
|
||||
|
||||
initial begin
|
||||
GTS_int = 1'b1;
|
||||
#(TOC_WIDTH)
|
||||
GTS_int = 1'b0;
|
||||
end
|
||||
|
||||
endmodule
|
||||
`endif
|
||||
11
Experiments/Exp1/Exp1.sim/sim_1/behav/xsim/tb_exp1.tcl
Normal file
11
Experiments/Exp1/Exp1.sim/sim_1/behav/xsim/tb_exp1.tcl
Normal file
@@ -0,0 +1,11 @@
|
||||
set curr_wave [current_wave_config]
|
||||
if { [string length $curr_wave] == 0 } {
|
||||
if { [llength [get_objects]] > 0} {
|
||||
add_wave /
|
||||
set_property needs_save false [current_wave_config]
|
||||
} else {
|
||||
send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
|
||||
}
|
||||
}
|
||||
|
||||
run 1000ns
|
||||
11
Experiments/Exp1/Exp1.sim/sim_1/behav/xsim/tb_exp1_vlog.prj
Normal file
11
Experiments/Exp1/Exp1.sim/sim_1/behav/xsim/tb_exp1_vlog.prj
Normal file
@@ -0,0 +1,11 @@
|
||||
# compile verilog/system verilog design source files
|
||||
verilog xil_defaultlib \
|
||||
"../../../../../Shared/ALU.v" \
|
||||
"../../../../../Shared/Ext.v" \
|
||||
"../../../../Exp1.srcs/sim_1/new/tb_exp1.v" \
|
||||
|
||||
# compile glbl module
|
||||
verilog xil_defaultlib "glbl.v"
|
||||
|
||||
# Do not sort compile order
|
||||
nosort
|
||||
12
Experiments/Exp1/Exp1.sim/sim_1/behav/xsim/webtalk.jou
Normal file
12
Experiments/Exp1/Exp1.sim/sim_1/behav/xsim/webtalk.jou
Normal file
@@ -0,0 +1,12 @@
|
||||
#-----------------------------------------------------------
|
||||
# Webtalk v2018.1 (64-bit)
|
||||
# SW Build 2188600 on Wed Apr 4 18:40:38 MDT 2018
|
||||
# IP Build 2185939 on Wed Apr 4 20:55:05 MDT 2018
|
||||
# Start of session at: Wed Jul 2 00:04:46 2025
|
||||
# Process ID: 16772
|
||||
# Current directory: D:/Schoolwork/ComputerComposition/Experiments/Exp1/Exp1.sim/sim_1/behav/xsim
|
||||
# Command line: wbtcv.exe -mode batch -source D:/Schoolwork/ComputerComposition/Experiments/Exp1/Exp1.sim/sim_1/behav/xsim/xsim.dir/tb_exp1_behav/webtalk/xsim_webtalk.tcl -notrace
|
||||
# Log file: D:/Schoolwork/ComputerComposition/Experiments/Exp1/Exp1.sim/sim_1/behav/xsim/webtalk.log
|
||||
# Journal file: D:/Schoolwork/ComputerComposition/Experiments/Exp1/Exp1.sim/sim_1/behav/xsim\webtalk.jou
|
||||
#-----------------------------------------------------------
|
||||
source D:/Schoolwork/ComputerComposition/Experiments/Exp1/Exp1.sim/sim_1/behav/xsim/xsim.dir/tb_exp1_behav/webtalk/xsim_webtalk.tcl -notrace
|
||||
BIN
Experiments/Exp1/Exp1.sim/sim_1/behav/xsim/xelab.pb
Normal file
BIN
Experiments/Exp1/Exp1.sim/sim_1/behav/xsim/xelab.pb
Normal file
Binary file not shown.
@@ -0,0 +1 @@
|
||||
-wto "37682ab63326475c8c4702befd41712b" --incr --debug "typical" --relax --mt "2" -L "xil_defaultlib" -L "unisims_ver" -L "unimacro_ver" -L "secureip" --snapshot "tb_exp1_behav" "xil_defaultlib.tb_exp1" "xil_defaultlib.glbl" -log "elaborate.log"
|
||||
@@ -0,0 +1 @@
|
||||
Breakpoint File Version 1.0
|
||||
@@ -0,0 +1,118 @@
|
||||
/**********************************************************************/
|
||||
/* ____ ____ */
|
||||
/* / /\/ / */
|
||||
/* /___/ \ / */
|
||||
/* \ \ \/ */
|
||||
/* \ \ Copyright (c) 2003-2013 Xilinx, Inc. */
|
||||
/* / / All Right Reserved. */
|
||||
/* /---/ /\ */
|
||||
/* \ \ / \ */
|
||||
/* \___\/\___\ */
|
||||
/**********************************************************************/
|
||||
|
||||
|
||||
#include "iki.h"
|
||||
#include <string.h>
|
||||
#include <math.h>
|
||||
#ifdef __GNUC__
|
||||
#include <stdlib.h>
|
||||
#else
|
||||
#include <malloc.h>
|
||||
#define alloca _alloca
|
||||
#endif
|
||||
/**********************************************************************/
|
||||
/* ____ ____ */
|
||||
/* / /\/ / */
|
||||
/* /___/ \ / */
|
||||
/* \ \ \/ */
|
||||
/* \ \ Copyright (c) 2003-2013 Xilinx, Inc. */
|
||||
/* / / All Right Reserved. */
|
||||
/* /---/ /\ */
|
||||
/* \ \ / \ */
|
||||
/* \___\/\___\ */
|
||||
/**********************************************************************/
|
||||
|
||||
|
||||
#include "iki.h"
|
||||
#include <string.h>
|
||||
#include <math.h>
|
||||
#ifdef __GNUC__
|
||||
#include <stdlib.h>
|
||||
#else
|
||||
#include <malloc.h>
|
||||
#define alloca _alloca
|
||||
#endif
|
||||
typedef void (*funcp)(char *, char *);
|
||||
extern int main(int, char**);
|
||||
extern void execute_6(char*, char *);
|
||||
extern void execute_16(char*, char *);
|
||||
extern void execute_17(char*, char *);
|
||||
extern void execute_18(char*, char *);
|
||||
extern void execute_19(char*, char *);
|
||||
extern void execute_20(char*, char *);
|
||||
extern void execute_21(char*, char *);
|
||||
extern void execute_22(char*, char *);
|
||||
extern void execute_3(char*, char *);
|
||||
extern void execute_5(char*, char *);
|
||||
extern void execute_11(char*, char *);
|
||||
extern void execute_12(char*, char *);
|
||||
extern void execute_13(char*, char *);
|
||||
extern void execute_14(char*, char *);
|
||||
extern void vlog_simple_process_execute_0_fast_no_reg_no_agg(char*, char*, char*);
|
||||
extern void execute_8(char*, char *);
|
||||
extern void execute_9(char*, char *);
|
||||
extern void execute_10(char*, char *);
|
||||
extern void execute_23(char*, char *);
|
||||
extern void execute_24(char*, char *);
|
||||
extern void execute_25(char*, char *);
|
||||
extern void execute_26(char*, char *);
|
||||
extern void execute_27(char*, char *);
|
||||
extern void vlog_transfunc_eventcallback(char*, char*, unsigned, unsigned, unsigned, char *);
|
||||
funcp funcTab[24] = {(funcp)execute_6, (funcp)execute_16, (funcp)execute_17, (funcp)execute_18, (funcp)execute_19, (funcp)execute_20, (funcp)execute_21, (funcp)execute_22, (funcp)execute_3, (funcp)execute_5, (funcp)execute_11, (funcp)execute_12, (funcp)execute_13, (funcp)execute_14, (funcp)vlog_simple_process_execute_0_fast_no_reg_no_agg, (funcp)execute_8, (funcp)execute_9, (funcp)execute_10, (funcp)execute_23, (funcp)execute_24, (funcp)execute_25, (funcp)execute_26, (funcp)execute_27, (funcp)vlog_transfunc_eventcallback};
|
||||
const int NumRelocateId= 24;
|
||||
|
||||
void relocate(char *dp)
|
||||
{
|
||||
iki_relocate(dp, "xsim.dir/tb_exp1_behav/xsim.reloc", (void **)funcTab, 24);
|
||||
|
||||
/*Populate the transaction function pointer field in the whole net structure */
|
||||
}
|
||||
|
||||
void sensitize(char *dp)
|
||||
{
|
||||
iki_sensitize(dp, "xsim.dir/tb_exp1_behav/xsim.reloc");
|
||||
}
|
||||
|
||||
void simulate(char *dp)
|
||||
{
|
||||
iki_schedule_processes_at_time_zero(dp, "xsim.dir/tb_exp1_behav/xsim.reloc");
|
||||
// Initialize Verilog nets in mixed simulation, for the cases when the value at time 0 should be propagated from the mixed language Vhdl net
|
||||
iki_execute_processes();
|
||||
|
||||
// Schedule resolution functions for the multiply driven Verilog nets that have strength
|
||||
// Schedule transaction functions for the singly driven Verilog nets that have strength
|
||||
|
||||
}
|
||||
#include "iki_bridge.h"
|
||||
void relocate(char *);
|
||||
|
||||
void sensitize(char *);
|
||||
|
||||
void simulate(char *);
|
||||
|
||||
extern SYSTEMCLIB_IMP_DLLSPEC void local_register_implicit_channel(int, char*);
|
||||
extern void implicit_HDL_SCinstatiate();
|
||||
|
||||
extern int xsim_argc_copy ;
|
||||
extern char** xsim_argv_copy ;
|
||||
|
||||
int main(int argc, char **argv)
|
||||
{
|
||||
iki_heap_initialize("ms", "isimmm", 0, 2147483648) ;
|
||||
iki_set_sv_type_file_path_name("xsim.dir/tb_exp1_behav/xsim.svtype");
|
||||
iki_set_crvs_dump_file_path_name("xsim.dir/tb_exp1_behav/xsim.crvsdump");
|
||||
void* design_handle = iki_create_design("xsim.dir/tb_exp1_behav/xsim.mem", (void *)relocate, (void *)sensitize, (void *)simulate, 0, isimBridge_getWdbWriter(), 0, argc, argv);
|
||||
iki_set_rc_trial_count(100);
|
||||
(void) design_handle;
|
||||
return iki_simulate_design();
|
||||
}
|
||||
Binary file not shown.
BIN
Experiments/Exp1/Exp1.sim/sim_1/behav/xsim/xvlog.pb
Normal file
BIN
Experiments/Exp1/Exp1.sim/sim_1/behav/xsim/xvlog.pb
Normal file
Binary file not shown.
48
Experiments/Exp1/Exp1.srcs/sim_1/new/tb_exp1.v
Normal file
48
Experiments/Exp1/Exp1.srcs/sim_1/new/tb_exp1.v
Normal file
@@ -0,0 +1,48 @@
|
||||
`timescale 1ns / 1ps
|
||||
module tb_exp1;
|
||||
|
||||
reg [31:0] alu_a, alu_b;
|
||||
reg [2:0] AluCtrl;
|
||||
wire [31:0] AddResult;
|
||||
wire Zero;
|
||||
|
||||
reg [31:0] Ext_DataIn;
|
||||
reg [1:0] ExtOp;
|
||||
wire [31:0] Ext_DataOut;
|
||||
|
||||
ALU u_ALU (
|
||||
.a(alu_a), .b(alu_b), .AluCtrl(AluCtrl),
|
||||
.AddResult(AddResult), .Zero(Zero)
|
||||
);
|
||||
|
||||
Ext u_Ext (
|
||||
.DataIn(Ext_DataIn), .ExtOp(ExtOp), .DataOut(Ext_DataOut)
|
||||
);
|
||||
|
||||
initial begin
|
||||
$display("----------------- 开始实验一仿真 -----------------");
|
||||
$display("=========== 测试 ALU 模块 ===========");
|
||||
alu_a = 32'd10; alu_b = 32'd5; AluCtrl = 3'b000; #10;
|
||||
$display("ALU ADD: %d + %d = %d", alu_a, alu_b, AddResult);
|
||||
alu_a = 32'd10; alu_b = 32'd10; AluCtrl = 3'b001; #10;
|
||||
$display("ALU SUB: %d - %d = %d, Zero = %b", alu_a, alu_b, AddResult, Zero);
|
||||
alu_a = 32'hFFFFFFFF;
|
||||
alu_b = 32'd1;
|
||||
AluCtrl = 3'b101; #10;
|
||||
$display("ALU SLT: $signed(%h) < $signed(%h) is %d", alu_a, alu_b, AddResult);
|
||||
AluCtrl = 3'b110; #10;
|
||||
$display("ALU SLTU: %h < %h is %d", alu_a, alu_b, AddResult);
|
||||
|
||||
$display("\n=========== 测试 Ext 模块 ===========");
|
||||
Ext_DataIn = 32'h02A4C503;
|
||||
ExtOp = 2'b00; #10;
|
||||
$display("ExtOp=00, DataIn=%h, DataOut=%h (符号扩展[21:10])", Ext_DataIn, Ext_DataOut);
|
||||
ExtOp = 2'b01; #10;
|
||||
$display("ExtOp=01, DataIn=%h, DataOut=%h (符号扩展[25:10] << 2)", Ext_DataIn, Ext_DataOut);
|
||||
ExtOp = 2'b10; #10;
|
||||
$display("ExtOp=10, DataIn=%h, DataOut=%h ([24:5] << 12)", Ext_DataIn, Ext_DataOut);
|
||||
|
||||
$display("\n----------------- 实验一仿真结束 -----------------");
|
||||
$stop;
|
||||
end
|
||||
endmodule
|
||||
153
Experiments/Exp1/Exp1.xpr
Normal file
153
Experiments/Exp1/Exp1.xpr
Normal file
@@ -0,0 +1,153 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<!-- Product Version: Vivado v2018.1 (64-bit) -->
|
||||
<!-- -->
|
||||
<!-- Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. -->
|
||||
|
||||
<Project Version="7" Minor="36" Path="D:/Schoolwork/ComputerComposition/Experiments/Exp1/Exp1.xpr">
|
||||
<DefaultLaunch Dir="$PRUNDIR"/>
|
||||
<Configuration>
|
||||
<Option Name="Id" Val="37682ab63326475c8c4702befd41712b"/>
|
||||
<Option Name="Part" Val="xc7a35tcsg324-1"/>
|
||||
<Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
|
||||
<Option Name="CompiledLibDirXSim" Val=""/>
|
||||
<Option Name="CompiledLibDirModelSim" Val="$PCACHEDIR/compile_simlib/modelsim"/>
|
||||
<Option Name="CompiledLibDirQuesta" Val="$PCACHEDIR/compile_simlib/questa"/>
|
||||
<Option Name="CompiledLibDirIES" Val="$PCACHEDIR/compile_simlib/ies"/>
|
||||
<Option Name="CompiledLibDirXcelium" Val="$PCACHEDIR/compile_simlib/xcelium"/>
|
||||
<Option Name="CompiledLibDirVCS" Val="$PCACHEDIR/compile_simlib/vcs"/>
|
||||
<Option Name="CompiledLibDirRiviera" Val="$PCACHEDIR/compile_simlib/riviera"/>
|
||||
<Option Name="CompiledLibDirActivehdl" Val="$PCACHEDIR/compile_simlib/activehdl"/>
|
||||
<Option Name="BoardPart" Val=""/>
|
||||
<Option Name="ActiveSimSet" Val="sim_1"/>
|
||||
<Option Name="DefaultLib" Val="xil_defaultlib"/>
|
||||
<Option Name="ProjectType" Val="Default"/>
|
||||
<Option Name="IPOutputRepo" Val="$PCACHEDIR/ip"/>
|
||||
<Option Name="IPCachePermission" Val="read"/>
|
||||
<Option Name="IPCachePermission" Val="write"/>
|
||||
<Option Name="EnableCoreContainer" Val="FALSE"/>
|
||||
<Option Name="CreateRefXciForCoreContainers" Val="FALSE"/>
|
||||
<Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
|
||||
<Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
|
||||
<Option Name="EnableBDX" Val="FALSE"/>
|
||||
<Option Name="DSAVendor" Val="xilinx"/>
|
||||
<Option Name="DSANumComputeUnits" Val="60"/>
|
||||
<Option Name="WTXSimLaunchSim" Val="2"/>
|
||||
<Option Name="WTModelSimLaunchSim" Val="0"/>
|
||||
<Option Name="WTQuestaLaunchSim" Val="0"/>
|
||||
<Option Name="WTIesLaunchSim" Val="0"/>
|
||||
<Option Name="WTVcsLaunchSim" Val="0"/>
|
||||
<Option Name="WTRivieraLaunchSim" Val="0"/>
|
||||
<Option Name="WTActivehdlLaunchSim" Val="0"/>
|
||||
<Option Name="WTXSimExportSim" Val="0"/>
|
||||
<Option Name="WTModelSimExportSim" Val="0"/>
|
||||
<Option Name="WTQuestaExportSim" Val="0"/>
|
||||
<Option Name="WTIesExportSim" Val="0"/>
|
||||
<Option Name="WTVcsExportSim" Val="0"/>
|
||||
<Option Name="WTRivieraExportSim" Val="0"/>
|
||||
<Option Name="WTActivehdlExportSim" Val="0"/>
|
||||
<Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
|
||||
<Option Name="XSimRadix" Val="hex"/>
|
||||
<Option Name="XSimTimeUnit" Val="ns"/>
|
||||
<Option Name="XSimArrayDisplayLimit" Val="1024"/>
|
||||
<Option Name="XSimTraceLimit" Val="65536"/>
|
||||
<Option Name="SimTypes" Val="rtl"/>
|
||||
</Configuration>
|
||||
<FileSets Version="1" Minor="31">
|
||||
<FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1">
|
||||
<Filter Type="Srcs"/>
|
||||
<File Path="$PPRDIR/../Shared/ALU.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../Shared/Ext.v">
|
||||
<FileInfo>
|
||||
<Attr Name="AutoDisabled" Val="1"/>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<Config>
|
||||
<Option Name="DesignMode" Val="RTL"/>
|
||||
<Option Name="TopModule" Val="ALU"/>
|
||||
<Option Name="TopAutoSet" Val="TRUE"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1">
|
||||
<Filter Type="Constrs"/>
|
||||
<Config>
|
||||
<Option Name="ConstrsType" Val="XDC"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1">
|
||||
<File Path="$PSRCDIR/sim_1/new/tb_exp1.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<Config>
|
||||
<Option Name="DesignMode" Val="RTL"/>
|
||||
<Option Name="TopModule" Val="tb_exp1"/>
|
||||
<Option Name="TopLib" Val="xil_defaultlib"/>
|
||||
<Option Name="TopAutoSet" Val="TRUE"/>
|
||||
<Option Name="TransportPathDelay" Val="0"/>
|
||||
<Option Name="TransportIntDelay" Val="0"/>
|
||||
<Option Name="SrcSet" Val="sources_1"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
</FileSets>
|
||||
<Simulators>
|
||||
<Simulator Name="XSim">
|
||||
<Option Name="Description" Val="Vivado Simulator"/>
|
||||
<Option Name="CompiledLib" Val="0"/>
|
||||
</Simulator>
|
||||
<Simulator Name="ModelSim">
|
||||
<Option Name="Description" Val="ModelSim Simulator"/>
|
||||
</Simulator>
|
||||
<Simulator Name="Questa">
|
||||
<Option Name="Description" Val="Questa Advanced Simulator"/>
|
||||
</Simulator>
|
||||
<Simulator Name="Riviera">
|
||||
<Option Name="Description" Val="Riviera-PRO Simulator"/>
|
||||
</Simulator>
|
||||
<Simulator Name="ActiveHDL">
|
||||
<Option Name="Description" Val="Active-HDL Simulator"/>
|
||||
</Simulator>
|
||||
</Simulators>
|
||||
<Runs Version="1" Minor="10">
|
||||
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a35tcsg324-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2018">
|
||||
<Desc>Vivado Synthesis Defaults</Desc>
|
||||
</StratHandle>
|
||||
<Step Id="synth_design"/>
|
||||
</Strategy>
|
||||
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2018"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
</Run>
|
||||
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcsg324-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2018">
|
||||
<Desc>Default settings for Implementation.</Desc>
|
||||
</StratHandle>
|
||||
<Step Id="init_design"/>
|
||||
<Step Id="opt_design"/>
|
||||
<Step Id="power_opt_design"/>
|
||||
<Step Id="place_design"/>
|
||||
<Step Id="post_place_power_opt_design"/>
|
||||
<Step Id="phys_opt_design"/>
|
||||
<Step Id="route_design"/>
|
||||
<Step Id="post_route_phys_opt_design"/>
|
||||
<Step Id="write_bitstream"/>
|
||||
</Strategy>
|
||||
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2018"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
</Run>
|
||||
</Runs>
|
||||
<Board/>
|
||||
</Project>
|
||||
1
Experiments/Exp2/Exp2.ip_user_files/README.txt
Normal file
1
Experiments/Exp2/Exp2.ip_user_files/README.txt
Normal file
@@ -0,0 +1 @@
|
||||
The files in this directory structure are automatically generated and managed by Vivado. Editing these files is not recommended.
|
||||
71
Experiments/Exp2/Exp2.sim/sim_1/behav/xsim/glbl.v
Normal file
71
Experiments/Exp2/Exp2.sim/sim_1/behav/xsim/glbl.v
Normal file
@@ -0,0 +1,71 @@
|
||||
// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
|
||||
`ifndef GLBL
|
||||
`define GLBL
|
||||
`timescale 1 ps / 1 ps
|
||||
|
||||
module glbl ();
|
||||
|
||||
parameter ROC_WIDTH = 100000;
|
||||
parameter TOC_WIDTH = 0;
|
||||
|
||||
//-------- STARTUP Globals --------------
|
||||
wire GSR;
|
||||
wire GTS;
|
||||
wire GWE;
|
||||
wire PRLD;
|
||||
tri1 p_up_tmp;
|
||||
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
|
||||
|
||||
wire PROGB_GLBL;
|
||||
wire CCLKO_GLBL;
|
||||
wire FCSBO_GLBL;
|
||||
wire [3:0] DO_GLBL;
|
||||
wire [3:0] DI_GLBL;
|
||||
|
||||
reg GSR_int;
|
||||
reg GTS_int;
|
||||
reg PRLD_int;
|
||||
|
||||
//-------- JTAG Globals --------------
|
||||
wire JTAG_TDO_GLBL;
|
||||
wire JTAG_TCK_GLBL;
|
||||
wire JTAG_TDI_GLBL;
|
||||
wire JTAG_TMS_GLBL;
|
||||
wire JTAG_TRST_GLBL;
|
||||
|
||||
reg JTAG_CAPTURE_GLBL;
|
||||
reg JTAG_RESET_GLBL;
|
||||
reg JTAG_SHIFT_GLBL;
|
||||
reg JTAG_UPDATE_GLBL;
|
||||
reg JTAG_RUNTEST_GLBL;
|
||||
|
||||
reg JTAG_SEL1_GLBL = 0;
|
||||
reg JTAG_SEL2_GLBL = 0 ;
|
||||
reg JTAG_SEL3_GLBL = 0;
|
||||
reg JTAG_SEL4_GLBL = 0;
|
||||
|
||||
reg JTAG_USER_TDO1_GLBL = 1'bz;
|
||||
reg JTAG_USER_TDO2_GLBL = 1'bz;
|
||||
reg JTAG_USER_TDO3_GLBL = 1'bz;
|
||||
reg JTAG_USER_TDO4_GLBL = 1'bz;
|
||||
|
||||
assign (strong1, weak0) GSR = GSR_int;
|
||||
assign (strong1, weak0) GTS = GTS_int;
|
||||
assign (weak1, weak0) PRLD = PRLD_int;
|
||||
|
||||
initial begin
|
||||
GSR_int = 1'b1;
|
||||
PRLD_int = 1'b1;
|
||||
#(ROC_WIDTH)
|
||||
GSR_int = 1'b0;
|
||||
PRLD_int = 1'b0;
|
||||
end
|
||||
|
||||
initial begin
|
||||
GTS_int = 1'b1;
|
||||
#(TOC_WIDTH)
|
||||
GTS_int = 1'b0;
|
||||
end
|
||||
|
||||
endmodule
|
||||
`endif
|
||||
11
Experiments/Exp2/Exp2.sim/sim_1/behav/xsim/tb_exp2.tcl
Normal file
11
Experiments/Exp2/Exp2.sim/sim_1/behav/xsim/tb_exp2.tcl
Normal file
@@ -0,0 +1,11 @@
|
||||
set curr_wave [current_wave_config]
|
||||
if { [string length $curr_wave] == 0 } {
|
||||
if { [llength [get_objects]] > 0} {
|
||||
add_wave /
|
||||
set_property needs_save false [current_wave_config]
|
||||
} else {
|
||||
send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
|
||||
}
|
||||
}
|
||||
|
||||
run 1000ns
|
||||
13
Experiments/Exp2/Exp2.sim/sim_1/behav/xsim/tb_exp2_vlog.prj
Normal file
13
Experiments/Exp2/Exp2.sim/sim_1/behav/xsim/tb_exp2_vlog.prj
Normal file
@@ -0,0 +1,13 @@
|
||||
# compile verilog/system verilog design source files
|
||||
verilog xil_defaultlib \
|
||||
"../../../../../Shared/DR.v" \
|
||||
"../../../../../Shared/DataRAM.v" \
|
||||
"../../../../../Shared/PC.v" \
|
||||
"../../../../../Shared/Registers.v" \
|
||||
"../../../../Exp2.srcs/sim_1/new/tb_exp2.v" \
|
||||
|
||||
# compile glbl module
|
||||
verilog xil_defaultlib "glbl.v"
|
||||
|
||||
# Do not sort compile order
|
||||
nosort
|
||||
12
Experiments/Exp2/Exp2.sim/sim_1/behav/xsim/webtalk.jou
Normal file
12
Experiments/Exp2/Exp2.sim/sim_1/behav/xsim/webtalk.jou
Normal file
@@ -0,0 +1,12 @@
|
||||
#-----------------------------------------------------------
|
||||
# Webtalk v2018.1 (64-bit)
|
||||
# SW Build 2188600 on Wed Apr 4 18:40:38 MDT 2018
|
||||
# IP Build 2185939 on Wed Apr 4 20:55:05 MDT 2018
|
||||
# Start of session at: Thu Jul 3 04:25:52 2025
|
||||
# Process ID: 1908
|
||||
# Current directory: D:/Schoolwork/ComputerComposition/Experiments/Exp2/Exp2.sim/sim_1/behav/xsim
|
||||
# Command line: wbtcv.exe -mode batch -source D:/Schoolwork/ComputerComposition/Experiments/Exp2/Exp2.sim/sim_1/behav/xsim/xsim.dir/tb_exp2_behav/webtalk/xsim_webtalk.tcl -notrace
|
||||
# Log file: D:/Schoolwork/ComputerComposition/Experiments/Exp2/Exp2.sim/sim_1/behav/xsim/webtalk.log
|
||||
# Journal file: D:/Schoolwork/ComputerComposition/Experiments/Exp2/Exp2.sim/sim_1/behav/xsim\webtalk.jou
|
||||
#-----------------------------------------------------------
|
||||
source D:/Schoolwork/ComputerComposition/Experiments/Exp2/Exp2.sim/sim_1/behav/xsim/xsim.dir/tb_exp2_behav/webtalk/xsim_webtalk.tcl -notrace
|
||||
@@ -0,0 +1,12 @@
|
||||
#-----------------------------------------------------------
|
||||
# Webtalk v2018.1 (64-bit)
|
||||
# SW Build 2188600 on Wed Apr 4 18:40:38 MDT 2018
|
||||
# IP Build 2185939 on Wed Apr 4 20:55:05 MDT 2018
|
||||
# Start of session at: Thu Jul 3 04:22:12 2025
|
||||
# Process ID: 10888
|
||||
# Current directory: D:/Schoolwork/ComputerComposition/Experiments/Exp2/Exp2.sim/sim_1/behav/xsim
|
||||
# Command line: wbtcv.exe -mode batch -source D:/Schoolwork/ComputerComposition/Experiments/Exp2/Exp2.sim/sim_1/behav/xsim/xsim.dir/tb_exp2_behav/webtalk/xsim_webtalk.tcl -notrace
|
||||
# Log file: D:/Schoolwork/ComputerComposition/Experiments/Exp2/Exp2.sim/sim_1/behav/xsim/webtalk.log
|
||||
# Journal file: D:/Schoolwork/ComputerComposition/Experiments/Exp2/Exp2.sim/sim_1/behav/xsim\webtalk.jou
|
||||
#-----------------------------------------------------------
|
||||
source D:/Schoolwork/ComputerComposition/Experiments/Exp2/Exp2.sim/sim_1/behav/xsim/xsim.dir/tb_exp2_behav/webtalk/xsim_webtalk.tcl -notrace
|
||||
@@ -0,0 +1,12 @@
|
||||
#-----------------------------------------------------------
|
||||
# Webtalk v2018.1 (64-bit)
|
||||
# SW Build 2188600 on Wed Apr 4 18:40:38 MDT 2018
|
||||
# IP Build 2185939 on Wed Apr 4 20:55:05 MDT 2018
|
||||
# Start of session at: Wed Jul 2 00:25:00 2025
|
||||
# Process ID: 28652
|
||||
# Current directory: D:/Schoolwork/ComputerComposition/Experiments/Exp2/Exp2.sim/sim_1/behav/xsim
|
||||
# Command line: wbtcv.exe -mode batch -source D:/Schoolwork/ComputerComposition/Experiments/Exp2/Exp2.sim/sim_1/behav/xsim/xsim.dir/tb_exp2_behav/webtalk/xsim_webtalk.tcl -notrace
|
||||
# Log file: D:/Schoolwork/ComputerComposition/Experiments/Exp2/Exp2.sim/sim_1/behav/xsim/webtalk.log
|
||||
# Journal file: D:/Schoolwork/ComputerComposition/Experiments/Exp2/Exp2.sim/sim_1/behav/xsim\webtalk.jou
|
||||
#-----------------------------------------------------------
|
||||
source D:/Schoolwork/ComputerComposition/Experiments/Exp2/Exp2.sim/sim_1/behav/xsim/xsim.dir/tb_exp2_behav/webtalk/xsim_webtalk.tcl -notrace
|
||||
BIN
Experiments/Exp2/Exp2.sim/sim_1/behav/xsim/xelab.pb
Normal file
BIN
Experiments/Exp2/Exp2.sim/sim_1/behav/xsim/xelab.pb
Normal file
Binary file not shown.
@@ -0,0 +1 @@
|
||||
-wto "164e4d51dc2148f893b981e9cc10cb15" --incr --debug "typical" --relax --mt "2" -L "xil_defaultlib" -L "unisims_ver" -L "unimacro_ver" -L "secureip" --snapshot "tb_exp2_behav" "xil_defaultlib.tb_exp2" "xil_defaultlib.glbl" -log "elaborate.log"
|
||||
@@ -0,0 +1 @@
|
||||
Breakpoint File Version 1.0
|
||||
@@ -0,0 +1,133 @@
|
||||
/**********************************************************************/
|
||||
/* ____ ____ */
|
||||
/* / /\/ / */
|
||||
/* /___/ \ / */
|
||||
/* \ \ \/ */
|
||||
/* \ \ Copyright (c) 2003-2013 Xilinx, Inc. */
|
||||
/* / / All Right Reserved. */
|
||||
/* /---/ /\ */
|
||||
/* \ \ / \ */
|
||||
/* \___\/\___\ */
|
||||
/**********************************************************************/
|
||||
|
||||
|
||||
#include "iki.h"
|
||||
#include <string.h>
|
||||
#include <math.h>
|
||||
#ifdef __GNUC__
|
||||
#include <stdlib.h>
|
||||
#else
|
||||
#include <malloc.h>
|
||||
#define alloca _alloca
|
||||
#endif
|
||||
/**********************************************************************/
|
||||
/* ____ ____ */
|
||||
/* / /\/ / */
|
||||
/* /___/ \ / */
|
||||
/* \ \ \/ */
|
||||
/* \ \ Copyright (c) 2003-2013 Xilinx, Inc. */
|
||||
/* / / All Right Reserved. */
|
||||
/* /---/ /\ */
|
||||
/* \ \ / \ */
|
||||
/* \___\/\___\ */
|
||||
/**********************************************************************/
|
||||
|
||||
|
||||
#include "iki.h"
|
||||
#include <string.h>
|
||||
#include <math.h>
|
||||
#ifdef __GNUC__
|
||||
#include <stdlib.h>
|
||||
#else
|
||||
#include <malloc.h>
|
||||
#define alloca _alloca
|
||||
#endif
|
||||
typedef void (*funcp)(char *, char *);
|
||||
extern int main(int, char**);
|
||||
extern void execute_11(char*, char *);
|
||||
extern void execute_12(char*, char *);
|
||||
extern void execute_21(char*, char *);
|
||||
extern void execute_22(char*, char *);
|
||||
extern void execute_23(char*, char *);
|
||||
extern void execute_24(char*, char *);
|
||||
extern void execute_25(char*, char *);
|
||||
extern void execute_26(char*, char *);
|
||||
extern void execute_27(char*, char *);
|
||||
extern void execute_28(char*, char *);
|
||||
extern void execute_29(char*, char *);
|
||||
extern void execute_30(char*, char *);
|
||||
extern void execute_31(char*, char *);
|
||||
extern void execute_32(char*, char *);
|
||||
extern void execute_33(char*, char *);
|
||||
extern void execute_34(char*, char *);
|
||||
extern void execute_35(char*, char *);
|
||||
extern void execute_36(char*, char *);
|
||||
extern void execute_37(char*, char *);
|
||||
extern void execute_38(char*, char *);
|
||||
extern void execute_39(char*, char *);
|
||||
extern void execute_3(char*, char *);
|
||||
extern void execute_5(char*, char *);
|
||||
extern void execute_7(char*, char *);
|
||||
extern void execute_8(char*, char *);
|
||||
extern void execute_17(char*, char *);
|
||||
extern void execute_18(char*, char *);
|
||||
extern void execute_10(char*, char *);
|
||||
extern void execute_19(char*, char *);
|
||||
extern void execute_20(char*, char *);
|
||||
extern void execute_14(char*, char *);
|
||||
extern void execute_15(char*, char *);
|
||||
extern void execute_16(char*, char *);
|
||||
extern void execute_40(char*, char *);
|
||||
extern void execute_41(char*, char *);
|
||||
extern void execute_42(char*, char *);
|
||||
extern void execute_43(char*, char *);
|
||||
extern void execute_44(char*, char *);
|
||||
extern void vlog_transfunc_eventcallback(char*, char*, unsigned, unsigned, unsigned, char *);
|
||||
funcp funcTab[39] = {(funcp)execute_11, (funcp)execute_12, (funcp)execute_21, (funcp)execute_22, (funcp)execute_23, (funcp)execute_24, (funcp)execute_25, (funcp)execute_26, (funcp)execute_27, (funcp)execute_28, (funcp)execute_29, (funcp)execute_30, (funcp)execute_31, (funcp)execute_32, (funcp)execute_33, (funcp)execute_34, (funcp)execute_35, (funcp)execute_36, (funcp)execute_37, (funcp)execute_38, (funcp)execute_39, (funcp)execute_3, (funcp)execute_5, (funcp)execute_7, (funcp)execute_8, (funcp)execute_17, (funcp)execute_18, (funcp)execute_10, (funcp)execute_19, (funcp)execute_20, (funcp)execute_14, (funcp)execute_15, (funcp)execute_16, (funcp)execute_40, (funcp)execute_41, (funcp)execute_42, (funcp)execute_43, (funcp)execute_44, (funcp)vlog_transfunc_eventcallback};
|
||||
const int NumRelocateId= 39;
|
||||
|
||||
void relocate(char *dp)
|
||||
{
|
||||
iki_relocate(dp, "xsim.dir/tb_exp2_behav/xsim.reloc", (void **)funcTab, 39);
|
||||
|
||||
/*Populate the transaction function pointer field in the whole net structure */
|
||||
}
|
||||
|
||||
void sensitize(char *dp)
|
||||
{
|
||||
iki_sensitize(dp, "xsim.dir/tb_exp2_behav/xsim.reloc");
|
||||
}
|
||||
|
||||
void simulate(char *dp)
|
||||
{
|
||||
iki_schedule_processes_at_time_zero(dp, "xsim.dir/tb_exp2_behav/xsim.reloc");
|
||||
// Initialize Verilog nets in mixed simulation, for the cases when the value at time 0 should be propagated from the mixed language Vhdl net
|
||||
iki_execute_processes();
|
||||
|
||||
// Schedule resolution functions for the multiply driven Verilog nets that have strength
|
||||
// Schedule transaction functions for the singly driven Verilog nets that have strength
|
||||
|
||||
}
|
||||
#include "iki_bridge.h"
|
||||
void relocate(char *);
|
||||
|
||||
void sensitize(char *);
|
||||
|
||||
void simulate(char *);
|
||||
|
||||
extern SYSTEMCLIB_IMP_DLLSPEC void local_register_implicit_channel(int, char*);
|
||||
extern void implicit_HDL_SCinstatiate();
|
||||
|
||||
extern int xsim_argc_copy ;
|
||||
extern char** xsim_argv_copy ;
|
||||
|
||||
int main(int argc, char **argv)
|
||||
{
|
||||
iki_heap_initialize("ms", "isimmm", 0, 2147483648) ;
|
||||
iki_set_sv_type_file_path_name("xsim.dir/tb_exp2_behav/xsim.svtype");
|
||||
iki_set_crvs_dump_file_path_name("xsim.dir/tb_exp2_behav/xsim.crvsdump");
|
||||
void* design_handle = iki_create_design("xsim.dir/tb_exp2_behav/xsim.mem", (void *)relocate, (void *)sensitize, (void *)simulate, 0, isimBridge_getWdbWriter(), 0, argc, argv);
|
||||
iki_set_rc_trial_count(100);
|
||||
(void) design_handle;
|
||||
return iki_simulate_design();
|
||||
}
|
||||
Binary file not shown.
BIN
Experiments/Exp2/Exp2.sim/sim_1/behav/xsim/xvlog.pb
Normal file
BIN
Experiments/Exp2/Exp2.sim/sim_1/behav/xsim/xvlog.pb
Normal file
Binary file not shown.
67
Experiments/Exp2/Exp2.srcs/sim_1/new/tb_exp2.v
Normal file
67
Experiments/Exp2/Exp2.srcs/sim_1/new/tb_exp2.v
Normal file
@@ -0,0 +1,67 @@
|
||||
module tb_exp2;
|
||||
reg clk;
|
||||
|
||||
reg DR_WE;
|
||||
reg [31:0] DR_DataIn;
|
||||
wire [31:0] DR_DataOut;
|
||||
|
||||
reg PC_rst, PC_pc_inc;
|
||||
reg [31:0] PC_offset;
|
||||
wire [31:0] PC_PCdata;
|
||||
|
||||
reg RegWr;
|
||||
reg [4:0] Ra, Rb, Rw;
|
||||
reg [31:0] busW;
|
||||
wire [31:0] busA, busB;
|
||||
|
||||
reg MemWrEn;
|
||||
reg [31:0] addr, data_in;
|
||||
wire [31:0] data_out;
|
||||
|
||||
DR u_DR (.clk(clk), .WE(DR_WE), .DataIn(DR_DataIn), .DataOut(DR_DataOut));
|
||||
PC u_PC (.clk(clk), .rst(PC_rst), .pc_inc(PC_pc_inc), .offset(PC_offset), .PCdata(PC_PCdata));
|
||||
Registers u_Registers (.clk(clk), .RegWr(RegWr), .Ra(Ra), .Rb(Rb), .Rw(Rw), .busW(busW), .busA(busA), .busB(busB));
|
||||
DataRAM u_DataRAM (.clk(clk), .MemWrEn(MemWrEn), .addr(addr), .data_in(data_in), .data_out(data_out));
|
||||
|
||||
initial begin
|
||||
clk = 0;
|
||||
forever #5 clk = ~clk;
|
||||
end
|
||||
|
||||
initial begin
|
||||
$display("----------------- 开始实验二仿真 -----------------");
|
||||
|
||||
$display("\n=========== 1. 测试 DR 模块 ===========");
|
||||
DR_DataIn = 32'h12345678; DR_WE = 1; #10;
|
||||
$display("T=%0t: 写入 DR, DataIn=%h. 期望 DataOut=%h. 实际 DataOut=%h", $time, DR_DataIn, DR_DataIn, DR_DataOut);
|
||||
DR_WE = 0; DR_DataIn = 32'hFFFFFFFF; #10;
|
||||
$display("T=%0t: 禁用写入, DataIn=%h. 期望 DataOut保持不变. 实际 DataOut=%h", $time, DR_DataIn, DR_DataOut);
|
||||
|
||||
$display("\n=========== 2. 测试 PC 模块 ===========");
|
||||
PC_rst = 1; #10;
|
||||
$display("T=%0t: 异步复位. 期望 PCdata=0. 实际 PCdata=%d", $time, PC_PCdata);
|
||||
PC_rst = 0; PC_pc_inc = 1; #10;
|
||||
$display("T=%0t: PC自增. 期望 PCdata=4. 实际 PCdata=%d", $time, PC_PCdata);
|
||||
PC_pc_inc = 1; #10;
|
||||
$display("T=%0t: PC再次自增. 期望 PCdata=8. 实际 PCdata=%d", $time, PC_PCdata);
|
||||
PC_pc_inc = 0; PC_offset = 32'd100; #10;
|
||||
$display("T=%0t: PC加偏移量100. 期望 PCdata=108. 实际 PCdata=%d", $time, PC_PCdata);
|
||||
|
||||
$display("\n=========== 3. 测试 Registers 模块 ===========");
|
||||
RegWr = 1; Rw = 5; busW = 32'hAAAAAAAA; #10;
|
||||
$display("T=%0t: 写入 r5 数据 0xAAAAAAAA", $time);
|
||||
Rw = 10; busW = 32'hBBBBBBBB; #10;
|
||||
$display("T=%0t: 写入 r10 数据 0xBBBBBBBB", $time);
|
||||
RegWr = 0; Ra = 5; Rb = 10; #10;
|
||||
$display("T=%0t: 读取 r5, r10. busA=%h, busB=%h", $time, busA, busB);
|
||||
|
||||
$display("\n=========== 4. 测试 DataRAM 模块 ===========");
|
||||
MemWrEn = 1; addr = 32'd100; data_in = 32'hCAFECAFE; #10;
|
||||
$display("T=%0t: 写入内存地址 100, 数据 0xCAFECAFE", $time);
|
||||
MemWrEn = 0; addr = 32'd100; #10;
|
||||
$display("T=%0t: 读取内存地址 100. data_out=%h", $time, data_out);
|
||||
|
||||
$display("\n----------------- 实验二仿真结束 -----------------");
|
||||
$stop;
|
||||
end
|
||||
endmodule
|
||||
185
Experiments/Exp2/Exp2.xpr
Normal file
185
Experiments/Exp2/Exp2.xpr
Normal file
@@ -0,0 +1,185 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<!-- Product Version: Vivado v2018.1 (64-bit) -->
|
||||
<!-- -->
|
||||
<!-- Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. -->
|
||||
|
||||
<Project Version="7" Minor="36" Path="D:/Schoolwork/ComputerComposition/Experiments/Exp2/Exp2.xpr">
|
||||
<DefaultLaunch Dir="$PRUNDIR"/>
|
||||
<Configuration>
|
||||
<Option Name="Id" Val="164e4d51dc2148f893b981e9cc10cb15"/>
|
||||
<Option Name="Part" Val="xc7a35tcsg324-1"/>
|
||||
<Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
|
||||
<Option Name="CompiledLibDirXSim" Val=""/>
|
||||
<Option Name="CompiledLibDirModelSim" Val="$PCACHEDIR/compile_simlib/modelsim"/>
|
||||
<Option Name="CompiledLibDirQuesta" Val="$PCACHEDIR/compile_simlib/questa"/>
|
||||
<Option Name="CompiledLibDirIES" Val="$PCACHEDIR/compile_simlib/ies"/>
|
||||
<Option Name="CompiledLibDirXcelium" Val="$PCACHEDIR/compile_simlib/xcelium"/>
|
||||
<Option Name="CompiledLibDirVCS" Val="$PCACHEDIR/compile_simlib/vcs"/>
|
||||
<Option Name="CompiledLibDirRiviera" Val="$PCACHEDIR/compile_simlib/riviera"/>
|
||||
<Option Name="CompiledLibDirActivehdl" Val="$PCACHEDIR/compile_simlib/activehdl"/>
|
||||
<Option Name="BoardPart" Val=""/>
|
||||
<Option Name="ActiveSimSet" Val="sim_1"/>
|
||||
<Option Name="DefaultLib" Val="xil_defaultlib"/>
|
||||
<Option Name="ProjectType" Val="Default"/>
|
||||
<Option Name="IPOutputRepo" Val="$PCACHEDIR/ip"/>
|
||||
<Option Name="IPCachePermission" Val="read"/>
|
||||
<Option Name="IPCachePermission" Val="write"/>
|
||||
<Option Name="EnableCoreContainer" Val="FALSE"/>
|
||||
<Option Name="CreateRefXciForCoreContainers" Val="FALSE"/>
|
||||
<Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
|
||||
<Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
|
||||
<Option Name="EnableBDX" Val="FALSE"/>
|
||||
<Option Name="DSAVendor" Val="xilinx"/>
|
||||
<Option Name="DSANumComputeUnits" Val="60"/>
|
||||
<Option Name="WTXSimLaunchSim" Val="3"/>
|
||||
<Option Name="WTModelSimLaunchSim" Val="0"/>
|
||||
<Option Name="WTQuestaLaunchSim" Val="0"/>
|
||||
<Option Name="WTIesLaunchSim" Val="0"/>
|
||||
<Option Name="WTVcsLaunchSim" Val="0"/>
|
||||
<Option Name="WTRivieraLaunchSim" Val="0"/>
|
||||
<Option Name="WTActivehdlLaunchSim" Val="0"/>
|
||||
<Option Name="WTXSimExportSim" Val="0"/>
|
||||
<Option Name="WTModelSimExportSim" Val="0"/>
|
||||
<Option Name="WTQuestaExportSim" Val="0"/>
|
||||
<Option Name="WTIesExportSim" Val="0"/>
|
||||
<Option Name="WTVcsExportSim" Val="0"/>
|
||||
<Option Name="WTRivieraExportSim" Val="0"/>
|
||||
<Option Name="WTActivehdlExportSim" Val="0"/>
|
||||
<Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
|
||||
<Option Name="XSimRadix" Val="hex"/>
|
||||
<Option Name="XSimTimeUnit" Val="ns"/>
|
||||
<Option Name="XSimArrayDisplayLimit" Val="1024"/>
|
||||
<Option Name="XSimTraceLimit" Val="65536"/>
|
||||
<Option Name="SimTypes" Val="rtl"/>
|
||||
</Configuration>
|
||||
<FileSets Version="1" Minor="31">
|
||||
<FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1">
|
||||
<Filter Type="Srcs"/>
|
||||
<File Path="$PPRDIR/../Shared/ALU.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../Shared/Ext.v">
|
||||
<FileInfo>
|
||||
<Attr Name="AutoDisabled" Val="1"/>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../Shared/Registers.v">
|
||||
<FileInfo>
|
||||
<Attr Name="AutoDisabled" Val="1"/>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../Shared/DataRAM.v">
|
||||
<FileInfo>
|
||||
<Attr Name="AutoDisabled" Val="1"/>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../Shared/DR.v">
|
||||
<FileInfo>
|
||||
<Attr Name="AutoDisabled" Val="1"/>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../Shared/PC.v">
|
||||
<FileInfo>
|
||||
<Attr Name="AutoDisabled" Val="1"/>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<Config>
|
||||
<Option Name="DesignMode" Val="RTL"/>
|
||||
<Option Name="TopModule" Val="ALU"/>
|
||||
<Option Name="TopAutoSet" Val="TRUE"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1">
|
||||
<Filter Type="Constrs"/>
|
||||
<Config>
|
||||
<Option Name="ConstrsType" Val="XDC"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1">
|
||||
<File Path="$PSRCDIR/sim_1/new/tb_exp2.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<Config>
|
||||
<Option Name="DesignMode" Val="RTL"/>
|
||||
<Option Name="TopModule" Val="tb_exp2"/>
|
||||
<Option Name="TopLib" Val="xil_defaultlib"/>
|
||||
<Option Name="TopAutoSet" Val="TRUE"/>
|
||||
<Option Name="TransportPathDelay" Val="0"/>
|
||||
<Option Name="TransportIntDelay" Val="0"/>
|
||||
<Option Name="SrcSet" Val="sources_1"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
</FileSets>
|
||||
<Simulators>
|
||||
<Simulator Name="XSim">
|
||||
<Option Name="Description" Val="Vivado Simulator"/>
|
||||
<Option Name="CompiledLib" Val="0"/>
|
||||
</Simulator>
|
||||
<Simulator Name="ModelSim">
|
||||
<Option Name="Description" Val="ModelSim Simulator"/>
|
||||
</Simulator>
|
||||
<Simulator Name="Questa">
|
||||
<Option Name="Description" Val="Questa Advanced Simulator"/>
|
||||
</Simulator>
|
||||
<Simulator Name="Riviera">
|
||||
<Option Name="Description" Val="Riviera-PRO Simulator"/>
|
||||
</Simulator>
|
||||
<Simulator Name="ActiveHDL">
|
||||
<Option Name="Description" Val="Active-HDL Simulator"/>
|
||||
</Simulator>
|
||||
</Simulators>
|
||||
<Runs Version="1" Minor="10">
|
||||
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a35tcsg324-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2018">
|
||||
<Desc>Vivado Synthesis Defaults</Desc>
|
||||
</StratHandle>
|
||||
<Step Id="synth_design"/>
|
||||
</Strategy>
|
||||
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2018"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
</Run>
|
||||
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcsg324-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2018">
|
||||
<Desc>Default settings for Implementation.</Desc>
|
||||
</StratHandle>
|
||||
<Step Id="init_design"/>
|
||||
<Step Id="opt_design"/>
|
||||
<Step Id="power_opt_design"/>
|
||||
<Step Id="place_design"/>
|
||||
<Step Id="post_place_power_opt_design"/>
|
||||
<Step Id="phys_opt_design"/>
|
||||
<Step Id="route_design"/>
|
||||
<Step Id="post_route_phys_opt_design"/>
|
||||
<Step Id="write_bitstream"/>
|
||||
</Strategy>
|
||||
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2018"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
</Run>
|
||||
</Runs>
|
||||
<Board/>
|
||||
</Project>
|
||||
1
Experiments/Exp3/Exp3.ip_user_files/README.txt
Normal file
1
Experiments/Exp3/Exp3.ip_user_files/README.txt
Normal file
@@ -0,0 +1 @@
|
||||
The files in this directory structure are automatically generated and managed by Vivado. Editing these files is not recommended.
|
||||
71
Experiments/Exp3/Exp3.sim/sim_1/behav/xsim/glbl.v
Normal file
71
Experiments/Exp3/Exp3.sim/sim_1/behav/xsim/glbl.v
Normal file
@@ -0,0 +1,71 @@
|
||||
// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
|
||||
`ifndef GLBL
|
||||
`define GLBL
|
||||
`timescale 1 ps / 1 ps
|
||||
|
||||
module glbl ();
|
||||
|
||||
parameter ROC_WIDTH = 100000;
|
||||
parameter TOC_WIDTH = 0;
|
||||
|
||||
//-------- STARTUP Globals --------------
|
||||
wire GSR;
|
||||
wire GTS;
|
||||
wire GWE;
|
||||
wire PRLD;
|
||||
tri1 p_up_tmp;
|
||||
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
|
||||
|
||||
wire PROGB_GLBL;
|
||||
wire CCLKO_GLBL;
|
||||
wire FCSBO_GLBL;
|
||||
wire [3:0] DO_GLBL;
|
||||
wire [3:0] DI_GLBL;
|
||||
|
||||
reg GSR_int;
|
||||
reg GTS_int;
|
||||
reg PRLD_int;
|
||||
|
||||
//-------- JTAG Globals --------------
|
||||
wire JTAG_TDO_GLBL;
|
||||
wire JTAG_TCK_GLBL;
|
||||
wire JTAG_TDI_GLBL;
|
||||
wire JTAG_TMS_GLBL;
|
||||
wire JTAG_TRST_GLBL;
|
||||
|
||||
reg JTAG_CAPTURE_GLBL;
|
||||
reg JTAG_RESET_GLBL;
|
||||
reg JTAG_SHIFT_GLBL;
|
||||
reg JTAG_UPDATE_GLBL;
|
||||
reg JTAG_RUNTEST_GLBL;
|
||||
|
||||
reg JTAG_SEL1_GLBL = 0;
|
||||
reg JTAG_SEL2_GLBL = 0 ;
|
||||
reg JTAG_SEL3_GLBL = 0;
|
||||
reg JTAG_SEL4_GLBL = 0;
|
||||
|
||||
reg JTAG_USER_TDO1_GLBL = 1'bz;
|
||||
reg JTAG_USER_TDO2_GLBL = 1'bz;
|
||||
reg JTAG_USER_TDO3_GLBL = 1'bz;
|
||||
reg JTAG_USER_TDO4_GLBL = 1'bz;
|
||||
|
||||
assign (strong1, weak0) GSR = GSR_int;
|
||||
assign (strong1, weak0) GTS = GTS_int;
|
||||
assign (weak1, weak0) PRLD = PRLD_int;
|
||||
|
||||
initial begin
|
||||
GSR_int = 1'b1;
|
||||
PRLD_int = 1'b1;
|
||||
#(ROC_WIDTH)
|
||||
GSR_int = 1'b0;
|
||||
PRLD_int = 1'b0;
|
||||
end
|
||||
|
||||
initial begin
|
||||
GTS_int = 1'b1;
|
||||
#(TOC_WIDTH)
|
||||
GTS_int = 1'b0;
|
||||
end
|
||||
|
||||
endmodule
|
||||
`endif
|
||||
11
Experiments/Exp3/Exp3.sim/sim_1/behav/xsim/tb_exp3.tcl
Normal file
11
Experiments/Exp3/Exp3.sim/sim_1/behav/xsim/tb_exp3.tcl
Normal file
@@ -0,0 +1,11 @@
|
||||
set curr_wave [current_wave_config]
|
||||
if { [string length $curr_wave] == 0 } {
|
||||
if { [llength [get_objects]] > 0} {
|
||||
add_wave /
|
||||
set_property needs_save false [current_wave_config]
|
||||
} else {
|
||||
send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
|
||||
}
|
||||
}
|
||||
|
||||
run 1000ns
|
||||
14
Experiments/Exp3/Exp3.sim/sim_1/behav/xsim/tb_exp3_vlog.prj
Normal file
14
Experiments/Exp3/Exp3.sim/sim_1/behav/xsim/tb_exp3_vlog.prj
Normal file
@@ -0,0 +1,14 @@
|
||||
# compile verilog/system verilog design source files
|
||||
verilog xil_defaultlib \
|
||||
"../../../../../Shared/ALU.v" \
|
||||
"../../../../../Shared/DataRAM.v" \
|
||||
"../../../../../Shared/Datapath.v" \
|
||||
"../../../../../Shared/Ext.v" \
|
||||
"../../../../../Shared/Registers.v" \
|
||||
"../../../../Exp3.srcs/sim_1/new/tb_exp3.v" \
|
||||
|
||||
# compile glbl module
|
||||
verilog xil_defaultlib "glbl.v"
|
||||
|
||||
# Do not sort compile order
|
||||
nosort
|
||||
12
Experiments/Exp3/Exp3.sim/sim_1/behav/xsim/webtalk.jou
Normal file
12
Experiments/Exp3/Exp3.sim/sim_1/behav/xsim/webtalk.jou
Normal file
@@ -0,0 +1,12 @@
|
||||
#-----------------------------------------------------------
|
||||
# Webtalk v2018.1 (64-bit)
|
||||
# SW Build 2188600 on Wed Apr 4 18:40:38 MDT 2018
|
||||
# IP Build 2185939 on Wed Apr 4 20:55:05 MDT 2018
|
||||
# Start of session at: Thu Jul 3 04:44:33 2025
|
||||
# Process ID: 32088
|
||||
# Current directory: D:/Schoolwork/ComputerComposition/Experiments/Exp3/Exp3.sim/sim_1/behav/xsim
|
||||
# Command line: wbtcv.exe -mode batch -source D:/Schoolwork/ComputerComposition/Experiments/Exp3/Exp3.sim/sim_1/behav/xsim/xsim.dir/tb_exp3_behav/webtalk/xsim_webtalk.tcl -notrace
|
||||
# Log file: D:/Schoolwork/ComputerComposition/Experiments/Exp3/Exp3.sim/sim_1/behav/xsim/webtalk.log
|
||||
# Journal file: D:/Schoolwork/ComputerComposition/Experiments/Exp3/Exp3.sim/sim_1/behav/xsim\webtalk.jou
|
||||
#-----------------------------------------------------------
|
||||
source D:/Schoolwork/ComputerComposition/Experiments/Exp3/Exp3.sim/sim_1/behav/xsim/xsim.dir/tb_exp3_behav/webtalk/xsim_webtalk.tcl -notrace
|
||||
@@ -0,0 +1,12 @@
|
||||
#-----------------------------------------------------------
|
||||
# Webtalk v2018.1 (64-bit)
|
||||
# SW Build 2188600 on Wed Apr 4 18:40:38 MDT 2018
|
||||
# IP Build 2185939 on Wed Apr 4 20:55:05 MDT 2018
|
||||
# Start of session at: Thu Jul 3 04:43:32 2025
|
||||
# Process ID: 28872
|
||||
# Current directory: D:/Schoolwork/ComputerComposition/Experiments/Exp3/Exp3.sim/sim_1/behav/xsim
|
||||
# Command line: wbtcv.exe -mode batch -source D:/Schoolwork/ComputerComposition/Experiments/Exp3/Exp3.sim/sim_1/behav/xsim/xsim.dir/tb_exp3_behav/webtalk/xsim_webtalk.tcl -notrace
|
||||
# Log file: D:/Schoolwork/ComputerComposition/Experiments/Exp3/Exp3.sim/sim_1/behav/xsim/webtalk.log
|
||||
# Journal file: D:/Schoolwork/ComputerComposition/Experiments/Exp3/Exp3.sim/sim_1/behav/xsim\webtalk.jou
|
||||
#-----------------------------------------------------------
|
||||
source D:/Schoolwork/ComputerComposition/Experiments/Exp3/Exp3.sim/sim_1/behav/xsim/xsim.dir/tb_exp3_behav/webtalk/xsim_webtalk.tcl -notrace
|
||||
@@ -0,0 +1,12 @@
|
||||
#-----------------------------------------------------------
|
||||
# Webtalk v2018.1 (64-bit)
|
||||
# SW Build 2188600 on Wed Apr 4 18:40:38 MDT 2018
|
||||
# IP Build 2185939 on Wed Apr 4 20:55:05 MDT 2018
|
||||
# Start of session at: Wed Jul 2 00:32:33 2025
|
||||
# Process ID: 9612
|
||||
# Current directory: D:/Schoolwork/ComputerComposition/Experiments/Exp3/Exp3.sim/sim_1/behav/xsim
|
||||
# Command line: wbtcv.exe -mode batch -source D:/Schoolwork/ComputerComposition/Experiments/Exp3/Exp3.sim/sim_1/behav/xsim/xsim.dir/tb_exp3_behav/webtalk/xsim_webtalk.tcl -notrace
|
||||
# Log file: D:/Schoolwork/ComputerComposition/Experiments/Exp3/Exp3.sim/sim_1/behav/xsim/webtalk.log
|
||||
# Journal file: D:/Schoolwork/ComputerComposition/Experiments/Exp3/Exp3.sim/sim_1/behav/xsim\webtalk.jou
|
||||
#-----------------------------------------------------------
|
||||
source D:/Schoolwork/ComputerComposition/Experiments/Exp3/Exp3.sim/sim_1/behav/xsim/xsim.dir/tb_exp3_behav/webtalk/xsim_webtalk.tcl -notrace
|
||||
BIN
Experiments/Exp3/Exp3.sim/sim_1/behav/xsim/xelab.pb
Normal file
BIN
Experiments/Exp3/Exp3.sim/sim_1/behav/xsim/xelab.pb
Normal file
Binary file not shown.
@@ -0,0 +1 @@
|
||||
-wto "0aa8d4d9ab684dbeab8e7342bdb2daf9" --incr --debug "typical" --relax --mt "2" -L "xil_defaultlib" -L "unisims_ver" -L "unimacro_ver" -L "secureip" --snapshot "tb_exp3_behav" "xil_defaultlib.tb_exp3" "xil_defaultlib.glbl" -log "elaborate.log"
|
||||
@@ -0,0 +1 @@
|
||||
Breakpoint File Version 1.0
|
||||
@@ -0,0 +1,139 @@
|
||||
/**********************************************************************/
|
||||
/* ____ ____ */
|
||||
/* / /\/ / */
|
||||
/* /___/ \ / */
|
||||
/* \ \ \/ */
|
||||
/* \ \ Copyright (c) 2003-2013 Xilinx, Inc. */
|
||||
/* / / All Right Reserved. */
|
||||
/* /---/ /\ */
|
||||
/* \ \ / \ */
|
||||
/* \___\/\___\ */
|
||||
/**********************************************************************/
|
||||
|
||||
|
||||
#include "iki.h"
|
||||
#include <string.h>
|
||||
#include <math.h>
|
||||
#ifdef __GNUC__
|
||||
#include <stdlib.h>
|
||||
#else
|
||||
#include <malloc.h>
|
||||
#define alloca _alloca
|
||||
#endif
|
||||
/**********************************************************************/
|
||||
/* ____ ____ */
|
||||
/* / /\/ / */
|
||||
/* /___/ \ / */
|
||||
/* \ \ \/ */
|
||||
/* \ \ Copyright (c) 2003-2013 Xilinx, Inc. */
|
||||
/* / / All Right Reserved. */
|
||||
/* /---/ /\ */
|
||||
/* \ \ / \ */
|
||||
/* \___\/\___\ */
|
||||
/**********************************************************************/
|
||||
|
||||
|
||||
#include "iki.h"
|
||||
#include <string.h>
|
||||
#include <math.h>
|
||||
#ifdef __GNUC__
|
||||
#include <stdlib.h>
|
||||
#else
|
||||
#include <malloc.h>
|
||||
#define alloca _alloca
|
||||
#endif
|
||||
typedef void (*funcp)(char *, char *);
|
||||
extern int main(int, char**);
|
||||
extern void execute_12(char*, char *);
|
||||
extern void execute_13(char*, char *);
|
||||
extern void execute_35(char*, char *);
|
||||
extern void execute_36(char*, char *);
|
||||
extern void execute_37(char*, char *);
|
||||
extern void execute_38(char*, char *);
|
||||
extern void execute_39(char*, char *);
|
||||
extern void execute_40(char*, char *);
|
||||
extern void execute_41(char*, char *);
|
||||
extern void execute_42(char*, char *);
|
||||
extern void execute_43(char*, char *);
|
||||
extern void execute_44(char*, char *);
|
||||
extern void execute_45(char*, char *);
|
||||
extern void execute_46(char*, char *);
|
||||
extern void execute_25(char*, char *);
|
||||
extern void execute_28(char*, char *);
|
||||
extern void execute_29(char*, char *);
|
||||
extern void execute_30(char*, char *);
|
||||
extern void execute_31(char*, char *);
|
||||
extern void execute_32(char*, char *);
|
||||
extern void execute_33(char*, char *);
|
||||
extern void execute_34(char*, char *);
|
||||
extern void execute_4(char*, char *);
|
||||
extern void execute_5(char*, char *);
|
||||
extern void execute_18(char*, char *);
|
||||
extern void execute_19(char*, char *);
|
||||
extern void execute_7(char*, char *);
|
||||
extern void execute_20(char*, char *);
|
||||
extern void execute_21(char*, char *);
|
||||
extern void execute_22(char*, char *);
|
||||
extern void execute_23(char*, char *);
|
||||
extern void vlog_simple_process_execute_0_fast_no_reg_no_agg(char*, char*, char*);
|
||||
extern void execute_9(char*, char *);
|
||||
extern void execute_11(char*, char *);
|
||||
extern void execute_26(char*, char *);
|
||||
extern void execute_27(char*, char *);
|
||||
extern void execute_15(char*, char *);
|
||||
extern void execute_16(char*, char *);
|
||||
extern void execute_17(char*, char *);
|
||||
extern void execute_47(char*, char *);
|
||||
extern void execute_48(char*, char *);
|
||||
extern void execute_49(char*, char *);
|
||||
extern void execute_50(char*, char *);
|
||||
extern void execute_51(char*, char *);
|
||||
extern void vlog_transfunc_eventcallback(char*, char*, unsigned, unsigned, unsigned, char *);
|
||||
funcp funcTab[45] = {(funcp)execute_12, (funcp)execute_13, (funcp)execute_35, (funcp)execute_36, (funcp)execute_37, (funcp)execute_38, (funcp)execute_39, (funcp)execute_40, (funcp)execute_41, (funcp)execute_42, (funcp)execute_43, (funcp)execute_44, (funcp)execute_45, (funcp)execute_46, (funcp)execute_25, (funcp)execute_28, (funcp)execute_29, (funcp)execute_30, (funcp)execute_31, (funcp)execute_32, (funcp)execute_33, (funcp)execute_34, (funcp)execute_4, (funcp)execute_5, (funcp)execute_18, (funcp)execute_19, (funcp)execute_7, (funcp)execute_20, (funcp)execute_21, (funcp)execute_22, (funcp)execute_23, (funcp)vlog_simple_process_execute_0_fast_no_reg_no_agg, (funcp)execute_9, (funcp)execute_11, (funcp)execute_26, (funcp)execute_27, (funcp)execute_15, (funcp)execute_16, (funcp)execute_17, (funcp)execute_47, (funcp)execute_48, (funcp)execute_49, (funcp)execute_50, (funcp)execute_51, (funcp)vlog_transfunc_eventcallback};
|
||||
const int NumRelocateId= 45;
|
||||
|
||||
void relocate(char *dp)
|
||||
{
|
||||
iki_relocate(dp, "xsim.dir/tb_exp3_behav/xsim.reloc", (void **)funcTab, 45);
|
||||
|
||||
/*Populate the transaction function pointer field in the whole net structure */
|
||||
}
|
||||
|
||||
void sensitize(char *dp)
|
||||
{
|
||||
iki_sensitize(dp, "xsim.dir/tb_exp3_behav/xsim.reloc");
|
||||
}
|
||||
|
||||
void simulate(char *dp)
|
||||
{
|
||||
iki_schedule_processes_at_time_zero(dp, "xsim.dir/tb_exp3_behav/xsim.reloc");
|
||||
// Initialize Verilog nets in mixed simulation, for the cases when the value at time 0 should be propagated from the mixed language Vhdl net
|
||||
iki_execute_processes();
|
||||
|
||||
// Schedule resolution functions for the multiply driven Verilog nets that have strength
|
||||
// Schedule transaction functions for the singly driven Verilog nets that have strength
|
||||
|
||||
}
|
||||
#include "iki_bridge.h"
|
||||
void relocate(char *);
|
||||
|
||||
void sensitize(char *);
|
||||
|
||||
void simulate(char *);
|
||||
|
||||
extern SYSTEMCLIB_IMP_DLLSPEC void local_register_implicit_channel(int, char*);
|
||||
extern void implicit_HDL_SCinstatiate();
|
||||
|
||||
extern int xsim_argc_copy ;
|
||||
extern char** xsim_argv_copy ;
|
||||
|
||||
int main(int argc, char **argv)
|
||||
{
|
||||
iki_heap_initialize("ms", "isimmm", 0, 2147483648) ;
|
||||
iki_set_sv_type_file_path_name("xsim.dir/tb_exp3_behav/xsim.svtype");
|
||||
iki_set_crvs_dump_file_path_name("xsim.dir/tb_exp3_behav/xsim.crvsdump");
|
||||
void* design_handle = iki_create_design("xsim.dir/tb_exp3_behav/xsim.mem", (void *)relocate, (void *)sensitize, (void *)simulate, 0, isimBridge_getWdbWriter(), 0, argc, argv);
|
||||
iki_set_rc_trial_count(100);
|
||||
(void) design_handle;
|
||||
return iki_simulate_design();
|
||||
}
|
||||
Binary file not shown.
BIN
Experiments/Exp3/Exp3.sim/sim_1/behav/xsim/xvlog.pb
Normal file
BIN
Experiments/Exp3/Exp3.sim/sim_1/behav/xsim/xvlog.pb
Normal file
Binary file not shown.
44
Experiments/Exp3/Exp3.srcs/sim_1/new/tb_exp3.v
Normal file
44
Experiments/Exp3/Exp3.srcs/sim_1/new/tb_exp3.v
Normal file
@@ -0,0 +1,44 @@
|
||||
`timescale 1ns / 1ps
|
||||
module tb_exp3;
|
||||
reg clk;
|
||||
reg [31:0] Instr;
|
||||
reg RegWr, MemToReg, MemWrEn, ALUBSrc, srcReg;
|
||||
reg [1:0] ExtOp;
|
||||
reg [2:0] AluCtrl;
|
||||
wire Zero;
|
||||
|
||||
Datapath uut (
|
||||
.clk(clk), .Instr(Instr), .RegWr(RegWr), .MemToReg(MemToReg), .MemWrEn(MemWrEn),
|
||||
.ALUBSrc(ALUBSrc), .srcReg(srcReg), .ExtOp(ExtOp), .AluCtrl(AluCtrl), .Zero(Zero)
|
||||
);
|
||||
|
||||
wire [31:0] r1_val = uut.u_Registers.regs[1];
|
||||
wire [31:0] r2_val = uut.u_Registers.regs[2];
|
||||
wire [31:0] r3_val = uut.u_Registers.regs[3];
|
||||
|
||||
initial begin clk = 0; forever #5 clk = ~clk; end
|
||||
|
||||
initial begin
|
||||
$display("----------------- 开始实验三仿真 -----------------");
|
||||
uut.u_Registers.regs[1] = 32'd10;
|
||||
uut.u_Registers.regs[2] = 32'd20;
|
||||
#10;
|
||||
$display("T=%0t: 初始化 r1=10, r2=20", $time);
|
||||
|
||||
$display("\n模拟 add.w r3, r1, r2");
|
||||
Instr = {11'b0, 5'd2, 5'd1, 5'd3};
|
||||
RegWr=1; MemToReg=0; MemWrEn=0; ALUBSrc=0; srcReg=0; ExtOp=2'bxx; AluCtrl=3'b000;
|
||||
#10;
|
||||
$display("T=%0t: 执行 add.w. 期望 r3 = 30. 实际 r3 = %d", $time, r3_val);
|
||||
|
||||
uut.u_DataRAM.ram[120/4] = 32'hDEADBEEF;
|
||||
$display("\n模拟 ld.w r1, 100(r2)");
|
||||
Instr = {12'd100, 5'd2, 5'd1};
|
||||
RegWr=1; MemToReg=1; MemWrEn=0; ALUBSrc=1; srcReg=0; ExtOp=2'b00; AluCtrl=3'b000;
|
||||
#10;
|
||||
$display("T=%0t: 执行 ld.w. 期望 r1 = 0xDEADBEEF. 实际 r1 = %h", $time, r1_val);
|
||||
|
||||
$display("\n----------------- 实验三仿真结束 -----------------");
|
||||
$stop;
|
||||
end
|
||||
endmodule
|
||||
173
Experiments/Exp3/Exp3.xpr
Normal file
173
Experiments/Exp3/Exp3.xpr
Normal file
@@ -0,0 +1,173 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<!-- Product Version: Vivado v2018.1 (64-bit) -->
|
||||
<!-- -->
|
||||
<!-- Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. -->
|
||||
|
||||
<Project Version="7" Minor="36" Path="D:/Schoolwork/ComputerComposition/Experiments/Exp3/Exp3.xpr">
|
||||
<DefaultLaunch Dir="$PRUNDIR"/>
|
||||
<Configuration>
|
||||
<Option Name="Id" Val="0aa8d4d9ab684dbeab8e7342bdb2daf9"/>
|
||||
<Option Name="Part" Val="xc7a35tcsg324-1"/>
|
||||
<Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
|
||||
<Option Name="CompiledLibDirXSim" Val=""/>
|
||||
<Option Name="CompiledLibDirModelSim" Val="$PCACHEDIR/compile_simlib/modelsim"/>
|
||||
<Option Name="CompiledLibDirQuesta" Val="$PCACHEDIR/compile_simlib/questa"/>
|
||||
<Option Name="CompiledLibDirIES" Val="$PCACHEDIR/compile_simlib/ies"/>
|
||||
<Option Name="CompiledLibDirXcelium" Val="$PCACHEDIR/compile_simlib/xcelium"/>
|
||||
<Option Name="CompiledLibDirVCS" Val="$PCACHEDIR/compile_simlib/vcs"/>
|
||||
<Option Name="CompiledLibDirRiviera" Val="$PCACHEDIR/compile_simlib/riviera"/>
|
||||
<Option Name="CompiledLibDirActivehdl" Val="$PCACHEDIR/compile_simlib/activehdl"/>
|
||||
<Option Name="BoardPart" Val=""/>
|
||||
<Option Name="ActiveSimSet" Val="sim_1"/>
|
||||
<Option Name="DefaultLib" Val="xil_defaultlib"/>
|
||||
<Option Name="ProjectType" Val="Default"/>
|
||||
<Option Name="IPOutputRepo" Val="$PCACHEDIR/ip"/>
|
||||
<Option Name="IPCachePermission" Val="read"/>
|
||||
<Option Name="IPCachePermission" Val="write"/>
|
||||
<Option Name="EnableCoreContainer" Val="FALSE"/>
|
||||
<Option Name="CreateRefXciForCoreContainers" Val="FALSE"/>
|
||||
<Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
|
||||
<Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
|
||||
<Option Name="EnableBDX" Val="FALSE"/>
|
||||
<Option Name="DSAVendor" Val="xilinx"/>
|
||||
<Option Name="DSANumComputeUnits" Val="60"/>
|
||||
<Option Name="WTXSimLaunchSim" Val="2"/>
|
||||
<Option Name="WTModelSimLaunchSim" Val="0"/>
|
||||
<Option Name="WTQuestaLaunchSim" Val="0"/>
|
||||
<Option Name="WTIesLaunchSim" Val="0"/>
|
||||
<Option Name="WTVcsLaunchSim" Val="0"/>
|
||||
<Option Name="WTRivieraLaunchSim" Val="0"/>
|
||||
<Option Name="WTActivehdlLaunchSim" Val="0"/>
|
||||
<Option Name="WTXSimExportSim" Val="0"/>
|
||||
<Option Name="WTModelSimExportSim" Val="0"/>
|
||||
<Option Name="WTQuestaExportSim" Val="0"/>
|
||||
<Option Name="WTIesExportSim" Val="0"/>
|
||||
<Option Name="WTVcsExportSim" Val="0"/>
|
||||
<Option Name="WTRivieraExportSim" Val="0"/>
|
||||
<Option Name="WTActivehdlExportSim" Val="0"/>
|
||||
<Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
|
||||
<Option Name="XSimRadix" Val="hex"/>
|
||||
<Option Name="XSimTimeUnit" Val="ns"/>
|
||||
<Option Name="XSimArrayDisplayLimit" Val="1024"/>
|
||||
<Option Name="XSimTraceLimit" Val="65536"/>
|
||||
<Option Name="SimTypes" Val="rtl"/>
|
||||
</Configuration>
|
||||
<FileSets Version="1" Minor="31">
|
||||
<FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1">
|
||||
<Filter Type="Srcs"/>
|
||||
<File Path="$PPRDIR/../Shared/ALU.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../Shared/DataRAM.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../Shared/Ext.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../Shared/Registers.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../Shared/Datapath.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<Config>
|
||||
<Option Name="DesignMode" Val="RTL"/>
|
||||
<Option Name="TopModule" Val="Datapath"/>
|
||||
<Option Name="TopAutoSet" Val="TRUE"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1">
|
||||
<Filter Type="Constrs"/>
|
||||
<Config>
|
||||
<Option Name="ConstrsType" Val="XDC"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1">
|
||||
<File Path="$PSRCDIR/sim_1/new/tb_exp3.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<Config>
|
||||
<Option Name="DesignMode" Val="RTL"/>
|
||||
<Option Name="TopModule" Val="tb_exp3"/>
|
||||
<Option Name="TopLib" Val="xil_defaultlib"/>
|
||||
<Option Name="TopAutoSet" Val="TRUE"/>
|
||||
<Option Name="TransportPathDelay" Val="0"/>
|
||||
<Option Name="TransportIntDelay" Val="0"/>
|
||||
<Option Name="SrcSet" Val="sources_1"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
</FileSets>
|
||||
<Simulators>
|
||||
<Simulator Name="XSim">
|
||||
<Option Name="Description" Val="Vivado Simulator"/>
|
||||
<Option Name="CompiledLib" Val="0"/>
|
||||
</Simulator>
|
||||
<Simulator Name="ModelSim">
|
||||
<Option Name="Description" Val="ModelSim Simulator"/>
|
||||
</Simulator>
|
||||
<Simulator Name="Questa">
|
||||
<Option Name="Description" Val="Questa Advanced Simulator"/>
|
||||
</Simulator>
|
||||
<Simulator Name="Riviera">
|
||||
<Option Name="Description" Val="Riviera-PRO Simulator"/>
|
||||
</Simulator>
|
||||
<Simulator Name="ActiveHDL">
|
||||
<Option Name="Description" Val="Active-HDL Simulator"/>
|
||||
</Simulator>
|
||||
</Simulators>
|
||||
<Runs Version="1" Minor="10">
|
||||
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a35tcsg324-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2018">
|
||||
<Desc>Vivado Synthesis Defaults</Desc>
|
||||
</StratHandle>
|
||||
<Step Id="synth_design"/>
|
||||
</Strategy>
|
||||
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2018"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
</Run>
|
||||
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcsg324-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2018">
|
||||
<Desc>Default settings for Implementation.</Desc>
|
||||
</StratHandle>
|
||||
<Step Id="init_design"/>
|
||||
<Step Id="opt_design"/>
|
||||
<Step Id="power_opt_design"/>
|
||||
<Step Id="place_design"/>
|
||||
<Step Id="post_place_power_opt_design"/>
|
||||
<Step Id="phys_opt_design"/>
|
||||
<Step Id="route_design"/>
|
||||
<Step Id="post_route_phys_opt_design"/>
|
||||
<Step Id="write_bitstream"/>
|
||||
</Strategy>
|
||||
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2018"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
</Run>
|
||||
</Runs>
|
||||
<Board/>
|
||||
</Project>
|
||||
1
Experiments/Exp4/Exp4.ip_user_files/README.txt
Normal file
1
Experiments/Exp4/Exp4.ip_user_files/README.txt
Normal file
@@ -0,0 +1 @@
|
||||
The files in this directory structure are automatically generated and managed by Vivado. Editing these files is not recommended.
|
||||
71
Experiments/Exp4/Exp4.sim/sim_1/behav/xsim/glbl.v
Normal file
71
Experiments/Exp4/Exp4.sim/sim_1/behav/xsim/glbl.v
Normal file
@@ -0,0 +1,71 @@
|
||||
// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
|
||||
`ifndef GLBL
|
||||
`define GLBL
|
||||
`timescale 1 ps / 1 ps
|
||||
|
||||
module glbl ();
|
||||
|
||||
parameter ROC_WIDTH = 100000;
|
||||
parameter TOC_WIDTH = 0;
|
||||
|
||||
//-------- STARTUP Globals --------------
|
||||
wire GSR;
|
||||
wire GTS;
|
||||
wire GWE;
|
||||
wire PRLD;
|
||||
tri1 p_up_tmp;
|
||||
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
|
||||
|
||||
wire PROGB_GLBL;
|
||||
wire CCLKO_GLBL;
|
||||
wire FCSBO_GLBL;
|
||||
wire [3:0] DO_GLBL;
|
||||
wire [3:0] DI_GLBL;
|
||||
|
||||
reg GSR_int;
|
||||
reg GTS_int;
|
||||
reg PRLD_int;
|
||||
|
||||
//-------- JTAG Globals --------------
|
||||
wire JTAG_TDO_GLBL;
|
||||
wire JTAG_TCK_GLBL;
|
||||
wire JTAG_TDI_GLBL;
|
||||
wire JTAG_TMS_GLBL;
|
||||
wire JTAG_TRST_GLBL;
|
||||
|
||||
reg JTAG_CAPTURE_GLBL;
|
||||
reg JTAG_RESET_GLBL;
|
||||
reg JTAG_SHIFT_GLBL;
|
||||
reg JTAG_UPDATE_GLBL;
|
||||
reg JTAG_RUNTEST_GLBL;
|
||||
|
||||
reg JTAG_SEL1_GLBL = 0;
|
||||
reg JTAG_SEL2_GLBL = 0 ;
|
||||
reg JTAG_SEL3_GLBL = 0;
|
||||
reg JTAG_SEL4_GLBL = 0;
|
||||
|
||||
reg JTAG_USER_TDO1_GLBL = 1'bz;
|
||||
reg JTAG_USER_TDO2_GLBL = 1'bz;
|
||||
reg JTAG_USER_TDO3_GLBL = 1'bz;
|
||||
reg JTAG_USER_TDO4_GLBL = 1'bz;
|
||||
|
||||
assign (strong1, weak0) GSR = GSR_int;
|
||||
assign (strong1, weak0) GTS = GTS_int;
|
||||
assign (weak1, weak0) PRLD = PRLD_int;
|
||||
|
||||
initial begin
|
||||
GSR_int = 1'b1;
|
||||
PRLD_int = 1'b1;
|
||||
#(ROC_WIDTH)
|
||||
GSR_int = 1'b0;
|
||||
PRLD_int = 1'b0;
|
||||
end
|
||||
|
||||
initial begin
|
||||
GTS_int = 1'b1;
|
||||
#(TOC_WIDTH)
|
||||
GTS_int = 1'b0;
|
||||
end
|
||||
|
||||
endmodule
|
||||
`endif
|
||||
11
Experiments/Exp4/Exp4.sim/sim_1/behav/xsim/tb_exp4.tcl
Normal file
11
Experiments/Exp4/Exp4.sim/sim_1/behav/xsim/tb_exp4.tcl
Normal file
@@ -0,0 +1,11 @@
|
||||
set curr_wave [current_wave_config]
|
||||
if { [string length $curr_wave] == 0 } {
|
||||
if { [llength [get_objects]] > 0} {
|
||||
add_wave /
|
||||
set_property needs_save false [current_wave_config]
|
||||
} else {
|
||||
send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
|
||||
}
|
||||
}
|
||||
|
||||
run 1000ns
|
||||
16
Experiments/Exp4/Exp4.sim/sim_1/behav/xsim/tb_exp4_vlog.prj
Normal file
16
Experiments/Exp4/Exp4.sim/sim_1/behav/xsim/tb_exp4_vlog.prj
Normal file
@@ -0,0 +1,16 @@
|
||||
# compile verilog/system verilog design source files
|
||||
verilog xil_defaultlib \
|
||||
"../../../../../Shared/ALU.v" \
|
||||
"../../../../../Shared/Controller.v" \
|
||||
"../../../../../Shared/DataRAM.v" \
|
||||
"../../../../../Shared/Datapath.v" \
|
||||
"../../../../../Shared/Ext.v" \
|
||||
"../../../../../Shared/LA32R_CPU.v" \
|
||||
"../../../../../Shared/Registers.v" \
|
||||
"../../../../Exp4.srcs/sim_1/new/tb_exp4.v" \
|
||||
|
||||
# compile glbl module
|
||||
verilog xil_defaultlib "glbl.v"
|
||||
|
||||
# Do not sort compile order
|
||||
nosort
|
||||
12
Experiments/Exp4/Exp4.sim/sim_1/behav/xsim/webtalk.jou
Normal file
12
Experiments/Exp4/Exp4.sim/sim_1/behav/xsim/webtalk.jou
Normal file
@@ -0,0 +1,12 @@
|
||||
#-----------------------------------------------------------
|
||||
# Webtalk v2018.1 (64-bit)
|
||||
# SW Build 2188600 on Wed Apr 4 18:40:38 MDT 2018
|
||||
# IP Build 2185939 on Wed Apr 4 20:55:05 MDT 2018
|
||||
# Start of session at: Thu Jul 3 05:15:51 2025
|
||||
# Process ID: 26536
|
||||
# Current directory: D:/Schoolwork/ComputerComposition/Experiments/Exp4/Exp4.sim/sim_1/behav/xsim
|
||||
# Command line: wbtcv.exe -mode batch -source D:/Schoolwork/ComputerComposition/Experiments/Exp4/Exp4.sim/sim_1/behav/xsim/xsim.dir/tb_exp4_behav/webtalk/xsim_webtalk.tcl -notrace
|
||||
# Log file: D:/Schoolwork/ComputerComposition/Experiments/Exp4/Exp4.sim/sim_1/behav/xsim/webtalk.log
|
||||
# Journal file: D:/Schoolwork/ComputerComposition/Experiments/Exp4/Exp4.sim/sim_1/behav/xsim\webtalk.jou
|
||||
#-----------------------------------------------------------
|
||||
source D:/Schoolwork/ComputerComposition/Experiments/Exp4/Exp4.sim/sim_1/behav/xsim/xsim.dir/tb_exp4_behav/webtalk/xsim_webtalk.tcl -notrace
|
||||
@@ -0,0 +1,12 @@
|
||||
#-----------------------------------------------------------
|
||||
# Webtalk v2018.1 (64-bit)
|
||||
# SW Build 2188600 on Wed Apr 4 18:40:38 MDT 2018
|
||||
# IP Build 2185939 on Wed Apr 4 20:55:05 MDT 2018
|
||||
# Start of session at: Wed Jul 2 00:40:08 2025
|
||||
# Process ID: 26240
|
||||
# Current directory: D:/Schoolwork/ComputerComposition/Experiments/Exp4/Exp4.sim/sim_1/behav/xsim
|
||||
# Command line: wbtcv.exe -mode batch -source D:/Schoolwork/ComputerComposition/Experiments/Exp4/Exp4.sim/sim_1/behav/xsim/xsim.dir/tb_exp4_behav/webtalk/xsim_webtalk.tcl -notrace
|
||||
# Log file: D:/Schoolwork/ComputerComposition/Experiments/Exp4/Exp4.sim/sim_1/behav/xsim/webtalk.log
|
||||
# Journal file: D:/Schoolwork/ComputerComposition/Experiments/Exp4/Exp4.sim/sim_1/behav/xsim\webtalk.jou
|
||||
#-----------------------------------------------------------
|
||||
source D:/Schoolwork/ComputerComposition/Experiments/Exp4/Exp4.sim/sim_1/behav/xsim/xsim.dir/tb_exp4_behav/webtalk/xsim_webtalk.tcl -notrace
|
||||
@@ -0,0 +1,12 @@
|
||||
#-----------------------------------------------------------
|
||||
# Webtalk v2018.1 (64-bit)
|
||||
# SW Build 2188600 on Wed Apr 4 18:40:38 MDT 2018
|
||||
# IP Build 2185939 on Wed Apr 4 20:55:05 MDT 2018
|
||||
# Start of session at: Wed Jul 2 00:39:32 2025
|
||||
# Process ID: 26568
|
||||
# Current directory: D:/Schoolwork/ComputerComposition/Experiments/Exp4/Exp4.sim/sim_1/behav/xsim
|
||||
# Command line: wbtcv.exe -mode batch -source D:/Schoolwork/ComputerComposition/Experiments/Exp4/Exp4.sim/sim_1/behav/xsim/xsim.dir/tb_exp4_behav/webtalk/xsim_webtalk.tcl -notrace
|
||||
# Log file: D:/Schoolwork/ComputerComposition/Experiments/Exp4/Exp4.sim/sim_1/behav/xsim/webtalk.log
|
||||
# Journal file: D:/Schoolwork/ComputerComposition/Experiments/Exp4/Exp4.sim/sim_1/behav/xsim\webtalk.jou
|
||||
#-----------------------------------------------------------
|
||||
source D:/Schoolwork/ComputerComposition/Experiments/Exp4/Exp4.sim/sim_1/behav/xsim/xsim.dir/tb_exp4_behav/webtalk/xsim_webtalk.tcl -notrace
|
||||
@@ -0,0 +1,12 @@
|
||||
#-----------------------------------------------------------
|
||||
# Webtalk v2018.1 (64-bit)
|
||||
# SW Build 2188600 on Wed Apr 4 18:40:38 MDT 2018
|
||||
# IP Build 2185939 on Wed Apr 4 20:55:05 MDT 2018
|
||||
# Start of session at: Thu Jul 3 05:13:39 2025
|
||||
# Process ID: 33472
|
||||
# Current directory: D:/Schoolwork/ComputerComposition/Experiments/Exp4/Exp4.sim/sim_1/behav/xsim
|
||||
# Command line: wbtcv.exe -mode batch -source D:/Schoolwork/ComputerComposition/Experiments/Exp4/Exp4.sim/sim_1/behav/xsim/xsim.dir/tb_exp4_behav/webtalk/xsim_webtalk.tcl -notrace
|
||||
# Log file: D:/Schoolwork/ComputerComposition/Experiments/Exp4/Exp4.sim/sim_1/behav/xsim/webtalk.log
|
||||
# Journal file: D:/Schoolwork/ComputerComposition/Experiments/Exp4/Exp4.sim/sim_1/behav/xsim\webtalk.jou
|
||||
#-----------------------------------------------------------
|
||||
source D:/Schoolwork/ComputerComposition/Experiments/Exp4/Exp4.sim/sim_1/behav/xsim/xsim.dir/tb_exp4_behav/webtalk/xsim_webtalk.tcl -notrace
|
||||
BIN
Experiments/Exp4/Exp4.sim/sim_1/behav/xsim/xelab.pb
Normal file
BIN
Experiments/Exp4/Exp4.sim/sim_1/behav/xsim/xelab.pb
Normal file
Binary file not shown.
@@ -0,0 +1 @@
|
||||
-wto "ae2a6b03df4749b48fa62497cdcfc9a7" --incr --debug "typical" --relax --mt "2" -L "xil_defaultlib" -L "unisims_ver" -L "unimacro_ver" -L "secureip" --snapshot "tb_exp4_behav" "xil_defaultlib.tb_exp4" "xil_defaultlib.glbl" -log "elaborate.log"
|
||||
@@ -0,0 +1 @@
|
||||
Breakpoint File Version 1.0
|
||||
@@ -0,0 +1,144 @@
|
||||
/**********************************************************************/
|
||||
/* ____ ____ */
|
||||
/* / /\/ / */
|
||||
/* /___/ \ / */
|
||||
/* \ \ \/ */
|
||||
/* \ \ Copyright (c) 2003-2013 Xilinx, Inc. */
|
||||
/* / / All Right Reserved. */
|
||||
/* /---/ /\ */
|
||||
/* \ \ / \ */
|
||||
/* \___\/\___\ */
|
||||
/**********************************************************************/
|
||||
|
||||
|
||||
#include "iki.h"
|
||||
#include <string.h>
|
||||
#include <math.h>
|
||||
#ifdef __GNUC__
|
||||
#include <stdlib.h>
|
||||
#else
|
||||
#include <malloc.h>
|
||||
#define alloca _alloca
|
||||
#endif
|
||||
/**********************************************************************/
|
||||
/* ____ ____ */
|
||||
/* / /\/ / */
|
||||
/* /___/ \ / */
|
||||
/* \ \ \/ */
|
||||
/* \ \ Copyright (c) 2003-2013 Xilinx, Inc. */
|
||||
/* / / All Right Reserved. */
|
||||
/* /---/ /\ */
|
||||
/* \ \ / \ */
|
||||
/* \___\/\___\ */
|
||||
/**********************************************************************/
|
||||
|
||||
|
||||
#include "iki.h"
|
||||
#include <string.h>
|
||||
#include <math.h>
|
||||
#ifdef __GNUC__
|
||||
#include <stdlib.h>
|
||||
#else
|
||||
#include <malloc.h>
|
||||
#define alloca _alloca
|
||||
#endif
|
||||
typedef void (*funcp)(char *, char *);
|
||||
extern int main(int, char**);
|
||||
extern void execute_15(char*, char *);
|
||||
extern void execute_16(char*, char *);
|
||||
extern void execute_47(char*, char *);
|
||||
extern void execute_48(char*, char *);
|
||||
extern void execute_49(char*, char *);
|
||||
extern void execute_50(char*, char *);
|
||||
extern void execute_51(char*, char *);
|
||||
extern void execute_52(char*, char *);
|
||||
extern void execute_53(char*, char *);
|
||||
extern void execute_40(char*, char *);
|
||||
extern void execute_41(char*, char *);
|
||||
extern void execute_42(char*, char *);
|
||||
extern void execute_43(char*, char *);
|
||||
extern void execute_44(char*, char *);
|
||||
extern void execute_45(char*, char *);
|
||||
extern void execute_46(char*, char *);
|
||||
extern void execute_4(char*, char *);
|
||||
extern void execute_21(char*, char *);
|
||||
extern void execute_22(char*, char *);
|
||||
extern void execute_30(char*, char *);
|
||||
extern void execute_33(char*, char *);
|
||||
extern void execute_34(char*, char *);
|
||||
extern void execute_35(char*, char *);
|
||||
extern void execute_36(char*, char *);
|
||||
extern void execute_37(char*, char *);
|
||||
extern void execute_38(char*, char *);
|
||||
extern void execute_39(char*, char *);
|
||||
extern void execute_7(char*, char *);
|
||||
extern void execute_8(char*, char *);
|
||||
extern void execute_23(char*, char *);
|
||||
extern void execute_24(char*, char *);
|
||||
extern void execute_10(char*, char *);
|
||||
extern void execute_25(char*, char *);
|
||||
extern void execute_26(char*, char *);
|
||||
extern void execute_27(char*, char *);
|
||||
extern void execute_28(char*, char *);
|
||||
extern void vlog_simple_process_execute_0_fast_no_reg_no_agg(char*, char*, char*);
|
||||
extern void execute_12(char*, char *);
|
||||
extern void execute_14(char*, char *);
|
||||
extern void execute_31(char*, char *);
|
||||
extern void execute_32(char*, char *);
|
||||
extern void execute_18(char*, char *);
|
||||
extern void execute_19(char*, char *);
|
||||
extern void execute_20(char*, char *);
|
||||
extern void execute_54(char*, char *);
|
||||
extern void execute_55(char*, char *);
|
||||
extern void execute_56(char*, char *);
|
||||
extern void execute_57(char*, char *);
|
||||
extern void execute_58(char*, char *);
|
||||
extern void vlog_transfunc_eventcallback(char*, char*, unsigned, unsigned, unsigned, char *);
|
||||
funcp funcTab[50] = {(funcp)execute_15, (funcp)execute_16, (funcp)execute_47, (funcp)execute_48, (funcp)execute_49, (funcp)execute_50, (funcp)execute_51, (funcp)execute_52, (funcp)execute_53, (funcp)execute_40, (funcp)execute_41, (funcp)execute_42, (funcp)execute_43, (funcp)execute_44, (funcp)execute_45, (funcp)execute_46, (funcp)execute_4, (funcp)execute_21, (funcp)execute_22, (funcp)execute_30, (funcp)execute_33, (funcp)execute_34, (funcp)execute_35, (funcp)execute_36, (funcp)execute_37, (funcp)execute_38, (funcp)execute_39, (funcp)execute_7, (funcp)execute_8, (funcp)execute_23, (funcp)execute_24, (funcp)execute_10, (funcp)execute_25, (funcp)execute_26, (funcp)execute_27, (funcp)execute_28, (funcp)vlog_simple_process_execute_0_fast_no_reg_no_agg, (funcp)execute_12, (funcp)execute_14, (funcp)execute_31, (funcp)execute_32, (funcp)execute_18, (funcp)execute_19, (funcp)execute_20, (funcp)execute_54, (funcp)execute_55, (funcp)execute_56, (funcp)execute_57, (funcp)execute_58, (funcp)vlog_transfunc_eventcallback};
|
||||
const int NumRelocateId= 50;
|
||||
|
||||
void relocate(char *dp)
|
||||
{
|
||||
iki_relocate(dp, "xsim.dir/tb_exp4_behav/xsim.reloc", (void **)funcTab, 50);
|
||||
|
||||
/*Populate the transaction function pointer field in the whole net structure */
|
||||
}
|
||||
|
||||
void sensitize(char *dp)
|
||||
{
|
||||
iki_sensitize(dp, "xsim.dir/tb_exp4_behav/xsim.reloc");
|
||||
}
|
||||
|
||||
void simulate(char *dp)
|
||||
{
|
||||
iki_schedule_processes_at_time_zero(dp, "xsim.dir/tb_exp4_behav/xsim.reloc");
|
||||
// Initialize Verilog nets in mixed simulation, for the cases when the value at time 0 should be propagated from the mixed language Vhdl net
|
||||
iki_execute_processes();
|
||||
|
||||
// Schedule resolution functions for the multiply driven Verilog nets that have strength
|
||||
// Schedule transaction functions for the singly driven Verilog nets that have strength
|
||||
|
||||
}
|
||||
#include "iki_bridge.h"
|
||||
void relocate(char *);
|
||||
|
||||
void sensitize(char *);
|
||||
|
||||
void simulate(char *);
|
||||
|
||||
extern SYSTEMCLIB_IMP_DLLSPEC void local_register_implicit_channel(int, char*);
|
||||
extern void implicit_HDL_SCinstatiate();
|
||||
|
||||
extern int xsim_argc_copy ;
|
||||
extern char** xsim_argv_copy ;
|
||||
|
||||
int main(int argc, char **argv)
|
||||
{
|
||||
iki_heap_initialize("ms", "isimmm", 0, 2147483648) ;
|
||||
iki_set_sv_type_file_path_name("xsim.dir/tb_exp4_behav/xsim.svtype");
|
||||
iki_set_crvs_dump_file_path_name("xsim.dir/tb_exp4_behav/xsim.crvsdump");
|
||||
void* design_handle = iki_create_design("xsim.dir/tb_exp4_behav/xsim.mem", (void *)relocate, (void *)sensitize, (void *)simulate, 0, isimBridge_getWdbWriter(), 0, argc, argv);
|
||||
iki_set_rc_trial_count(100);
|
||||
(void) design_handle;
|
||||
return iki_simulate_design();
|
||||
}
|
||||
Binary file not shown.
BIN
Experiments/Exp4/Exp4.sim/sim_1/behav/xsim/xvlog.pb
Normal file
BIN
Experiments/Exp4/Exp4.sim/sim_1/behav/xsim/xvlog.pb
Normal file
Binary file not shown.
43
Experiments/Exp4/Exp4.srcs/sim_1/new/tb_exp4.v
Normal file
43
Experiments/Exp4/Exp4.srcs/sim_1/new/tb_exp4.v
Normal file
@@ -0,0 +1,43 @@
|
||||
`timescale 1ns / 1ps
|
||||
module tb_exp4;
|
||||
reg clk;
|
||||
reg [31:0] Instr;
|
||||
|
||||
LA32R_CPU uut (.clk(clk), .Instr(Instr));
|
||||
|
||||
wire [31:0] r1_val = uut.u_Datapath.u_Registers.regs[1];
|
||||
wire [31:0] r2_val = uut.u_Datapath.u_Registers.regs[2];
|
||||
wire [31:0] r3_val = uut.u_Datapath.u_Registers.regs[3];
|
||||
wire [31:0] r4_val = uut.u_Datapath.u_Registers.regs[4];
|
||||
wire [31:0] r5_val = uut.u_Datapath.u_Registers.regs[5];
|
||||
|
||||
initial begin clk = 0; forever #5 clk = ~clk; end
|
||||
|
||||
initial begin
|
||||
$display("----------------- 开始实验四仿真-----------------");
|
||||
|
||||
Instr = {3'b001, 4'b0, 20'h12345, 5'd1}; #10;
|
||||
$display("执行 lu12i.w r1, 0x12345. 期望 r1=12345000. 实际 r1=%h", r1_val);
|
||||
|
||||
Instr = {3'b001, 4'b0, 20'hABCDE, 5'd2}; #10;
|
||||
$display("执行 lu12i.w r2, 0xABCDE. 期望 r2=abcde000. 实际 r2=%h", r2_val);
|
||||
|
||||
Instr = {3'b000, 7'b0, 7'b0000010, 5'd2, 5'd1, 5'd3}; #10;
|
||||
$display("执行 add.w r3, r1, r2. 期望 r3=be023000. 实际 r3=%h", r3_val);
|
||||
|
||||
Instr = {3'b000, 7'b0, 7'b0000100, 5'd2, 5'd1, 5'd4}; #10;
|
||||
$display("执行 slt r4, r1, r2. 期望 r4=00000000. 实际 r4=%h", r4_val);
|
||||
|
||||
Instr = {3'b000, 7'b0, 7'b0000101, 5'd2, 5'd1, 5'd5}; #10;
|
||||
$display("执行 sltu r5, r1, r2. 期望 r5=00000001. 实际 r5=%h", r5_val);
|
||||
|
||||
Instr = {3'b011, 7'b0, 12'd100, 5'd2, 5'd1}; #10;
|
||||
$display("执行 st.w r1, r2, 100. 将r1的值存入内存");
|
||||
|
||||
Instr = {3'b010, 7'b0, 12'd100, 5'd2, 5'd3}; #10;
|
||||
$display("执行 ld.w r3, r2, 100. 期望 r3=12345000. 实际 r3=%h", r3_val);
|
||||
|
||||
$display("\n----------------- 实验四仿真结束 -----------------");
|
||||
$stop;
|
||||
end
|
||||
endmodule
|
||||
187
Experiments/Exp4/Exp4.xpr
Normal file
187
Experiments/Exp4/Exp4.xpr
Normal file
@@ -0,0 +1,187 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<!-- Product Version: Vivado v2018.1 (64-bit) -->
|
||||
<!-- -->
|
||||
<!-- Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. -->
|
||||
|
||||
<Project Version="7" Minor="36" Path="D:/Schoolwork/ComputerComposition/Experiments/Exp4/Exp4.xpr">
|
||||
<DefaultLaunch Dir="$PRUNDIR"/>
|
||||
<Configuration>
|
||||
<Option Name="Id" Val="ae2a6b03df4749b48fa62497cdcfc9a7"/>
|
||||
<Option Name="Part" Val="xc7a35tcsg324-1"/>
|
||||
<Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
|
||||
<Option Name="CompiledLibDirXSim" Val=""/>
|
||||
<Option Name="CompiledLibDirModelSim" Val="$PCACHEDIR/compile_simlib/modelsim"/>
|
||||
<Option Name="CompiledLibDirQuesta" Val="$PCACHEDIR/compile_simlib/questa"/>
|
||||
<Option Name="CompiledLibDirIES" Val="$PCACHEDIR/compile_simlib/ies"/>
|
||||
<Option Name="CompiledLibDirXcelium" Val="$PCACHEDIR/compile_simlib/xcelium"/>
|
||||
<Option Name="CompiledLibDirVCS" Val="$PCACHEDIR/compile_simlib/vcs"/>
|
||||
<Option Name="CompiledLibDirRiviera" Val="$PCACHEDIR/compile_simlib/riviera"/>
|
||||
<Option Name="CompiledLibDirActivehdl" Val="$PCACHEDIR/compile_simlib/activehdl"/>
|
||||
<Option Name="BoardPart" Val=""/>
|
||||
<Option Name="ActiveSimSet" Val="sim_1"/>
|
||||
<Option Name="DefaultLib" Val="xil_defaultlib"/>
|
||||
<Option Name="ProjectType" Val="Default"/>
|
||||
<Option Name="IPOutputRepo" Val="$PCACHEDIR/ip"/>
|
||||
<Option Name="IPCachePermission" Val="read"/>
|
||||
<Option Name="IPCachePermission" Val="write"/>
|
||||
<Option Name="EnableCoreContainer" Val="FALSE"/>
|
||||
<Option Name="CreateRefXciForCoreContainers" Val="FALSE"/>
|
||||
<Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
|
||||
<Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
|
||||
<Option Name="EnableBDX" Val="FALSE"/>
|
||||
<Option Name="DSAVendor" Val="xilinx"/>
|
||||
<Option Name="DSANumComputeUnits" Val="60"/>
|
||||
<Option Name="WTXSimLaunchSim" Val="9"/>
|
||||
<Option Name="WTModelSimLaunchSim" Val="0"/>
|
||||
<Option Name="WTQuestaLaunchSim" Val="0"/>
|
||||
<Option Name="WTIesLaunchSim" Val="0"/>
|
||||
<Option Name="WTVcsLaunchSim" Val="0"/>
|
||||
<Option Name="WTRivieraLaunchSim" Val="0"/>
|
||||
<Option Name="WTActivehdlLaunchSim" Val="0"/>
|
||||
<Option Name="WTXSimExportSim" Val="0"/>
|
||||
<Option Name="WTModelSimExportSim" Val="0"/>
|
||||
<Option Name="WTQuestaExportSim" Val="0"/>
|
||||
<Option Name="WTIesExportSim" Val="0"/>
|
||||
<Option Name="WTVcsExportSim" Val="0"/>
|
||||
<Option Name="WTRivieraExportSim" Val="0"/>
|
||||
<Option Name="WTActivehdlExportSim" Val="0"/>
|
||||
<Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
|
||||
<Option Name="XSimRadix" Val="hex"/>
|
||||
<Option Name="XSimTimeUnit" Val="ns"/>
|
||||
<Option Name="XSimArrayDisplayLimit" Val="1024"/>
|
||||
<Option Name="XSimTraceLimit" Val="65536"/>
|
||||
<Option Name="SimTypes" Val="rtl"/>
|
||||
</Configuration>
|
||||
<FileSets Version="1" Minor="31">
|
||||
<FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1">
|
||||
<Filter Type="Srcs"/>
|
||||
<File Path="$PPRDIR/../Shared/ALU.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../Shared/Controller.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../Shared/DataRAM.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../Shared/Datapath.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../Shared/Ext.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../Shared/Registers.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../Shared/LA32R_CPU.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<Config>
|
||||
<Option Name="DesignMode" Val="RTL"/>
|
||||
<Option Name="TopModule" Val="LA32R_CPU"/>
|
||||
<Option Name="TopAutoSet" Val="TRUE"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1">
|
||||
<Filter Type="Constrs"/>
|
||||
<Config>
|
||||
<Option Name="ConstrsType" Val="XDC"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1">
|
||||
<File Path="$PSRCDIR/sim_1/new/tb_exp4.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<Config>
|
||||
<Option Name="DesignMode" Val="RTL"/>
|
||||
<Option Name="TopModule" Val="tb_exp4"/>
|
||||
<Option Name="TopLib" Val="xil_defaultlib"/>
|
||||
<Option Name="TopAutoSet" Val="TRUE"/>
|
||||
<Option Name="TransportPathDelay" Val="0"/>
|
||||
<Option Name="TransportIntDelay" Val="0"/>
|
||||
<Option Name="SrcSet" Val="sources_1"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
</FileSets>
|
||||
<Simulators>
|
||||
<Simulator Name="XSim">
|
||||
<Option Name="Description" Val="Vivado Simulator"/>
|
||||
<Option Name="CompiledLib" Val="0"/>
|
||||
</Simulator>
|
||||
<Simulator Name="ModelSim">
|
||||
<Option Name="Description" Val="ModelSim Simulator"/>
|
||||
</Simulator>
|
||||
<Simulator Name="Questa">
|
||||
<Option Name="Description" Val="Questa Advanced Simulator"/>
|
||||
</Simulator>
|
||||
<Simulator Name="Riviera">
|
||||
<Option Name="Description" Val="Riviera-PRO Simulator"/>
|
||||
</Simulator>
|
||||
<Simulator Name="ActiveHDL">
|
||||
<Option Name="Description" Val="Active-HDL Simulator"/>
|
||||
</Simulator>
|
||||
</Simulators>
|
||||
<Runs Version="1" Minor="10">
|
||||
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a35tcsg324-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2018">
|
||||
<Desc>Vivado Synthesis Defaults</Desc>
|
||||
</StratHandle>
|
||||
<Step Id="synth_design"/>
|
||||
</Strategy>
|
||||
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2018"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
</Run>
|
||||
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcsg324-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2018">
|
||||
<Desc>Default settings for Implementation.</Desc>
|
||||
</StratHandle>
|
||||
<Step Id="init_design"/>
|
||||
<Step Id="opt_design"/>
|
||||
<Step Id="power_opt_design"/>
|
||||
<Step Id="place_design"/>
|
||||
<Step Id="post_place_power_opt_design"/>
|
||||
<Step Id="phys_opt_design"/>
|
||||
<Step Id="route_design"/>
|
||||
<Step Id="post_route_phys_opt_design"/>
|
||||
<Step Id="write_bitstream"/>
|
||||
</Strategy>
|
||||
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2018"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
</Run>
|
||||
</Runs>
|
||||
<Board/>
|
||||
</Project>
|
||||
31
Experiments/Shared/ALU.v
Normal file
31
Experiments/Shared/ALU.v
Normal file
@@ -0,0 +1,31 @@
|
||||
module ALU(
|
||||
input [31:0] a,
|
||||
input [31:0] b,
|
||||
input [2:0] AluCtrl,
|
||||
output reg [31:0] AddResult,
|
||||
output reg Zero
|
||||
);
|
||||
parameter ADD = 3'b000;
|
||||
parameter SUB = 3'b001;
|
||||
parameter AND = 3'b010;
|
||||
parameter OR = 3'b011;
|
||||
parameter NOR = 3'b100;
|
||||
parameter SLT = 3'b101;
|
||||
parameter SLTU = 3'b110;
|
||||
parameter PASSB= 3'b111;
|
||||
|
||||
always @(*) begin
|
||||
case (AluCtrl)
|
||||
ADD: AddResult = a + b;
|
||||
SUB: AddResult = a - b;
|
||||
AND: AddResult = a & b;
|
||||
OR: AddResult = a | b;
|
||||
NOR: AddResult = ~(a | b);
|
||||
SLT: AddResult = ($signed(a) < $signed(b)) ? 32'd1 : 32'd0;
|
||||
SLTU: AddResult = (a < b) ? 32'd1 : 32'd0;
|
||||
PASSB:AddResult = b;
|
||||
default: AddResult = 32'hxxxxxxxx;
|
||||
endcase
|
||||
Zero = (AddResult == 32'd0);
|
||||
end
|
||||
endmodule
|
||||
43
Experiments/Shared/Controller.v
Normal file
43
Experiments/Shared/Controller.v
Normal file
@@ -0,0 +1,43 @@
|
||||
module Controller(
|
||||
input [31:15] Opcode_in,
|
||||
output reg RegWr,
|
||||
output reg MemToReg,
|
||||
output reg MemWrEn,
|
||||
output reg ALUBSrc,
|
||||
output reg srcReg,
|
||||
output reg [1:0] ExtOp,
|
||||
output reg [2:0] AluCtrl
|
||||
);
|
||||
parameter OP_RTYPE = 3'b000, OP_LU12I = 3'b001, OP_LOAD = 3'b010, OP_STORE = 3'b011;
|
||||
|
||||
parameter FUNC_ADD = 7'b0000010, FUNC_SLT = 7'b0000100, FUNC_SLTU= 7'b0000101;
|
||||
|
||||
wire [2:0] main_op = Opcode_in[31:29];
|
||||
wire [6:0] func_op = Opcode_in[21:15];
|
||||
|
||||
always @(*) begin
|
||||
RegWr=0; MemToReg=0; MemWrEn=0; ALUBSrc=0; srcReg=0; ExtOp=2'bxx; AluCtrl=3'bxxx;
|
||||
|
||||
case(main_op)
|
||||
OP_RTYPE: begin
|
||||
RegWr=1; ALUBSrc=0;
|
||||
case(func_op)
|
||||
FUNC_ADD: AluCtrl = 3'b000;
|
||||
FUNC_SLT: AluCtrl = 3'b101;
|
||||
FUNC_SLTU: AluCtrl = 3'b110;
|
||||
default: ;
|
||||
endcase
|
||||
end
|
||||
OP_LU12I: begin
|
||||
RegWr=1; ALUBSrc=1; ExtOp=2'b10; AluCtrl=3'b111;
|
||||
end
|
||||
OP_LOAD: begin
|
||||
RegWr=1; MemToReg=1; ALUBSrc=1; ExtOp=2'b00; AluCtrl=3'b000;
|
||||
end
|
||||
OP_STORE: begin
|
||||
MemWrEn=1; ALUBSrc=1; srcReg=1; ExtOp=2'b00; AluCtrl=3'b000;
|
||||
end
|
||||
default: ;
|
||||
endcase
|
||||
end
|
||||
endmodule
|
||||
12
Experiments/Shared/DR.v
Normal file
12
Experiments/Shared/DR.v
Normal file
@@ -0,0 +1,12 @@
|
||||
module DR(
|
||||
input clk,
|
||||
input WE,
|
||||
input [31:0] DataIn,
|
||||
output reg [31:0] DataOut
|
||||
);
|
||||
always @(posedge clk) begin
|
||||
if (WE) begin
|
||||
DataOut <= DataIn;
|
||||
end
|
||||
end
|
||||
endmodule
|
||||
17
Experiments/Shared/DataRAM.v
Normal file
17
Experiments/Shared/DataRAM.v
Normal file
@@ -0,0 +1,17 @@
|
||||
module DataRAM(
|
||||
input clk,
|
||||
input MemWrEn,
|
||||
input [31:0] addr,
|
||||
input [31:0] data_in,
|
||||
output [31:0] data_out
|
||||
);
|
||||
reg [31:0] ram[0:1023];
|
||||
wire [9:0] word_addr = addr[11:2];
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (MemWrEn) begin
|
||||
ram[word_addr] <= data_in;
|
||||
end
|
||||
end
|
||||
assign data_out = ram[word_addr];
|
||||
endmodule
|
||||
24
Experiments/Shared/Datapath.v
Normal file
24
Experiments/Shared/Datapath.v
Normal file
@@ -0,0 +1,24 @@
|
||||
module Datapath(
|
||||
input clk,
|
||||
input [31:0] Instr,
|
||||
input RegWr,
|
||||
input MemToReg,
|
||||
input MemWrEn,
|
||||
input ALUBSrc,
|
||||
input srcReg,
|
||||
input [1:0] ExtOp,
|
||||
input [2:0] AluCtrl,
|
||||
output Zero
|
||||
);
|
||||
wire [31:0] busA_out, busB_out, ext_out, alu_in_b, alu_result, ram_data_out, reg_write_data;
|
||||
wire [4:0] rj = Instr[9:5];
|
||||
wire [4:0] rk_or_rd_store = Instr[14:10];
|
||||
wire [4:0] rd_write = Instr[4:0];
|
||||
|
||||
Registers u_Registers(.clk(clk), .RegWr(RegWr), .Ra(rj), .Rb(srcReg ? Instr[4:0] : rk_or_rd_store), .Rw(rd_write), .busW(reg_write_data), .busA(busA_out), .busB(busB_out));
|
||||
Ext u_Ext(.DataIn(Instr), .ExtOp(ExtOp), .DataOut(ext_out));
|
||||
assign alu_in_b = ALUBSrc ? ext_out : busB_out;
|
||||
ALU u_ALU(.a(busA_out), .b(alu_in_b), .AluCtrl(AluCtrl), .AddResult(alu_result), .Zero(Zero));
|
||||
DataRAM u_DataRAM(.clk(clk), .MemWrEn(MemWrEn), .addr(alu_result), .data_in(busB_out), .data_out(ram_data_out));
|
||||
assign reg_write_data = MemToReg ? ram_data_out : alu_result;
|
||||
endmodule
|
||||
23
Experiments/Shared/Ext.v
Normal file
23
Experiments/Shared/Ext.v
Normal file
@@ -0,0 +1,23 @@
|
||||
module Ext(
|
||||
input [31:0] DataIn,
|
||||
input [1:0] ExtOp,
|
||||
output [31:0] DataOut
|
||||
);
|
||||
wire [31:0] imm12, imm16, imm20, imm26;
|
||||
assign imm12 = {{20{DataIn[21]}}, DataIn[21:10]};
|
||||
assign imm16 = {{14{DataIn[25]}}, DataIn[25:10], 2'b0};
|
||||
assign imm20 = {DataIn[24:5], 12'b0};
|
||||
assign imm26 = {{4{DataIn[9]}}, DataIn[9:0], DataIn[25:10], 2'b0};
|
||||
|
||||
reg [31:0] temp_DataOut;
|
||||
always @(*) begin
|
||||
case (ExtOp)
|
||||
2'b00: temp_DataOut = imm12;
|
||||
2'b01: temp_DataOut = imm16;
|
||||
2'b10: temp_DataOut = imm20;
|
||||
2'b11: temp_DataOut = imm26;
|
||||
default: temp_DataOut = 32'hxxxxxxxx;
|
||||
endcase
|
||||
end
|
||||
assign DataOut = temp_DataOut;
|
||||
endmodule
|
||||
14
Experiments/Shared/LA32R_CPU.v
Normal file
14
Experiments/Shared/LA32R_CPU.v
Normal file
@@ -0,0 +1,14 @@
|
||||
module LA32R_CPU(
|
||||
input clk,
|
||||
input [31:0] Instr
|
||||
);
|
||||
wire RegWr, MemToReg, MemWrEn, ALUBSrc, srcReg;
|
||||
wire [1:0] ExtOp;
|
||||
wire [2:0] AluCtrl;
|
||||
wire Zero;
|
||||
|
||||
Controller u_Controller(.Opcode_in(Instr[31:15]), .RegWr(RegWr), .MemToReg(MemToReg), .MemWrEn(MemWrEn),
|
||||
.ALUBSrc(ALUBSrc), .srcReg(srcReg), .ExtOp(ExtOp), .AluCtrl(AluCtrl));
|
||||
Datapath u_Datapath(.clk(clk), .Instr(Instr), .RegWr(RegWr), .MemToReg(MemToReg), .MemWrEn(MemWrEn),
|
||||
.ALUBSrc(ALUBSrc), .srcReg(srcReg), .ExtOp(ExtOp), .AluCtrl(AluCtrl), .Zero(Zero));
|
||||
endmodule
|
||||
19
Experiments/Shared/PC.v
Normal file
19
Experiments/Shared/PC.v
Normal file
@@ -0,0 +1,19 @@
|
||||
module PC(
|
||||
input clk,
|
||||
input rst,
|
||||
input pc_inc,
|
||||
input [31:0] offset,
|
||||
output reg [31:0] PCdata
|
||||
);
|
||||
always @(posedge clk or posedge rst) begin
|
||||
if (rst) begin
|
||||
PCdata <= 32'd0;
|
||||
end else begin
|
||||
if (pc_inc) begin
|
||||
PCdata <= PCdata + 4;
|
||||
end else begin
|
||||
PCdata <= PCdata + offset;
|
||||
end
|
||||
end
|
||||
end
|
||||
endmodule
|
||||
25
Experiments/Shared/Registers.v
Normal file
25
Experiments/Shared/Registers.v
Normal file
@@ -0,0 +1,25 @@
|
||||
module Registers(
|
||||
input clk,
|
||||
input RegWr,
|
||||
input [4:0] Ra, Rb, Rw,
|
||||
input [31:0] busW,
|
||||
output [31:0] busA,
|
||||
output [31:0] busB
|
||||
);
|
||||
reg [31:0] regs[0:31];
|
||||
integer i;
|
||||
initial begin
|
||||
for (i = 0; i < 32; i = i + 1) begin
|
||||
regs[i] = 32'd0;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (RegWr && (Rw != 5'd0)) begin
|
||||
regs[Rw] <= busW;
|
||||
end
|
||||
end
|
||||
|
||||
assign busA = (Ra == 5'd0) ? 32'd0 : regs[Ra];
|
||||
assign busB = (Rb == 5'd0) ? 32'd0 : regs[Rb];
|
||||
endmodule
|
||||
Reference in New Issue
Block a user